ee241 - spring 2003
TRANSCRIPT
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UC Berkeley EE241 J. Rabaey. B. Nikolić
EE241 - Spring 2003Advanced Digital Integrated Circuits
Lecture 8Differential Logic
Pass-Transistor Logic
UC Berkeley EE241 J. Rabaey. B. Nikolić
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Cascode Voltage Switch LogicVDD
VSS
PDN1
Out
VDD
VSS
PDN2
Out
AABB
M1 M2
Cascode Voltage Switch Logic (CVSL)
Sometimes called Differential Cascode Voltage Switch Logic (DCVSL)
UC Berkeley EE241 J. Rabaey. B. Nikolić
CVSL Properties
� Static� No static power, except DSL leakage� Process and supply tolerance is an
issue with DSL
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Using Ordered BDDs
BDD = Binary Decision Diagrams
UC Berkeley EE241 J. Rabaey. B. Nikolić
Push-Pull Cascode Logic
Gieseke et al, U.S. Patent 5,023,480 June 1991.
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DSL Differential Split-Level Logic
UC Berkeley EE241 J. Rabaey. B. Nikolić
But … Consumes Static Power
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Simulation Results for Different Adders
UC Berkeley EE241 J. Rabaey. B. Nikolić
Cascode Non-Threshold Logic
Use negative feedbackto limit VOLCapacitors used fordecoupling
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Optimizing the Intrinsic RC-Delay
UC Berkeley EE241 J. Rabaey. B. Nikolić
Progressive Sizing
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Uniform versus Progressive Sizing
Uniform
kn-1
kn-1
N
Non-uniform
1
k
k2
kn-1
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Sizing Models
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Case Study
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Example: Progressive Scaling ofNMOS Devices in DOMINO CMOS
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Pass-Transistor Logic Families
UC Berkeley EE241 J. Rabaey. B. Nikolić
Pass-Transistor Logic
Inpu
ts
Switch
Network
OutOut
A
B
B
B
• N transistors
• No static consumptionA
B
BF = AB
0
• Transistor implementationusing NMOS
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UC Berkeley EE241 J. Rabaey. B. Nikolić
Pass-Transistor Logic Families
UC Berkeley EE241 J. Rabaey. B. Nikolić
NMOS-only switch
A =2.5V
B
C = 2.5V
CL
A = 2.5 V
C = 2.5 V
BM2
M1
Mn
Threshold voltage loss causesstatic power consumption
VB does not pull up to 2.5V, but 2.5- VTN
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NMOS-Only Switch
0 0.5 1 1.5 20.0
1.0
2.0
3.0
Time,ns
Volta
ge,VVDD
IN
Outx
0.5µm/0.25µm0.5µm/0.25µm
1.5µm/0.25µm xOut
In
UC Berkeley EE241 J. Rabaey. B. Nikolić
Transmission Gate Based Logic
A B
C
C
A B
C
C
B
CL
C = 0 V
A = 2.5V
C = 2.5V
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Transmission Gate XOR
A
B
F
B
A
B
B
M1
M2
M3/M4
UC Berkeley EE241 J. Rabaey. B. Nikolić
Transmission Gate Adder
A
B
P
Ci
VDDA
A A
VDD
Ci
A
P
AB
VDD
VDD
Ci
Ci
Co
S
Ci
P
P
P
P
P
Sum Generation
Carry Generation
Setup
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Transmission Gate LogicConditional CellConditional Sum Adder
2-way MUXes
Rothermel, JSSC 89
UC Berkeley EE241 J. Rabaey. B. Nikolić
TG Resistance
0.0 1.0 2.00
10
20
30
Res
ista
nce
,oh
ms
Rn
Rp
Rn || Rp
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Level Restoring
M2
M1
Mn
Mr
OutA
B
VDDVDDLevel Restorer
X
UC Berkeley EE241 J. Rabaey. B. Nikolić
Level Restorer
=1.50/0.25
0100 200 300 400 500
0.0
1.0
2.0
3.0
W/Lr =1.0/0.25 W/Lr =1.25/0.25
W/Lr
W/Lr =1.75/0.25
Vo
lt ag
e,V
Time, ps
Sizing oflevel restorer
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Single-Ended Level Restoring
OutputInput
Feedback Inverter
Output InverterLevel Restoration
Transistor
UC Berkeley EE241 J. Rabaey. B. Nikolić
Differential Level Restoring
Differential NMOS Logic Tree
f f
Inputs
Inputs
Different level restoration leads to different logic families
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Different Restoration Schemes
Differential NMOS Logic Tree
f f
Inputs
Inputs
Swing-Restored Pass-Transistor Logic
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Swing-Restored Pass-Transistor Logic
Parameswar, et alCICC’94, JSSC 6/96
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Other Level-Restoring Schemes
Differential NMOS Logic Tree
f f
Inputs
Inputs
Differential NMOS Logic Tree
ff
Inputs
Inputs
Energy Economized Pass-TransistorLogic
DCVS with Pass Gates(DCVS-PG)
UC Berkeley EE241 J. Rabaey. B. Nikolić
ComplementaryPass-Transistor Logic (CPL)
F
F
Pass-Transistor
Network
Pass-TransistorNetwork
AABB
AABB
Complementary
• Complementary functions• Reduced number of logic levels• Much less transistors than CMOS• Fast – reduced load• Complementary inputs – complementary outputs• VT drop – several solutions
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CPL
Level restoration
Yano et al, CICC’89, JSSC 4/90
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CPL
Same topology of networksJust different signal arrangements
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Complementary Pass-Transistor Logic(CPL)
AA
S S
A A
B
B
C
C
SS(a) (b)
B
B
Q Qb
n1 n2
n4n3
XORSum
nFET logic
network
- Fast
- VT drop
- Efficient
implementation
of arithmetic
UC Berkeley EE241 J. Rabaey. B. Nikolić
CPL
Out
VDD
VDD
5V
VDD
0V 5V
0V
WATCH OUT FOR LEAKAGE CURRENTS
Yano – CICC’89: 0.5µm CMOS with dual thresholds
VTh = 0V
VTh = 0.4V
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Karnaugh Maps
A
B
0 0
0 1
C1 C2
A
A
B A
BA ⋅
C2 C1
A
A
B
BA ⋅
C2 C1
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CPL vs. CMOS
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Skewing Output Inverter
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CPL vs. CMOS
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Differential vs. Single-Ended
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CPL vs. Supply Voltage
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Leap Cell Library
Yano et al, CICC’94, JSSC 6/96
Goal: Implement full logic functionality with small libraryRely on automated design methodology
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Various Logic Functions of theLean Library
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LEAP Comparison
UC Berkeley EE241 J. Rabaey. B. Nikolić
LEAP Performance
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DCVSPG(Differential Cascode Voltage Logic – with Pass Gate)
DCVS DCVSPG
UC Berkeley EE241 J. Rabaey. B. Nikolić
DCVSPG
Delay dependence on PMOS width and load, with NMOS constant
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DCVSPG Latch
UC Berkeley EE241 J. Rabaey. B. Nikolić
Double Pass-Transistor Logic(DPL)
A
B
A B B A
VDD
B
A
OO
A
B
A B BA
B
A
OO
B
A
B A B A
B
A
A B
A B
AND/NAND
XOR/XNOR
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Designing DPL Gates
A
A
B
BA ⋅
C2
C1
A B
B
C3
C4A
B
0 0
0 1
C3 C4
C1
C2
UC Berkeley EE241 J. Rabaey. B. Nikolić
Designing DPL Gates (2)
A
B
0 1
1 0
C1 C2
C3
C4
A
B
0 1
1 0
C1 C2
C3
C4
A
BA ⊕
A
B
B B
A
A
B
C1
C2C3
C4
A
BA ⊕
A
B
B B
A
A
B
C1 C2
C3C4
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Applications of DPL
1.5ns 32-bit ALUin 0.25µm CMOS
Full adder:
Suzuki, ISSCC’93JSSC 11/93
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XOR Gate Comparison
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DPL Delay vs. Supply
UC Berkeley EE241 J. Rabaey. B. Nikolić
Applications of DPL54x54bit DPL Multiplier in 4.4ns
Ohkubo, CICC’94, JSSC 5/95
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4:2 Compressor in DPL
UC Berkeley EE241 J. Rabaey. B. Nikolić
Adder in DPL
4-bit adder 8-bit adder
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Adder in DPL
108-bitfinal adder
UC Berkeley EE241 J. Rabaey. B. Nikolić
Redundancy in DPL
AND
Elimination of Redundant Branches
B B A A
A BGND
1
GND
B B A A
A BVDD VDD
NAND
AND
B B A
A GND GND
NAND
B B A
A VDDVDD
DPLL 2L 3L 4L
A
B
0 0
0 1
L4 L3
L2
L1
DVL - Oklobdzija, Duchene, VLSI-TSA’95
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Redundancy in DPL
AND
Signal Rearrangement
B B A A
A BGND GND
B B A A
A BVDD VDD
NAND
AND
B B
A GND
NAND
B B B
VDD
B
A
DPL
A
B
0 0
0 1
L4 L3
L2
L1
UC Berkeley EE241 J. Rabaey. B. Nikolić
Comparison of Logic Styles
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Comparison of Logic Styles
Zimmermann, Fichtner, JSSC 7/97
UC Berkeley EE241 J. Rabaey. B. Nikolić
Comparison of Logic Styles
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Comparison of Logic Styles
UC Berkeley EE241 J. Rabaey. B. Nikolić
Results