ee241 - spring 2003bwrcs.eecs.berkeley.edu/classes/icdesign/ee241_s03/... · cdr : dual-loop...

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UC Berkeley EE241 J. Zerbe / B. Nikolic

EE241 - Spring 2003Advanced Digital Integrated Circuits

Lecture 26High-Speed Links

Guest Lecturer : Jared Zerbe, Rambus Inc.


Agenda : High Speed Links

l Backgroundl The Probleml Key componentsl Resultsl Future areas

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Background : Where Links?

l Chip-2-Chipl Cablesl Single connectorl Backplanes

Increasingcomplexity


What Makes a Link?l Signaling: sending and receiving the information

l Clocking: Determining which bit is which

RxTx

RTERM

Channel

RTERM

tbit /2

1 0 0 01 01

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Spanning A Broad Spacel Inverter.........to……..DSL modeml Metrics

» Speed» Latency» Electrical environment» Power & area» Volume


Serial Link Signaling Over Backplanes

l Very challenging signaling environment» Almost no signal left at receiver

serdes

BackplaneLinecard Linecard

serdes

Signal at Tx Signal at Rx

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The Backplane Environment

l The problem is there are many sources of Z…and thus many possible sources of reflections

Back plane connector

Line card trace

Package

On-chip parasitic (termination resistance and device loading capacitance)

Line card via

Back plane trace

Backplane via


SI drives Si above 3Gb/s

l What’s your perspective? 3G? 6G? 10G?l We must understand much more about the

problem to operate above 3Gb/s

1.00E-03

1.00E-02

1.00E-01

1.00E+00

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

Frequency (GHz)

1.00E-03

1.00E-02

1.00E-01

1.00E+00

0.0 0.5 1.0 1.5 2.0 2.5 3.0

Frequency (GHz)

1.00E-03

1.00E-02

1.00E-01

1.00E+00

0.0 1.0 2.0 3.0 4.0 5.0

Frequency (GHz)

3G view 6G view 10G view

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Key Problems In The Backplanel Backgroundl The Problem

» Loss» Reflections» Crosstalk» Skew

l Key componentsl Resultsl Future areas


Problems : Material Loss

l PCB Loss : skin & dielectric loss» Skin Loss ∝ √f» Dielectric loss ∝ f : a bigger issue at higher f

FR4 dielectric, 8 mil wide and 1m long 50 Ohm strip line

0

0.2

0.4

0.6

0.8

1

1.0E+06 1.0E+07 1.0E+08 1.0E+09 1.0E+10

Frequency, Hz

Att

enua

tion

Total loss

Conductor loss

Dielectric loss

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Problems : Reflections

l Sources of Reflections : Z - Discontinuities» PCB Z mismatch» Connector Z mismatch» Vias (through) Z mismatch» Device parasitics - effective Z mismatch

Z1 Z2

Z2 Z

DC via Conn via BP

Energy flow into junction = transmitted +

reflected energy


Discontinuities + Energy @ F= Resonance

Roger BP, Length: 1.5", T/S: 29/264 mil

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

0.00 0.78 1.56 2.33 3.11 3.89 4.67 5.45 6.22 7.00

Frequency, GHz

Tra

nsf

er fu

nct

ion

(s21

)

meas

sim

Resonant notch due to via stub

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Reflections From Via Stubs

l Additional sources of reflections : stubs» Vias - particularly on thick backplanes» Package plating stubs

Top layer signaling results in large via stub


Signaling With Stubs:DRAM example

receivers

0

1

1” stubs w/ 1” spacing

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Shortening Stubs & Tuning Z

0

1


Problems : Crosstalkl Many sources

» On-chip» Package» PCB traces» Inside connector

l Differential signaling can help» Minimize xtalk generation & make effects common-mode

l Both NEXT & FEXT» NEXT very destructive if RX and TX pairs are adjacent

– Full swing-TX coupling into attenuated RX signal– Effect on SNR is multiplied by signal loss

» Simple solution : group RX/TX pairs in connector

» NEXT typically 3-6%, FEXT typically 1-3%

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Problems : Skewl A router can have

» 1,000’s, even 10,000’s of links» Sources from any linecard to any switch-card port» Clocking and delay matching is a nightmare!

l Matching skew across all switch card inputs would make backplane routing impossible» Make each link independent and use CDR

– Don’t need to worry about clock or data skews across BP

» Still need to match skews within differential pair– Otherwise can have modal conversion loss & EMI problems


A Complex System

PCB only

PCB + Connectors

PCB, Connectors,Via stubs & Devices

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Key Components In Linksl Backgroundl The Probleml Key components

» Loss : Equalization, MLS» Reflections : Termination, active methods» Skew : Clocking and PLLs, CDRs» TX & RX Design

l Resultsl Future areas


Equalization For Loss :Goal is to Flatten Response

l Channel is band-limitedl Equalization : boost high-frequencies relative to

lower frequencies

+

=

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Receive Linear Equalizerl Amplifies high-frequencies

attenuated by the channell Pre-decisionl Digital or Analog FIR filterl Issues

» Also amplifies noise!» Precision» Tuning delays (if analog)» Setting coefficients

– Adaptive algorithms such asLMS

…

WL-1

DDD

WLW1

+

H(s)

freq


Transmit Linear Equalizerl Attenuates low-frequencies

» Need to be careful about output amplitude : limited output power

– If you could make bigger swings, you would

– EQ really attenuates low-frequencies to match high frequencies Also FIR filter : D/A converter

l Can get better precision than RXl Issues

» How to set EQ weights?» Doesn’t help loss at f

H(s)

freq

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Transmit Linear Equalizer :Single Bit Operation

0.0 0.3 0.6 0.9 1.2-0.3

-0.1

0.1

0.3

0.5

0.7UnequalizedEqualization PulseEnd of Line

time (ns)

Vo

ltag

e


Example : 5Gbps Over 26” FR4With No Equalization

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Example : 5Gbps Over 26” FR4Under Equalized


Example : 5Gbps Over 26” FR4Over Equalized

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Example : 5Gbps Over 26” FR4Correct Tx Equalization


Decision Feedback Equalizationl Don’t invert channel…

just remove ISI» Know ISI because already

received symbols» Doesn’t amplify noise» Has error accumulation problem

– Less of an issue in linkswhere random noise small

l Requires a feed-forward equalizer for precursor ISI» Reshapes pulse to eliminate

precursor

-

FIR filter

Decision (slicer)

FIR filter

Feed-forward EQ

Feed-back EQ

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Alternate Approaches : Multi-Level Signaling

l Binary (NRZ) is 2-PAMl 2-PAM uses 2-levels to send

one bit per symboll Signaling rate = 2 x Nyquist

l 4-PAM uses 4-levels to send 2 bits per symbol

l Each level has 2 bit valuel Signaling rate = 4 x Nyquist

00

01

11

10

1

0

1

0

Note : both can be either single -ended or differential


When Does 4-PAM Make Sense?

l First order : slope of S21» 3 eyes : 1 eye = 10db» loss > 10db/octave : 4-PAM

should be considered

0.0 1.0 2.0 3.0 4.0

Nyquist Frequency (GHz)

|H(f

)|

-20db

-40db

-60db

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Alternate Approaches : Simultaneous BiDirectional

l Two signals at halfspeed» Makes sense if b/w need

equal in both directions

l Issues» Getting ideal timing

between TX & RX is tough

Vlinedrv

VrefVrefH (shared)VrefL (shared)

rcvr

receive signal

transmit signal

VlineVref

(Vline - Vref)+ve

-ve

VrefH

VrefL

Fixed VrefL= Vdd – 1.5*Vswing





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Minimizing Reflections : The Viasl Minimizing via stubs

» Thinner PCBs are better…but sometimes impossible

» Counter-boring» Blind vias» SMT technology

» All are costly1.1x - 2x

counter-boredblind via


Vias : Effect of Counter-boring

l Counter-boring top layer takes it from highest-loss to lowest-loss & reduces resonance

Layer3 no Counter-boringLayer3 with Counter-boring

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Minimizing Reflections :Termination Design

l On-chip termination » Bondwire & pad capacitance part of the channel

… instead of a stub (which rings)


Minimizing Reflections :Terminating AC or DC

l With differential signals can terminate to the compliment» Potential power savings

– Can build a higher-Z system

» What sets common-mode?– Usually TX– Demands large RX common-

mode range

» AC-coupled & AC-term– Can set common mode with

parallel large R’s

RAC Rx

RxRAC

VTT

VTT

RCM

RCM

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Minimizing Reflections : FET Terminations

IV-characteristicof two-element resistor

[Dally]


Minimizing Reflections : Active Techniques

l Use sampled data stream to actively cancel reflections

Sampler

VariableDelay

CDR

PhaseMixer

UP/DOWNRx Data

RX EQ

Tap Weights

Tap Select

Normal Rx Path

... 5

13

Tap Mux

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Clocking : Terminology

Needs CDR!

Can do with orwithout CDR

Poulton’99

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What’s a CDR?Clock and Data Recovery

l Recovering clock from the data» Can recover clock completely, or just phase» Just phase: need a reference clock

l Why?» Allows separate xtals on different boards» Don’t have to match trace lengths, delays» Easier system design / clock distribution

l Why Not» Expensive: takes area, power» Requires coding or transition density or training sequence

– 8b10b coding uses 10b to xfer 8b of info; 20% BW loss


CDR : PLL Techniquel Simple bang-bang PLL

» Observe data with phase detector» Filter Early/Late & drive VCO

l Advantages» Good frequency range» Low Jitter

l Challenges» Phase offset» Lock time - startup sequence» Loss of lock - coding dependant» How to integrate?

Multiple PLLs –Harmonic locking problems

Incoming Data

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CDR : Dual-Loop Techniquel Combination of

» Core PLL provides multiple phases at frequency

» Periphery DLL mixes and make desired phase

l Advantages» Avoids harmonic locking

– Easy to integrate many» Rapid CDR lock time» CDR very stable

– Can even ‘hold’ phase state

l Challenges» Limited Freq offset from PLL» Jitter not as low as PLL

PDLow Pass

Filter VCO

RefClk

÷ N

Phase MixersCDRLogic

RXData

RClk


CDR : Coding & Transition Densityl CDR requires transition density to keep lockl AC - coupling requires DC-balancel Coding as solutionl Typical code : 8b10b

» 8 bits into the link => 10 bits on the wires» Raw data rate must be 25% faster than effective data rate

– 6.25Gb raw for 5Gb effective

» 8b10b code guarantees– DC balance– Transition density : 2 transitions every 10 bits– Reserved codes, control characters

» CDR doesn’t mean you must have 8b10b– 64/66 or scrambling can give transition density

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Transmitter Design

l Critical components: Sync, Mux, Tx

l Design issues:» Slew rate control vs ISI, jitter» Output current and impedance control

l Clock and Driver power dissipation

Data Generation Pre-Driver Driver

Tx50Ω

Sync MuxEncoder

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Output Drivers


SSTLVTT

50Ω

25Ω

VTT

50Ω 50Ω

25Ω

VTT

Io = +/- 8mA

Io = +/- 16mAVTT=0.45*VDDQ (center term)

VTT

VTT

Zo = 50Ω

Zo = 50Ω

Class-I

Class-II

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LVDS

100Ω

Io = +/- 3.5mA

VCM=1.25V (set by driver)

Zo = 100Ω

Zo = 100Ω

RxTx

AC terminated @ receiver


CML - direct coupled

Io = - 21mA

Zo = 50Ω

Zo = 50Ω

RxTx

Double-terminated

50Ω 50Ω

VD D VDD

on-chip

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CML - AC coupled

Io = - 21mA

Zo = 50Ω

Zo = 50Ω

RxTx

Supports different

50Ω 50Ω

VD D VTERM

on-chipVterms


Physical signal swings

dc-coupled

2.0V

1.5V

1.0V

0.5V

0V

CTT

HSTL

GTLGTL+

LVDS 2

CML 2

RSLSSTL_31

1 swing @ receiver input, driver swing will be higher.

BTL

2 differential signalling

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Simple Transmitter

l DDR: send a bit per clock edgel Critical issues:

» 50% duty cycle» Tbit > 4-FO4

Data_O

Data_E1 2 3 4 50

10

20

30

bit time (normalized to FO4)

outp

ut p

ulse

wid

th c

losu

re (

%)


Fastest Transmitter» Off chip time constant smaller than on chip:ÞGenerate current pulse at the output

» Limited only by the output capacitance

out

out_bRTERM

RTERM

x 8

d0 d0

ck3

D0 D1 D2data(ck0)

clock(ck3)

0.50 0.60 0.70 0.80 0.90 1.000.0

10.0

20.0

30.0

Bit-width (#FO-4)

% e

ye c

losu

re

» Limiting time constant 25-Ω*Cpad

» Cpad = 8*Cdriver + Cesd

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Simple Receiver

l Preconditioning stage: filter/integrate rectify CMl Latch makes decision (4-FO4)l DAC can be used to compensate offsets

in

ref

clk

A latch

D/A

clk


Fastest Receiver

l Use multiple input receivers» Simplest 2, more complex 4-8» Decouples Tbit from latch resolution» Leverage high input impedance amplifiers

D0 D1 D2 D7

clk0

clk1

clk2

clk3

Ring Oscillatorclk0 clk1 clk2 clk3

ck0

ck1

ck2

ck3

ck4

din

To A

mpl

ifie

rs

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Measured Link Resultsl Backgroundl The Probleml Key componentsl Resultsl Future areas


Characterization Systeml Multiple

» Connectors» Backplane materials» Trace lengths» Layers/via lengths» Via technology

l These slides» 20” Trace length» FR4 non counter-bored» Nelco 6000 2-step

counter-bored» Top & bottom layers

l 20” = 14” Backplane+ 2 x 3” Linecards

l Linecards always FR4

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0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

Nyauist Frequency (GHz)

S21

FR420top

FR420bot

FR410top

FR410bot

Measured S21’s: FR4 no C-Bore


26” FR4 Bot 3.125Gbps, 2P no EQ

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26” FR4 Bot 3.125Gbps, 2P w/EQ


26” FR4 Bot 6.4Gbps, 2P w/3G EQ

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26” FR4 Bot 6.4Gbps, 2P w/EQ


26” FR4 Top 6.4Gbps, 2P w/EQ

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26” FR4 Top 6.4Gbps, 4P w/EQ


0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

Nyquist Frequency (GHz)

S21

NCB20top

NCB20bot

NCB10top

NCB10bot

Measured S21’s : N6k C-Bore

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26” N6k-cb Top 6.4Gbps, 2P


10G Eyes & System Margin Shmoos

l 3”/20”/3” = 26” Trace + 2 Connectorsl Tested to BER < 10-15

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Future Areas for Workl Backgroundl The Probleml Key componentsl Resultsl Future areas

» System Issues vs. Frequency» Link performance, power & area» Circuit challenges


Vo

ltag

eT

imin

g

1G100M 3G 5G 10G

Return current path control

SSN / Ground bounce

Cross talk

Via stub effect

Connector stub

Impedance matching across transmission line

Timing variation across all pins

Timing variation between clock and data

Timing variation due to coupling

Reflection control

Intra pair skew

Device I/O capacitance act as LPF

Inter symbol interference

Skin effect

Dielectric loss

ISI Jitter

System Issues vs. Frequency

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Link Performance vs. Time

Walker’02


Link Efficiency: Gb/W, Gb/mm2

Walker’02(ISSCC’92-2001)

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Next Challengesl Improving PSR of all ckts in the pathl Integration of many links

» Low power, area, portable solutions

l Control of complex architectures» Deal with loss, reflections and crosstalk

l Offset and mismatch» Both voltage and time

l Lots of opportunity for design!

ee241 - spring 2003bwrcs.eecs.berkeley.edu/classes/icdesign/ee241_s03/... · cdr : dual-loop...

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