2/18/2016 EE101 Quiz exam preparation Guide Dear EE101 students,

Your Quiz exam is on 2/24/2017 from 2-3:50PM in SOS B2 (http://web-app.usc.edu/web/its/spaces/room-finder/details.php?id=104). It has 98 seats and you please be seated in alternate columns.

Everything taught before the Quiz including the material covered in lectures on 2/21/2017 and 2/23/2017 is included for the Quiz. Following is a suggested list of topics and typical set of problems. Actual exam may be different. 1. From EE101_Lec1.pdf Binary Numbers, number conversions, Number ranges, Memory Maps 1.1 210 = _______ (state in decimal), 1 Mega Byte = 2x bytes, then X = ______ (10/20/30/other) How big is the range C400 hex to C7FF hex ____________ state the size as a power of 2 and also as a decimal number. Divide this into two equal ranges and state them in hex.

1.2 Natural range: 7000-7999 is a natural range of a thousand in decimal system. It could be the volume 7 of a 10-volume encyclopedia where the 10 volumes are each 1000 pages in size. If we need to refer to the page 4321, we pick up the volume #4 which goes from 4000-4999. Let us do the same in binary. The encyclopedia has 220 = 1 Mega pages divided into 16 volumes each of 216 pages. You are looking for the page BADF3 hex. Which volume you pick up and what is the range of page numbers in that volume in hex?

1.3 Slides 19 and 20 as reproduced below

1.4 Slides 22, 23

2. From EE101_Lec2.pdf 2.1 Readable logic, Slides 3, 4

2.2 Building larger gates from smaller gates. Linear cascade vs. a tree structure, number of small gates needed, number of levels, etc. Slides 16-19

2.3 DeMorgan’s theorem and bubble manipulation (slides 20-30):

3. From EE101_Lec3.pdf and Adders.pdf all pages 3.1 incrementer design: Using three half adders and an inverter, design a 4-bit incrementer

3.2 Produce Y = X+2 using one inverter and as few HA (Half Adders) as possible. X is a 4-bit number and Y is a 5-bit number.

3.3 Learn to understand addition in binary (either addition of two variables or addition of a variable and a constant). Learn to understand that the final carry output from a 4-bit adder represents S4 (the sum bit 4 with a weight of 24 = 16) in unsigned number addition. 3.4 Constant addition should provide opportunity for a lot of simplification. Please practice.

4. EE101Lecture4.pdf 4.1 Single Variables Theorems (very simple)

4.2 Minterms mi

4.3

5. EE101Lecture3.pdf

5.1 Is the above division of 16 combinations of the 4 bits in the 4-bit signed number system into two parts (8 combinations for 8 positive numbers and 8 combinations for 8 negative numbers) true for (a) sign-magnitude representation for signed numbers (b) 2’s complement representation for signed numbers (c) both of the above Answer 5.2 Learn to quickly represent a given decimal signed number in each of the two systems

5.2.1 How do you represent (-40) (minus forty) in 8-bit sign-magnitude system? How do you represent (-40) (minus forty) in 8-bit 2’s complement system? Answer: First consider how to represent +40 in 8-bit binary system 40 = 32 + 8 = 25 + 23 = 00101000 Hence -40 in 8-bit sign-magnitude system = 10101000 To find -40 representation in 2’s complement system, start with the +40 representation, flip 1’s and 0’s (i.e. called 1’s complementation) and then add a 1. 1’s complement of 00101000 = 11010111 Add a 1: 11010111 + 1 = 11011000 You can verify the value using the positional weights for the 2’s complement system (MSB has negative weight and the rest of the bits have positive weights) Value of 11011000 = 1 * 27 + 1 * 26 + 0 * 25 + 1 * 24 + 1 * 23 + 0 * 22 + 0 * 21 + 0 * 20 = -128 + 64 + 16 + 8 = - 128 + 88 = +40 5.2.2 -4 is represented as 1100 in 4-bit 2’s complement system. Sign-extend and represent it as an 8-bit number in 2’s complement system 1100 = 11111100

5.3

5.3.1 State the range of signed numbers that can be represented using a 4-bit system (a) in sign-magnitude representation of signed numbers and (b) in 2’s complement representation of signed numbers Answer: (a) -7 to +7 (b) -8 to +7

5.3.2 Do the same for a 6-bit system Answer: (a) -31 to ++31 (b) -32 to +31

5.4 Can you use the 4-bit ripple-carry adder (RCA) (also called Carry propagate Adder CPA) below to add (a) two unsigned 4-bit numbers (b) two signed 4-bit numbers represented in sign-magnitude representation of signed numbers (c) two signed 4-bit numbers represented in 2’s complement representation of signed numbers

Note: If you are adding two signed numbers, then the two number can be both positive or both negative or one positive and one negative. Assume that the result is also a 4-bit number. In finite-number system, both the summands and the sum are represented in the same number of bits. A 32-bit processor represents A, B, and S all in 32 bits in S = A + B. Obviously overflow is bound to occur. If A and B are both positive and are holding the largest number that they can hold in 32 bits, there is no way that S can hold the sum because S is also 32 bits in size. Overflow indicator in the addition of unsigned numbers is the out-going carry (C32 in the 32-bit system). Overflow indicator in the addition of signed numbers represented in 2’s complement system is the “V” output which is produced by XORing the incoming carry (C31) and the out-going carry (C32). This is not covered in the course yet. So the job of the CPU is to perform the addition A + B and deposit the result in S and make a complete report of what happened in the “FLAG register” (also called “Processor Status Word (PSW)” or “Condition Code Register (CCR)”). If the programmer wants to take any action, he can take action on C by doing BCS Target (Branch to Target if Carry Set) or BVS Target (Branch to Target if V is Set).

Answer: You can use the above 4-bit adder to add (a) two unsigned numbers and (b) two signed numbers represented in 2’s complement representation system. But you cannot use it for adding two signed numbers represented in sign-magnitude system. The 2’s complement representation for signed numbers was designed to make it suitable to add two signed numbers without having to pre-inspect if they are both of same sign or of different signs (and if they were different signs to subtract the magnitude of the smaller from the magnitude of the larger and associate sign of the result magnitude to the sign of the larger of the two).

5.5. Get to know to subtract too.

5.5.1 Statement: To do (A – B), we do (A+B’+1) for signed numbers represented in 2’s complement representation system or for unsigned numbers also? Answer: This was not taught in detail but interestingly, the procedure applies to both. Of course the result may be wrong if it is supposed to be wrong and a report will be made in the Flag register by the CPU hardware. 5.5.2 Is it necessary to do (A+B’+1) all in one stroke or may we do [(A+(B’+1)]. Answer: In one stroke. If you do it parts you can cause spurious overflow. This will be discussed in later chapters.

5.6 Overflow detection in subtraction.

6. From EE101Lecture5.pdf , EE101Lecture6.pdf , EE101Lecture7.pdf , EE101Lecture8.pdf , Boolean algebra, 2-3 variable theorems, SOP and POS, min terms and Max terms. K-Maps, 2-level implementations

While T8 ( over distribution) is easy to understand and accept based on our high school algebra, in Boolean algebra, we need understand that T8’ ( over distribution) is also true.

One way to understand this is expand the (X+Y).(X+Z) i.e . multiply it out

7. From EE101Lecture9.pdf , EE101Lecture10.pdf , EE101Lecture11.pdf , EE101Lecture12.pdf Decoders and Multiplexers 7.1 From EE101Lecture9.pdf

For functions with many minterms, a smaller NOR gate can be used instead of a large OR gate.

7.2 From EE101Lecture11.pdf Decoders with enables Classnotes page 133

Classnotes page 135 Please practice filling this page

7.3 Building larger Decoders from smaller decoders (classnotes pages 136-138) EE101Lecture11.pdf

7.3.1 How many 2 to 4 decoders does it take to build a 4 to 16 decoder using the above tree decoding method. Answer: Consider 4-bit zip code for mailing and think that the Head Post Office in Washington DC decodes the top two bits and sends it to one of the four state Post Offices. The states decode the next two bits and send to the four customers. So we need 5 decoders in two levels.

7.3.1.A If we add another level of 2-4 decoders how many you need and what size is the overall decoder? Answer: The 16 outputs of the current design will act as enables for the next level

7.4 From EE101Lecture12.pdf Mux design from gates: from page 146 of the classnotes

7.5 Larger Mux with smaller muxes: From the classnotes page 151

7.6 wider mux with smaller muxes From the classnotes page 148

8. From EE101Lecture15.pdf Please see EE101Lecture15_sol.pdf and also EE101_Dis_6_Sol.pdf Expect about 2 to 3 questions in this area. 9. From material to be covered on 2/21/2017 and 2/23/2017 Best of luck! Gandhi