ece 331 – digital system design · 2014-12-02 · spring 2011 ece 331 - digital system design 2...
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ECE 331 – Digital System Design
Counters
(Lecture #20)
The slides included herein were taken from the materials accompanying
Fundamentals of Logic Design, 6th Edition, by Roth and Kinney,
and were used with permission from Cengage Learning.
Spring 2011 ECE 331 - Digital System Design 2
Counters
● A counter is a sequential circuit (aka. finite state machine) that cycles through a fixed sequence of states.
● The state of the counter is stored in Flip-Flops.
● An n-bit counter
– has n Flip-Flops
– can cycle through at most 2n states.
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Counters
00
10
0111010110
000 001111
011100101
2-bit Counter
3-bit Counter
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Counters
2-bit Counter
3-bit Counter
00
01
10
using only 3 states
using only 5 states
010
101 011
000
110
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Binary Counters
● An n-bit binary counter is a counter that cycles through all 2n states in ascending (or descending) order.
010110
000 001111
011100101
3-bit Binary Counter
Cycles through all 8 states
in ascending order
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Binary Counters: Design
1.Draw a state graph that specifies the desired sequence of the counter.
2.Construct a state table from the state graph.
One Flip-Flop for each bit in the state.
3.Derive a K-map from the state table for each Flip-Flop input.
Select the type of Flip-Flop to be used.
4.Determine the input equation(s) for each Flip-Flop.
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Binary Counters: Design
Example: State Table (using D FF)
Present State Next State FF Inputs
C B A C+ B+ A+ DC DB DA
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 1 0 1
1 0 1 1 1 0
1 1 0 1 1 1
1 1 1 0 0 0
Q+ = D
CharacteristicEquation:
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Binary Counters: Design
Example: K-maps (for D FF inputs)
Spring 2011 ECE 331 - Digital System Design 9
Binary Counters: Design
Example: Circuit Diagram (using D FF)
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Binary Counters: Design
Example: State Table (using T FF)
Q+ = T xor Q
CharacteristicEquation:
Present State Next State FF Inputs
C B A C+ B+ A+ TC TB TA
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 1 0 1
1 0 1 1 1 0
1 1 0 1 1 1
1 1 1 0 0 0
Excitation Table:
Q Q+ T
0 0 0
0 1 1
1 0 1
1 1 0
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Binary Counters: Design
Example: K-maps (for T FF inputs)
Spring 2011 ECE 331 - Digital System Design 12
Binary Counters: Design
Example: Circuit Diagram (using T FF)
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Binary Up-Down Counters
What constraints must be placed on the U and D control signals?
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Binary Up-Down Counters
Spring 2011 ECE 331 - Digital System Design 15
Loadable Counter with Enable
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Counters: Design
1.Draw a state graph that specifies the desired sequence of the counter.
2.Construct a state table from the state graph.
One Flip-Flop for each bit in the state.
3.Derive a K-map from the state table for each Flip-Flop input.
Select the type of Flip-Flop to be used.
4.Determine the input equation(s) for each Flip-Flop.
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Counters: Design
Example:
Design the following counter using D Flip-Flops.
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Counters: Design
Example: State Table (using D FF)
Present State Next State FF Inputs
C B A C+ B+ A+ DC DB DA
0 0 0 1 0 0
0 0 1 x x x
0 1 0 0 1 1
0 1 1 0 0 0
1 0 0 1 1 1
1 0 1 x x x
1 1 0 x x x
1 1 1 0 1 0D = Q+
ExcitationEquation:
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Counters: Design
Example: K-maps (for D FF inputs)
DC DB DA
Spring 2011 ECE 331 - Digital System Design 20
Counters: Design
Example: Circuit Diagram (using D FF)
Spring 2011 ECE 331 - Digital System Design 21
Counters: Design
Example:
Design the following counter using T Flip-Flops.
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Counters: Design
Example: State Table (using T FF)
Present State Next State FF Inputs
C B A C+ B+ A+ TC TB TA
0 0 0 1 0 0
0 0 1 x x x
0 1 0 0 1 1
0 1 1 0 0 0
1 0 0 1 1 1
1 0 1 x x x
1 1 0 x x x
1 1 1 0 1 0T = Q xor Q+
ExcitationEquation:
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Counters: Design
Example: K-maps (for T FF inputs)
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Counters: Design
Example: K-maps (for T FF inputs)
We could derive TC , TB , and TA directly from the state table,
but it is often more convenient to plot next-state maps
showing C+, B+, and A+ as functions of C, B, and A, and then
derive TC , TB , and TA from these maps.
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Counters: Design
Example: Circuit Diagram (using T FF)
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Counters: Design
Example: Next States (for T FF inputs)
Although the original state table for the counter is not
completely specified, the next states of states 001, 101,
and 110 have been specified in the process of
completing the circuit design
110101
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Counters: Design
Example:
Design the following counter using JK Flip-Flops.
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Counters: Design
Example: Using JK Flip-Flops
Excitation Table:
Q Q+ J K
0 0 0 x
0 1 1 x
1 0 x 1
1 1 x 0
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Counters: Design
Example: State Table (using JK FF)
Present State Next State FF Inputs
C B A C+ B+ A+ JC KC JB KB JA KA
0 0 0 1 0 0
0 0 1 x x x
0 1 0 0 1 1
0 1 1 0 0 0
1 0 0 1 1 1
1 0 1 x x x
1 1 0 x x x
1 1 1 0 1 0
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Counters: Design
Example: K-maps (for JK FF inputs)
Spring 2011 ECE 331 - Digital System Design 31
Counters: Design
Example: Circuit Diagram (using JK FF)
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Questions?