ECE 331 – Digital System Design

Flip-Flops and Registers

(Lecture #18)

The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6th Edition, by Roth and Kinney,

and were used with permission from Cengage Learning.

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Material to be covered …

Chapter 11: Sections 6 – 8

Chapter 12: Sections 1 – 2

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Flip-Flops

(continued)

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An S-R flip-flop is similar to an S-R latch in that S = 1 sets the Q output to 1, and R = 1 resets the Q output to 0.

The essential difference is that the flip-flop has a clock input, and the Q output can change only after an active clock edge.

SR Flip-Flop

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Operation summary: S = R = 0 no state change S = 1, R = 0 set Q to 1 (after active Ck edge) S = 0, R = 1 reset Q to 0 (after active Ck edge) S = R = 1 not allowed

SR Flip-Flop

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SR Flip-Flop (master-slave)

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SR Flip-Flop: Timing Diagram

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The J-K flip-flop is an extended version of the S-R flip-flop. The J-K flip-flop has three inputs – J, K, and the clock (CK). The J input corresponds to S, and K corresponds to R.

Unlike the S-R flip-flop, a 1 input may be applied simultaneously to J and K, in which case the flip-flop changes state (i.e. toggles) after the active clock edge.

JK Flip-Flop

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JK Flip-Flop

}Q+ = Q

}Q+ = 0

}Q+ = 1

}Q+ = Q'

set

reset

store

toggle

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JK Flip-Flop (master-slave)

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JK Flip-Flop: Timing Diagram

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The T flip-flop, also called the toggle flip-flop, is frequently used in building counters. It has a T input and a clock input.

When T = 1 the flip-flop changes state after the active edge of the clock. When T = 0, no state change occurs.

T Flip-Flop

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Q+ = T'Q + TQ' = Q T

T Flip-Flop

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T Flip-Flop: Timing Diagram

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Building a T Flip-Flop

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Asynchronous Control Signals

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Asynchronous Control Signals: Timing Diagram

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D FF with Clock Enable

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Registers

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Several D flip-flops may be grouped together with a common clock to form a register. Because each flip-flop can store one bit of information, a register with n D flip-flops can store n bits of information.

A load signal can be ANDed with the clock to enable and disable loading the registers.

A better approach is to use registers with clock enables if they are available.

Registers

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Register: 4 bits

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Transferring data between registers is a common operation in digital systems.

Data can be transferred from the output of one of two registers into a third register using tri-state buffers.

Data Transfer between Registers

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Data Transfer between Registers

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Register with Tri-state Output

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Data Transfer using Tri-state Bus

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A shift register is a register in which binary data can be stored and shifted either left or right. The data is shifted according to the applied shift signal; often there is a left shift signal and a right shift signal.

A shift register must be constructed using flip-flops (i.e. edge-triggered devices); it cannot be constructed using latches or gated-latches (i.e. level-sensitive devices).

Shift Register

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Shift Register: 4 bits

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Shift Register (4 bits): Timing Diagram

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8-bit SI SO Shift Register

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8-bit Shift Register: Timing Diagram

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4-bit PI PO Shift Register

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4-bit PI PO Shift Register: Operation

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4-bit PI PO Shift Register: Timing Diagram

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Parallel Adder with Accumulator

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In computer circuits, it is frequently desirable to store one number in a register (called an accumulator) and add a second number to it, leaving the result stored in the register.

Parallel Adder with Accumulator

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n-bit Parallel Adder with Accumulator

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Before addition in the previous circuit can take place, the accumulator must be loaded with X. This can be accomplished in several ways. The easiest way is to first clear the accumulator using the asynchronous clear inputs on the flip-flops, and then put the X data on the Y inputs to the adder and add the accumulator in the normal way.

Alternatively, we could add multiplexers at the accumulator inputs so that we could select either the Y input data or the adder output to load into the accumulator.

Loading the Accumulator

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Adder Cell with Multiplexer

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Questions?