ECE 331 – Digital System Design

Latches and Flip-Flops

(Lecture #17)

The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6th Edition, by Roth and Kinney,

and were used with permission from Cengage Learning.

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Material to be covered …

Chapter 11: Sections 1 – 7

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Brief introductionto

Sequential Logic Circuits

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Sequential switching circuits have the property that the output depends not only on the present input but also on the past sequence of inputs.

In effect, these circuits must be able to “remember” something about the past history of the inputs in order to produce the present output.

We say a circuit has feedback if the output of one of the gates is connected back into the input of another gate in the circuit so as to form a closed loop.

Sequential Logic Circuits

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Sequential Logic Circuits

CombinationalLogicCircuit Memory

inputsoutputs

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Basic Memory Elements

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Basic Memory Elements Latch

Clock input is level sensitive. Output can change multiple times during a clock

cycle. Output changes while clock is active.

Flip Flop Clock input is edge sensitive. Output can change only once during a clock

cycle. Output changes on clock transition.

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Basic Memory Elements

Both latches and flip flops use feedback to achieve “memory”.

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Feedback Circuit with 2 Stable States

What is the problem with this circuit?

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Set-Reset (SR) Latch

P

NOR gates

Feedback

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SR Latch: Behavior

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SR Latch: Behavior

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S R Q+

0 0 Q

0 1 0

1 0 1

1 1 Not allowed

• If S = 1 (Set), Q+ = 1

• If R = 1 (Reset), Q+ = 0

• If S = R = 0, Q+ = Q (no change)

• S = R = 1 is not allowed.

SR Latch: Behavior

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P ≠ Q′

SR Latch: Improper Operation

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SR Latch: Symbolalways complementary

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SR Latch: Timing Diagram

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SR Latch: Characteristic Equation

Characteristic Equation: Q+ = S + R'.Q (S.R = 0)

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SR Latch: using NAND gates

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A gated D latch has two inputs – a data input (D) and a gate input (G). The D latch can be constructed from an S-R latch and additional logic gates.

When G = 1, the value of D is passed to Q.

When G = 0, the Q output holds the last value of D (no state change).

This type of latch is also referred to as a transparent latch.

Gated D Latch

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Gated D Latch: Circuit and Timing

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Gated D Latch: Symbol and Truth Table

No invalid inputs!

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Gated D Latch: Characteristic Equation

Characteristic Equation: Q+ = G'.Q + G.D

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Gated D Latch: using NAND gates

S'

R'

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A D flip-flop has two inputs, D (data) and Ck (clock). The small arrowhead on the flip-flop symbol identifies the clock input. Unlike the D latch, the flip-flop output changes only in response to the clock, not to a change in D.

If the output can change in response to a 0 to 1 transition on the clock input, we say that the flip-flop is triggered on the rising edge (or positive edge) of the clock.

If the output can change in response to a 1 to 0 transition of the clock input, we say that the flip-flop is triggered on the falling edge (or negative edge) of the clock. An inversion bubble on the clock input indicates a falling-edge trigger.

D Flip-Flop (edge-triggered)

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Q+ = DCharacteristic Equation

D Flip-Flop

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D Flip-Flop: Timing Diagram

Which clock edge is the D flip-flop triggered on?

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D Flip-Flop (master-slave)

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D Flip-Flop: Timing Diagram

Which clock edge is the D flip-flop triggered on?

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D Flip-Flop: Setup and Hold Times

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D Flip-Flop: Minimum Clock Period

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Questions?