dsp c5000 chapter 9 understanding and programming the multi-channel buffered serial port (mcbsp)...

DSP C5000DSP C5000

Chapter 9Chapter 9

Understanding and Programming the Understanding and Programming the Multi-channel Buffered Serial Port Multi-channel Buffered Serial Port

(McBSP)(McBSP)

Copyright © 2003 Texas Instruments. All rights reserved.Copyright © 2003 Texas Instruments. All rights reserved.

Copyright © 2003 Texas Instruments. All rights reserved.

ESIEE, Slide 2

OutlineOutline

Application of McBSPApplication of McBSP

McBSP on McBSP on

C5416 and C5510C5416 and C5510

Differences between C5416 and C5510Differences between C5416 and C5510

ReferencesReferences

Configuration with CConfiguration with CSLSL


ESIEE, Slide 3

Application of McBSPApplication of McBSP McBSP = Multichannel Buffered Serial PortMcBSP = Multichannel Buffered Serial Port

Direct interface to industry-standard codecs, Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially analog interface chips (AICs), and other serially connected A/D - D/A and serial devices.connected A/D - D/A and serial devices.

Direct connection to other C5000 devices,Direct connection to other C5000 devices, Usually works in connection with DMA Usually works in connection with DMA

EF01

E23A

D6C5

Input or Output buffer Serial device Data Clock Frame Sync

McBSP DMA

Int./Ext. Memory


ESIEE, Slide 4

Audio System using DMA and McBSPAudio System using DMA and McBSP

Codec DSP

DD//AA DDMMAA

Sample Ready

AA//DD DDMMAA

MMeemm

MMeemm SSPP

SSPP

AApppplliiccaattiioonn Buffers Ready

Let’s take a closer look at how the buffers are organized... Let’s take a closer look at how the buffers are organized...


ESIEE, Slide 5

Ping-Pong BuffersPing-Pong Buffers

In order to make the application lessIn order to make the application lessreal-time critical, the input is double real-time critical, the input is double bufferedbuffered

These buffers are called ping-pong These buffers are called ping-pong buffersbuffers

The configuration is that of a twoThe configuration is that of a twoframe circular bufferframe circular buffer

First fill one buffer, then fill the other,First fill one buffer, then fill the other,then switch back to the firstthen switch back to the first

DDMMAA

ppiinngg__RRXX

ppoonngg__RRXX

What about the output buffers?What about the output buffers?


ESIEE, Slide 6

The Flow 1 of 4The Flow 1 of 4

What needs to happen to the DMA Channels?What needs to happen to the DMA Channels?

DDMMAA

ping_RX

pong_RX pong_TX

ping_TX

DMA INT

DMA INT

PING_TO_PONG

Application

DDMMAA


ESIEE, Slide 7


DDMMAA DDMMAA

ping_RX

pong_RX pong_TX

ping_TX

DMA INT

DMA INT

PING_TO_PONG

Application

What buffers can the application use to process?What buffers can the application use to process?


ESIEE, Slide 8


DDMMAA DDMMAA

ping_RX

pong_RX pong_TX

ping_TX

DMA INT

DMA INT

PING_TO_PONG

Application

How do we know when new buffers are ready?How do we know when new buffers are ready?


ESIEE, Slide 9


DDMMAA DDMMAA

ping_RX

pong_RX ppoonngg__TTXX

ping_TX

DMA INT

DMA INT

PING_TO_PONG

Application

PONG_TO_PING

DMA INT

DMA INT

And everything starts over…on to the hardware!!And everything starts over…on to the hardware!!


ESIEE, Slide 10

McBSP on C5416 and C5510McBSP on C5416 and C5510

C5416 and C5510 McBSP are very C5416 and C5510 McBSP are very similarsimilar The small differences will be discussed in a The small differences will be discussed in a

later sectionlater section 3 McBSPs on C5416 and C55103 McBSPs on C5416 and C5510 Basic pins on serial ports (R for Read Basic pins on serial ports (R for Read

and X for Transmit):and X for Transmit): BDR or BDX: serial dataBDR or BDX: serial data BCLKR or BCLKX: clock at bit rateBCLKR or BCLKX: clock at bit rate BFSR or BFSX: frame synchronization BFSR or BFSX: frame synchronization

(word rate)(word rate)


ESIEE, Slide 11

Multi-Channel Buffered Serial Port (McBSP)Multi-Channel Buffered Serial Port (McBSP)

Full duplex, max bit rate = ½ CPU clockFull duplex, max bit rate = ½ CPU clock Word length: 8, 12, 16,20, 24, 32Word length: 8, 12, 16,20, 24, 32 Frame length (between FS): 1-128 wordsFrame length (between FS): 1-128 words

McBSP

DRR

XSR DXR

Event

CPU

DMA

RBR RSR

Clock &

Frame Control

Multi-Channel Control

RINT

XINT

BDR

BDX

BCLKR BCLKX BFSR BFSX

Data Bus

DMA Bus

BCLKS


ESIEE, Slide 12

McBSP Interface Signals McBSP Interface Signals

Pin I/O/Z† DescriptionBCLKR I/O/Z Receive clockBCLKX I/O/Z Transmit clockBCLKS I External clockBDR I Received serial dataBDX O/Z Transmitted serial dataBFSR I/O/Z Receive frame synchronizationBFSX I/O/Z Transmit frame synchronization

† I = Input, O = Output, Z = High-impedance


ESIEE, Slide 13

More Features of the McBSP 1 of 2More Features of the McBSP 1 of 2

Double-buffered transmission and Double-buffered transmission and triple-buffered receptiontriple-buffered reception

Independent clocking and framing for Independent clocking and framing for transmit and receive.transmit and receive.

Capability to send interrupts to the Capability to send interrupts to the CPU and DMA event to the DMA CPU and DMA event to the DMA controller.controller.

External shift clock generation or an External shift clock generation or an internal programmable-frequency clockinternal programmable-frequency clock

Highly programmable internal clock Highly programmable internal clock and frame generationand frame generation Programmable sample rate generatorProgrammable sample rate generator

128 channels.128 channels.


ESIEE, Slide 14

More Features of the McBSP 2 of 2More Features of the McBSP 2 of 2

Programmable polarity for both frame Programmable polarity for both frame synchronization and data clockssynchronization and data clocks

8-bit data transfers with option of LSB 8-bit data transfers with option of LSB or MSB firstor MSB first

-Law and A-Law companding-Law and A-Law companding

(1) (2) (DLB) From CPU/DMA DXR1

To CPU/DMA DRR1 RJUST

DX XSR1 Compress

Expand DR RBR1 RSR1 8

8

16

16

16


ESIEE, Slide 15

Bit OrderingBit Ordering Normally, transfers using the McBSP Normally, transfers using the McBSP

are sent and received with the MSB are sent and received with the MSB first.first.

Certain 8-bit data protocols (that do not Certain 8-bit data protocols (that do not use companded data) require the LSB to use companded data) require the LSB to be transferred first:be transferred first: By setting (R/X)COMPAND = 01b in By setting (R/X)COMPAND = 01b in

(R/X)CR2, the bit ordering of 8-bit words (R/X)CR2, the bit ordering of 8-bit words is reversed (LSB first) . is reversed (LSB first) .

This feature is only enabled if the This feature is only enabled if the appropriate (R/X)WDLEN[1,2] is set to 0, appropriate (R/X)WDLEN[1,2] is set to 0, (8-bit words).(8-bit words).

If either phase of the frame does not have If either phase of the frame does not have an 8-bit word length, the McBSP assumes an 8-bit word length, the McBSP assumes the word length is 8 bits, and LSB-first the word length is 8 bits, and LSB-first ordering is done.ordering is done.


ESIEE, Slide 16

McBSP Data and Control PathsMcBSP Data and Control Paths

The letter B The letter B before the before the pin names is pin names is omitted on omitted on this figure, this figure, ie DX ie DX instead of instead of BDX.BDX.

It will also It will also be the case be the case in the in the following following slides.slides.


ESIEE, Slide 17

McBSP Control Registers for Clock and Frame McBSP Control Registers for Clock and Frame Synchronisation and ControlSynchronisation and Control

SPCR1x McBSP serial port control register 1SPCR2x McBSP serial port control register 2RCR1x McBSP receive control register 1RCR2x McBSP receive control register 2XCR1x McBSP transmit control register 1XCR2x McBSP transmit control register 2SRGR1x McBSP sample rate generator register 1SRGR2x McBSP sample rate generator register 2PCRx McBSP pin control register

The x at the end of a register name represents the number of the The x at the end of a register name represents the number of the McBSP device: McBSP 0,1 or 2.McBSP device: McBSP 0,1 or 2.


ESIEE, Slide 18

McBSP Control Registers for Channel SelectionMcBSP Control Registers for Channel Selection

8 partitions A, B, C, D, E, F, G, H8 partitions A, B, C, D, E, F, G, H

The x at the end of a register name represents the number of the The x at the end of a register name represents the number of the McBSP device: McBSP 0,1 or 2.McBSP device: McBSP 0,1 or 2.

MCR1xMCR1xRCERAxRCERBxRCERCx to RCERHxXCERAxXCERBxXCERCx to XCERHx

McBSP multichannel register 1McBSP multichannel register 2

McBSP transmit channel enable partition AMcBSP transmit channel enable partition B

McBSP receive channel enable register partition AMcBSP receive channel enable register partition B

...

…


ESIEE, Slide 19

McBSP ConfigurationMcBSP Configuration

Via SPCR1, SPCR2 and PCR registersVia SPCR1, SPCR2 and PCR registers These contain status information and bits These contain status information and bits

that can be configured for the required that can be configured for the required operation.operation.

PCR PCR Configures the McBSP pins as inputs or outputs Configures the McBSP pins as inputs or outputs

during normal serial port operation,during normal serial port operation, Configures the pins as general purpose inputs or Configures the pins as general purpose inputs or

outputs during receiver and/or transmitter reset.outputs during receiver and/or transmitter reset.


ESIEE, Slide 20

Configuration of McBSP, SPCR1 RegisterConfiguration of McBSP, SPCR1 Register

DLB= Digital Loop Back ModeDLB= Digital Loop Back Mode RJUST = Receive Sign-Extension and Justification ModeRJUST = Receive Sign-Extension and Justification Mode CLKSTP = Clock Stop ModeCLKSTP = Clock Stop Mode DXENA = DX DXENA = DX delay delay EnablerEnabler ABIS = A-bis modeABIS = A-bis mode RINTM = Receive Interrupt Mode RINTM = Receive Interrupt Mode RSYNCERR = Receive Synchronization ErrorRSYNCERR = Receive Synchronization Error RFULL = Receiver shift Register fullRFULL = Receiver shift Register full RRDY = Receiver ReadyRRDY = Receiver Ready RRST = Receiver ResetRRST = Receiver Reset

15DLB

RW,+0

7 6 3 2 1 0DXENA ABIS RSYNCERR RFULL RRDY RRSTRW,+0 RW,+0 RW,+0 R,+0 R,+0 RW,+0 *

Note: R = Read, W = Write, +0 = Value at reset* R, +0 means read-only, reset value is 0. RW, +0 means read and write allowed, reset value is 0.

RW,+0 R,+0

RW,+0

10 812 1114 13

5 4

reservedCLKSTPRJUST

RINTM

RW,+0


ESIEE, Slide 21

Configuration of McBSP, SPCR2 RegisterConfiguration of McBSP, SPCR2 Register15 14 13 12 11 10 9 8

FREE SOFTRW,+0 RW,+0

7 6 3 2 1 0FRST GRST XSYNCERR‡ XEMPTY XRDY XRST

RW,+0 RW,+0 RW,+0 R,+0 R,+0 RW,+0

Reserved*R,+0

5 4XINTMRW,+0

*Note: This and all reserved bit-fields have NO storage associated with them; however, they are always read as 0.

‡ CAUTION: Writing a 1 to this bit sets the error condition; thus, it is mainly used for testing purposes or if this operation is desired.

FREE = Free Running mode (in emulation)FREE = Free Running mode (in emulation) SOFT = Soft bit (in emulation)SOFT = Soft bit (in emulation) FRST = Frame-sync generator ResetFRST = Frame-sync generator Reset GRST = Sample rate generator ResetGRST = Sample rate generator Reset


ESIEE, Slide 22

Configuration of McBSP Configuration of McBSP PCR Pin Control RegisterPCR Pin Control Register

15 14 13 12 11 10 9 8XIOEN RIOEN FSXM FSRM CLKXM CLKRMRW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0

7 6 3 2 1 0reserved CLKS STAT DX STAT DR STAT FSXP FSRP CLKXP CLKRP

R,+0 R,+0 R,+0 R,+0 RW,+0 RW,+0 RW,+0 RW,+0

5 4

ReservedR,+0

XIOEN = Transmit general purpose IO modeXIOEN = Transmit general purpose IO mode RIOEN = Receive general purpose IO modeRIOEN = Receive general purpose IO mode FSXM = Transmit Frame-Synchronization ModeFSXM = Transmit Frame-Synchronization Mode FSRM = Receive Frame-Synchronization ModeFSRM = Receive Frame-Synchronization Mode CLKXM, CLKRM = Transmitter (Receiver) clock ModeCLKXM, CLKRM = Transmitter (Receiver) clock Mode CLKS_STAT = Status of CLKS pin when GPIOCLKS_STAT = Status of CLKS pin when GPIO DX_STAT, DR_STAT = Status of DX (DR) when GPIODX_STAT, DR_STAT = Status of DX (DR) when GPIO FSXP, FSRP = Transmit (receive) Frame-Sync. PolarityFSXP, FSRP = Transmit (receive) Frame-Sync. Polarity CLKXP, CLKRP = Transmit (receive) Clock PolarityCLKXP, CLKRP = Transmit (receive) Clock Polarity


ESIEE, Slide 23

Receive and Transmit Control Registers RCR and XCRReceive and Transmit Control Registers RCR and XCR

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0rsvdR,+0

RFRLEN1 RWDLEN1 ReservedRW,+0 RW,+0 R,+0

RCR1RCR1

RFLEN1 = Receive Frame Length 1 (1 to 128 words / frame)RFLEN1 = Receive Frame Length 1 (1 to 128 words / frame) RWDLEN1 = Receive Word Length 1 (8, 12, 16, 20, 24, 32 bits)RWDLEN1 = Receive Word Length 1 (8, 12, 16, 20, 24, 32 bits)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0RPHASE RFIGRW,+0 RW,+0

RCOMPAND RDATDLYRW,+0 RW,+0

RFRLEN2 RWDLEN2RW,+0 RW,+0

RCR2RCR2

RPHASE = Receive phases (single or dual frames)RPHASE = Receive phases (single or dual frames) RFLEN2 =Receive Frame Length 2 (1 to 128 words / frame)RFLEN2 =Receive Frame Length 2 (1 to 128 words / frame) RWDLEN2 = Receive Word Length 2 (8, 12, 16, 20, 24, 32 bits)RWDLEN2 = Receive Word Length 2 (8, 12, 16, 20, 24, 32 bits) RCOMPAND = Receive companding modeRCOMPAND = Receive companding mode RFIG = Receive Frame IgnoreRFIG = Receive Frame Ignore RDATDLY =Receive Data DelayRDATDLY =Receive Data Delay

Structure of XCR1 and XCR2 is similar to that of RCR1 and RCR2.Structure of XCR1 and XCR2 is similar to that of RCR1 and RCR2.


ESIEE, Slide 24

McBSP ResetMcBSP Reset

(R/X)RST and RESET(R/X)RST and RESET Device reset (RS = 0) places the receiver, Device reset (RS = 0) places the receiver,

transmitter and the sample rate generator transmitter and the sample rate generator SRGR in reset. SRGR in reset.

When the device reset is removed (RS = 1) When the device reset is removed (RS = 1) GRST = FRST = RRST = XRST = 0, GRST = FRST = RRST = XRST = 0, keeping the entire serial port in the reset keeping the entire serial port in the reset state.state.

The SP transmitter and receiver can be The SP transmitter and receiver can be independently reset by the RRST and independently reset by the RRST and XRST bits in the SPCR registers. The XRST bits in the SPCR registers. The SRGR is reset by the GRST bit in SPCR2.SRGR is reset by the GRST bit in SPCR2.


ESIEE, Slide 25

Determining Ready Status

RRDY and XRDY indicate the ready RRDY and XRDY indicate the ready state of the McBSP receiver and state of the McBSP receiver and transmitter. transmitter.

Serial port writes and reads may be Serial port writes and reads may be synchronized:synchronized: By polling RRDY and XRDY, By polling RRDY and XRDY, or by using the events to DMAor by using the events to DMA

REVT and XEVT in normal mode,REVT and XEVT in normal mode, and REVTA and XEVTA in A-bis mode, and REVTA and XEVTA in A-bis mode,

or by interrupts to CPU (RINT and XINT), or by interrupts to CPU (RINT and XINT), which the events generate. which the events generate.

Note that reading DRR[1,2] and writing to Note that reading DRR[1,2] and writing to DXR[1,2] affect RRDY and XRDY.DXR[1,2] affect RRDY and XRDY.


ESIEE, Slide 26

Frame and Clock ConfigurationFrame and Clock Configuration

The McBSP allows independent The McBSP allows independent configurations of data clock and frame configurations of data clock and frame synchronization for receive and transmit:synchronization for receive and transmit: Polarities of FSR, FSX, CLKX, and CLKRPolarities of FSR, FSX, CLKX, and CLKR A choice of single- or dual-phase framesA choice of single- or dual-phase frames For each phase, the number of words per frameFor each phase, the number of words per frame For each phase, the number of bits per wordFor each phase, the number of bits per word Subsequent frame synchronization may restart the Subsequent frame synchronization may restart the

serial data stream or be ignored.serial data stream or be ignored. The data bit delay from frame synchronization to The data bit delay from frame synchronization to

first data bit can be 0-,first data bit can be 0-, 1-, or 2-bit delays.1-, or 2-bit delays. Right- or left-justification as well as sign-extension Right- or left-justification as well as sign-extension

or zero-filling can be chosen for receive data.or zero-filling can be chosen for receive data.


ESIEE, Slide 27

Frame and Clock OperationFrame and Clock Operation

Receive and transmit frame-sync pulses Receive and transmit frame-sync pulses can be generated:can be generated: Either internally by the sample rate Either internally by the sample rate

generator SRGR,generator SRGR, or driven by an external source.or driven by an external source. The source of frame sync is selected by the The source of frame sync is selected by the

mode bit, FS(R/X)M, in the PCR.mode bit, FS(R/X)M, in the PCR. FSR is affected by GSYNC bit in SRGR2FSR is affected by GSYNC bit in SRGR2 Receive and transmit clocks can be selected Receive and transmit clocks can be selected

to be inputs or outputs by the mode bit, to be inputs or outputs by the mode bit, CLK(R/X)M, in the PCR.CLK(R/X)M, in the PCR.


ESIEE, Slide 28

Sample Rate GeneratorSample Rate Generator


ESIEE, Slide 29

Sample Rate Generator Register SRGRSample Rate Generator Register SRGR

15 8 7 0FWID CLKGDV

RW,+0 RW

SRGR 1SRGR 1

FWID = Frame WidthFWID = Frame Width CLKGDV = Sample rate generator Clock DividerCLKGDV = Sample rate generator Clock Divider

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0GSYNC CLKSP CLKSM FSGMRW,+0 RW,+0 RW RW,+0

FPERRW,+0

SRGR 2SRGR 2

GSYNC = SRGR Clock synchronizationGSYNC = SRGR Clock synchronization CLKSP = Polarity Clock edge selectionCLKSP = Polarity Clock edge selection CLKSM = SRGR Clock ModeCLKSM = SRGR Clock Mode FSGM = SRGR transmit Frame-Sync ModeFSGM = SRGR transmit Frame-Sync Mode FPER = Frame PeriodFPER = Frame Period


ESIEE, Slide 30

Data Clock GenerationData Clock Generation

When (CLK[R/X]M = 1), the data When (CLK[R/X]M = 1), the data clocks (CLK[R/X]) are driven by:clocks (CLK[R/X]) are driven by: the internal SRGR output clock, CLKG. the internal SRGR output clock, CLKG. The input clock to the SRGR can be either The input clock to the SRGR can be either

the CPU clock or a dedicated external the CPU clock or a dedicated external clock input (CLKS).clock input (CLKS). The CLKSM bit in SRGR2 selects either the The CLKSM bit in SRGR2 selects either the

CPU clock (CLKSM = 1) or the external clock CPU clock (CLKSM = 1) or the external clock input (CLKSM = 0) CLKS.input (CLKSM = 0) CLKS.

The input clock source to the SRGR can be The input clock source to the SRGR can be divided down by a programmable value divided down by a programmable value (CLKGDV) to drive CLKG(CLKGDV) to drive CLKG

Regardless of the source to the SRGR, the Regardless of the source to the SRGR, the rising edge of CLKSRG generates CLKG rising edge of CLKSRG generates CLKG and FSGand FSG


ESIEE, Slide 31

Digital Loop Back Mode DLBDigital Loop Back Mode DLB

DLB = 1 in SPCR1 enables digital loop DLB = 1 in SPCR1 enables digital loop back mode.back mode.

During DLB mode, DR, FSR, and During DLB mode, DR, FSR, and CLKR are internally connected through CLKR are internally connected through multiplexers to DX, FSX, CLKX, multiplexers to DX, FSX, CLKX, respectively.respectively.

DLB mode allows testing of serial port DLB mode allows testing of serial port code with a single DSP device.code with a single DSP device.

In digital loop back mode, the In digital loop back mode, the transmitter clock drives the receiver. transmitter clock drives the receiver. CLKRM determines whether the CLKR CLKRM determines whether the CLKR pin is an input or an output.pin is an input or an output.


ESIEE, Slide 32

Frame-sync Signal GenerationFrame-sync Signal Generation

When FRST=1 in SPCR2, it activates When FRST=1 in SPCR2, it activates the frame-sync generation logic to the frame-sync generation logic to generate a frame-sync signal, if FSGM = generate a frame-sync signal, if FSGM = 1 in SRGR2. 1 in SRGR2.

Frame-sync programming options:Frame-sync programming options: A frame pulse with a programmable period A frame pulse with a programmable period

and programmable active width, using the and programmable active width, using the SRGR1 register,SRGR1 register,

The transmit portion may trigger its own The transmit portion may trigger its own frame-sync signal generated by a frame-sync signal generated by a DXR[1,2]-to-XSR[1,2] copy,DXR[1,2]-to-XSR[1,2] copy,

Both the receive and transmit sections may Both the receive and transmit sections may independently select an external frame independently select an external frame synchronization on the FSR and FSX pins, synchronization on the FSR and FSX pins, respectively.respectively.


ESIEE, Slide 33

PCR 1100 CLKRM FSRMM

00 11

55

0-external 1-internal

88

0-external 1-internal

SPCR11 55 44 11

RRDY RINTM 00 11

55

CCPPUU iinntteerrrruupptt?? DDRRRR rreeaaddyy?? (not used) (not used)

RCR1 88

RWDLEN1 00 11

55

8/12/16/20/24/32

55

1-128

RFRLEN1 77 11

44

(16) (16)

McBSP - ExampleMcBSP - Example Problem: transfer 16 16-bit words to SARAM, ext’l CLK/FS, no CPU intProblem: transfer 16 16-bit words to SARAM, ext’l CLK/FS, no CPU int

DD CCLLKK FFSS

A/D w0 w1 w15 ...... BDR

CLKR FSR

McBSP

DRR REVT

DMA 0 1

... 15

SARAM

- Bit/CLKR shifted into RSR- Bit/CLKR shifted into RSR

- RSR - RSR RBR RBR

- RBR - RBR DRR (RRDY=1) DRR (RRDY=1)

- REVT sync event activates- REVT sync event activates DMA (no McBSP setup) DMA (no McBSP setup)

- DMA transfers DRR- DMA transfers DRR to SARAM to SARAM

……repeatrepeat

OperationOperation


ESIEE, Slide 34

Multichannel Selection OperationMultichannel Selection Operation

A McBSP channel is a time slot for A McBSP channel is a time slot for shifting in/out the bits of one serial word.shifting in/out the bits of one serial word. Each McBSP supports up to 128 channels.Each McBSP supports up to 128 channels.

The 128 channels are divided into 8 The 128 channels are divided into 8 blocksblocks of 16 consecutive channels:of 16 consecutive channels: Block 0: Channels 0-15Block 0: Channels 0-15 Block 1: Channels 16-31 …Block 1: Channels 16-31 … Block 7: Channels 112-127Block 7: Channels 112-127

The blocks are assigned to The blocks are assigned to partitionspartitions:: In ‘C5410 or ‘C5420, only 2 partitions A or BIn ‘C5410 or ‘C5420, only 2 partitions A or B In the In the C5416C5416 and and C5510C5510, choice between 2 , choice between 2

partitions (A,B) or 8 partitions (A, B, C, …H.)partitions (A,B) or 8 partitions (A, B, C, …H.)


ESIEE, Slide 35

Multichannel Partition ModeMultichannel Partition Mode

In the In the 2 partitions mode2 partitions mode:: One even-numbered block (0,2,4,6) is One even-numbered block (0,2,4,6) is

assigned to partition A and one odd-assigned to partition A and one odd-numbered block (1,3,5,7) to partition B.numbered block (1,3,5,7) to partition B.

Up to 32 channels can be selected.Up to 32 channels can be selected. In the In the 8 partitions mode8 partitions mode, blocks 0 , blocks 0

through 7 are automatically assigned to through 7 are automatically assigned to partitions A through H.partitions A through H. Up to 128 channels can be selected.Up to 128 channels can be selected.

The number of partitions for reception The number of partitions for reception and transmission are independent.and transmission are independent.


ESIEE, Slide 36

Multichannel SelectionMultichannel Selection

When a McBSP uses a TDM (Time When a McBSP uses a TDM (Time Division Multiplex) data stream, it may Division Multiplex) data stream, it may need to select only a few channels to need to select only a few channels to save memory and bandwidth.save memory and bandwidth.

Each channel Each channel partition partition has a dedicated has a dedicated channel enable register.channel enable register. If the multichannel selection mode is on, If the multichannel selection mode is on,

each bit in the register controls whether a each bit in the register controls whether a channel is selected or not in the partition.channel is selected or not in the partition.

There is 1 receive multichannel selection There is 1 receive multichannel selection mode and 3 transmit modes.mode and 3 transmit modes.


ESIEE, Slide 37

Configuring a Frame for Multichannel Configuring a Frame for Multichannel SelectionSelection

Select a single-phase frame:Select a single-phase frame: RPHASE/WPHASE = 0RPHASE/WPHASE = 0 Each frame represents a TDM data stream.Each frame represents a TDM data stream.

Set a frame length (R/X)FRLEN1 Set a frame length (R/X)FRLEN1 including the highest-numbered channel including the highest-numbered channel in the selection.in the selection.


ESIEE, Slide 38

Control of Multichannel SelectionControl of Multichannel Selection

The multichannel mode can be enabled The multichannel mode can be enabled independently for receive and transmit independently for receive and transmit by setting RMCM = 1 and XMCM to a by setting RMCM = 1 and XMCM to a non-zero value in control registers non-zero value in control registers MCR[1,2], respectively.MCR[1,2], respectively.

Choose the partition mode: 2 or 8 Choose the partition mode: 2 or 8 partitions, with the RMCME and/or partitions, with the RMCME and/or XMCME bits:XMCME bits: (R/X)MCME = 0, 2 partitions A-B(R/X)MCME = 0, 2 partitions A-B (R/X)MCME = 1, 8 partitions A-B…H(R/X)MCME = 1, 8 partitions A-B…H


ESIEE, Slide 39

Multichannel Operation Control RegistersMultichannel Operation Control Registers

MCR1, MCR2: Multichannel control MCR1, MCR2: Multichannel control registersregisters

XCERx: transmit channel enable registersXCERx: transmit channel enable registers x = a letter A, B, C, D, E, F or Hx = a letter A, B, C, D, E, F or H

RCERx: receive channel enable registersRCERx: receive channel enable registers x = a letter A, B, C, D, E, F or Hx = a letter A, B, C, D, E, F or H


ESIEE, Slide 40

Multichannel Operation MCR1 RegisterMultichannel Operation MCR1 Register

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0rsvd RMCMR,+0 RW,+0

Reserved RPBBLK RPABLK RCBLKR,+0 RW,+0 RW,+0 R,+0

MCR1MCR1 for C5410 or C5420 for C5410 or C5420

RPBBLK = Receive Partition B BlockRPBBLK = Receive Partition B Block RPABLK = Receive Partition A BlockRPABLK = Receive Partition A Block RCBLK = Receive Current BlockRCBLK = Receive Current Block RMCM = Receive Multichannel Selection EnableRMCM = Receive Multichannel Selection Enable

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0RMCME rsvd RMCM

R,+0 RW,+0RPBBLK RPABLK RCBLKReserved

R,+0 RW,+0 RW,+0 R,+0

MCR1MCR1 for for C5416 C5416 and and C5510C5510

RMCME = Receive Multichannel Partition Mode bit, applicable if RMCME = Receive Multichannel Partition Mode bit, applicable if channel can be individually selected RMCM = 1channel can be individually selected RMCM = 1


ESIEE, Slide 41

Multichannel Operation MCR2 RegisterMultichannel Operation MCR2 Register

MCR 2 for C5410 or C54 20MCR 2 for C5410 or C54 20

MCR 2 for MCR 2 for C5416 C5416 and and C5510C5510

MCR2 has the same structure as MCR1 but for transmission.MCR2 has the same structure as MCR1 but for transmission.

The XMCM bits of XCR2 determine whether all channels or only The XMCM bits of XCR2 determine whether all channels or only selected channels are enabled and unmasked for transmission. selected channels are enabled and unmasked for transmission.

There are 3 transmit multichannel selection modes There are 3 transmit multichannel selection modes 00b: No selection. All channels are enabled and unmasked. 00b: No selection. All channels are enabled and unmasked. 01b: All channels are disabled unless selected in XCERs registers. If 01b: All channels are disabled unless selected in XCERs registers. If

enabled, a channel is also unmasked.enabled, a channel is also unmasked. 10b: All channels are enabled, but they are masked unless they are 10b: All channels are enabled, but they are masked unless they are

selected in XCERs registers.selected in XCERs registers. 11 b: symmetric transmission/reception. All channels are disabled for 11 b: symmetric transmission/reception. All channels are disabled for

transmission unless they are enabled for reception in RCER registers. transmission unless they are enabled for reception in RCER registers. Once enabled, they are masked unless they are also selected in the Once enabled, they are masked unless they are also selected in the XCERs registers.XCERs registers.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R,+0 RW,+0 RW,+0 R,+0Reserved XPBBLK XPABLK XCBLK XMCM

RW,+0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0XMCME

R,+0 RW,+0 RW,+0 R,+0Reserved XPBBLK XPABLK XCBLK XMCM

RW,+0


ESIEE, Slide 42

Using Using 2 partitions2 partitions A and B A and B McBSP channels are activated using an McBSP channels are activated using an

alternating scheme. After a sync pulse:alternating scheme. After a sync pulse: ReRecceiver or transmitter begins with the eiver or transmitter begins with the

channels in partition A and alternates channels in partition A and alternates between part. B and A until the end of the between part. B and A until the end of the frame.frame.

Assigning blocks to partitions. Any 2 of Assigning blocks to partitions. Any 2 of the 8 blocks can be assigned to A and B:the 8 blocks can be assigned to A and B: Assign an even-numbered block to A by Assign an even-numbered block to A by

writing the 2 (R/X)PABLK bits and an writing the 2 (R/X)PABLK bits and an odd-numbered block to B (R/X)PBBLK.odd-numbered block to B (R/X)PBBLK.

The channels are controlled the receive or The channels are controlled the receive or transmit channel enable registers transmit channel enable registers (R/X)CERCA, (R/X)CERA.(R/X)CERCA, (R/X)CERA.


ESIEE, Slide 43

Using Using 2 partitions2 partitions A and B A and B

Blocks can be reassigned during Blocks can be reassigned during communication if we want to use more communication if we want to use more than 32 selected channels.than 32 selected channels. It is not possible to modify the block It is not possible to modify the block

assignment of a partition during its assignment of a partition during its transfer.transfer.

The block currently involved in the The block currently involved in the transmission is reflected in the (R/X)CBLK transmission is reflected in the (R/X)CBLK bits. They can be polled.bits. They can be polled.

At the end of a block, an interrupt can be At the end of a block, an interrupt can be sent to the CPU that checks (R/X)CBLK sent to the CPU that checks (R/X)CBLK bits and updates the inactive partition.bits and updates the inactive partition.


ESIEE, Slide 44

Using Using 8 Partitions8 Partitions

RMCME/XMCME = 1RMCME/XMCME = 1 Partitions are activated in the order:Partitions are activated in the order:

A B C D E F G H.A B C D E F G H. The (R/X)PABLK and (R/X)PBBLK are The (R/X)PABLK and (R/X)PBBLK are

ignored. ignored. The blocks are assigned to the partitions in The blocks are assigned to the partitions in

natural order:natural order: A: block 0, channels 0 to 15, reg. (R/X)CERAA: block 0, channels 0 to 15, reg. (R/X)CERA B: block 1, channels 16 to 31, reg. (R/X)CERBB: block 1, channels 16 to 31, reg. (R/X)CERB …… H: block 7, chan. 112 to 127, reg. (R/X)CERHH: block 7, chan. 112 to 127, reg. (R/X)CERH


ESIEE, Slide 45

Receive Channels DisabledReceive Channels Disabled

If a receive channel is disabled, any bits If a receive channel is disabled, any bits received in that channel are passed only received in that channel are passed only as far as the receive buffer register(s) as far as the receive buffer register(s) (RBR(s)). (RBR(s)). The receiver does not copy the content of The receiver does not copy the content of

the RBR(s) to the DRR(s), and as a result, the RBR(s) to the DRR(s), and as a result, does not set the receiver ready bit (RRDY).does not set the receiver ready bit (RRDY).

Therefore, no DMA synchronization event Therefore, no DMA synchronization event (REVT) is generated, and if the receiver (REVT) is generated, and if the receiver interrupt mode depends on RRDY interrupt mode depends on RRDY (RINTM = 00b), no interrupt is generated.(RINTM = 00b), no interrupt is generated.


ESIEE, Slide 46

Enabling/Disabling versus Masking/UnmaskingEnabling/Disabling versus Masking/Unmasking

For transmission, a channel may be:For transmission, a channel may be: Enabled and unmaskedEnabled and unmasked

Transmission can begin and be completedTransmission can begin and be completed Enabled: Data are passed from DXR to XSR.Enabled: Data are passed from DXR to XSR. Unmasked: Data in XSR shifted out on DX pin.Unmasked: Data in XSR shifted out on DX pin.

Enabled and maskedEnabled and masked Transmission can begin but cannot be completedTransmission can begin but cannot be completed Masked: DX pin is held in high impedance. Avoids Masked: DX pin is held in high impedance. Avoids

bus contention on a shared serial bus.bus contention on a shared serial bus.

DisabledDisabled Transmission cannot occur. No DXR to XSR copy.Transmission cannot occur. No DXR to XSR copy.

The bit XRDY is not set.The bit XRDY is not set.


ESIEE, Slide 47

Channel Enable Registers RCERx and XCERxChannel Enable Registers RCERx and XCERx

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0RCEA15 RCEA14 RCEA13 RCEA12RCEA11 RCEA10 RCEA9 RCEA8 RCEA7 RCEA6 RCEA5RCEA4 RCEA3 RCEA2RCEA1 RCEA0RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0XCEA15 XCEA14 XCEA13 XCEA12 XCEA11 XCEA10 XCEA9 XCEA8 XCEA7 XCEA6 XCEA5 XCEA4 XCEA3 XCEA2 XCEA1 XCEA0RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0

RRCCEERRAA

XXCCEERRAA

In C5410 and C5420, there are 2 receive and 2 transmit In C5410 and C5420, there are 2 receive and 2 transmit Channel Enable Registers: RCERA, RCERB, XCERA, Channel Enable Registers: RCERA, RCERB, XCERA, XCERB.XCERB.

In In C5416C5416 and and C5510C5510, there are 8 receive + 8 transmit , there are 8 receive + 8 transmit Channel Enable Registers: RCERA to RCERH and Channel Enable Registers: RCERA to RCERH and XCERA to XCERH.XCERA to XCERH.


ESIEE, Slide 48

SPI ModeSPI Mode The SPI protocol is a master-slave configuration, with one master The SPI protocol is a master-slave configuration, with one master

device and one or more slave devices. The interface consists of four device and one or more slave devices. The interface consists of four signals.signals. The clock stop mode of the McBSP provides compatibility with the SPI The clock stop mode of the McBSP provides compatibility with the SPI

protocol.protocol.


ESIEE, Slide 49

McBSP Pins as General Purpose I/O pins 1 of 2McBSP Pins as General Purpose I/O pins 1 of 2 Two conditions allow the serial port pins Two conditions allow the serial port pins

(CLKX, FSX, DX, CLKR, FSR and DR) to be (CLKX, FSX, DX, CLKR, FSR and DR) to be used as general purpose input/output (I/O) used as general purpose input/output (I/O) rather than serial port pins:rather than serial port pins: 1) The related portion (transmitter or receiver) of 1) The related portion (transmitter or receiver) of

the serial port is in reset; (R/X)RST = 0 in the serial port is in reset; (R/X)RST = 0 in SPCR[1,2].SPCR[1,2].

2) General purpose I/O is enabled for the related 2) General purpose I/O is enabled for the related portion of the serial port; (R/X)IOEN = 1 in the portion of the serial port; (R/X)IOEN = 1 in the PCR.PCR.

In the case of FS(R/X), FS(R/X)M=0(or 1) In the case of FS(R/X), FS(R/X)M=0(or 1) configures the pin as an input (or output).configures the pin as an input (or output). When configured as an output, the value driven on When configured as an output, the value driven on

FS(R/X) is the value stored in FS(R/X)P. FS(R/X) is the value stored in FS(R/X)P. If configured as an input, FS(R/X)P becomes a If configured as an input, FS(R/X)P becomes a

read-only bit that reflects the status of that signal.read-only bit that reflects the status of that signal.


ESIEE, Slide 50

McBSP Pins as General Purpose I/O pins 2 of 2McBSP Pins as General Purpose I/O pins 2 of 2

CLK(R/X)M and CLK(R/X)P work CLK(R/X)M and CLK(R/X)P work similarly for CLK(R/X). similarly for CLK(R/X).

DX and DR as GPIO pins:DX and DR as GPIO pins: the value of the DX_STAT bit in the PCR the value of the DX_STAT bit in the PCR

is driven onto DX. is driven onto DX. DR is always an input and its value is held DR is always an input and its value is held

in the DR_STAT bit in the PCR. in the DR_STAT bit in the PCR. CLKS as a general purpose input:CLKS as a general purpose input:

both the transmitter and receiver must be both the transmitter and receiver must be in reset state and (R/X)IOEN = 1, because in reset state and (R/X)IOEN = 1, because CLKS is always an input to the McBSP CLKS is always an input to the McBSP and affects both transmit and receive and affects both transmit and receive operations.operations.


ESIEE, Slide 51

McBSP Operation in Power-down ModeMcBSP Operation in Power-down Mode For the For the C5416C5416, Power-down modes may be , Power-down modes may be

invoked in several ways:invoked in several ways: executing the IDLE instruction or driving the executing the IDLE instruction or driving the

HOLD input low with the HM status bit set to one. HOLD input low with the HM status bit set to one. The McBSP can take the CPU out of IDLE using a The McBSP can take the CPU out of IDLE using a

transmit or receive interrupt.transmit or receive interrupt. When in IDLE1 or HOLD modes, the McBSP When in IDLE1 or HOLD modes, the McBSP

continues to operate normally with no restrictions.continues to operate normally with no restrictions. In IDLE2 or IDLE3 modes, the internal device In IDLE2 or IDLE3 modes, the internal device

clocks provided to the peripherals are stopped. clocks provided to the peripherals are stopped. If external clock and frame-sync are provided, the If external clock and frame-sync are provided, the

McBSP can continue to operate, and receive and McBSP can continue to operate, and receive and transmit interrupts can be used to exit the IDLE state.transmit interrupts can be used to exit the IDLE state.

If either clocks or frame-syncs are internal, the McBSP If either clocks or frame-syncs are internal, the McBSP will stop in IDLE2/3.will stop in IDLE2/3.

In IDLE2/3, the internal clocks to the McBSP and the In IDLE2/3, the internal clocks to the McBSP and the DMA controller are started automatically when a DMA controller are started automatically when a transfer begins, and stopped after the transferis transfer begins, and stopped after the transferis completed. completed.


ESIEE, Slide 52

McBSP Operation in Power-down ModeMcBSP Operation in Power-down Mode For theFor the C5510 C5510,, The McBSP is placed into its The McBSP is placed into its

idle mode when:idle mode when: the PERIPH idle domain is idle (PERIS = 1 in the PERIPH idle domain is idle (PERIS = 1 in

ISTR) ISTR) the McBSP idle enable bit is set (SPn = 1) in the the McBSP idle enable bit is set (SPn = 1) in the

PICR register. When the McBSP is in the Idle PICR register. When the McBSP is in the Idle state, it is unable to receive or transmit data.state, it is unable to receive or transmit data.

In the McBSP idle mode:In the McBSP idle mode: If the McBSP is operates with internal clocking If the McBSP is operates with internal clocking

and frame sync., it will be completely stopped.and frame sync., it will be completely stopped. If the McBSP is operates with ext. clocking and If the McBSP is operates with ext. clocking and

frame sync., the external interface portion of the frame sync., the external interface portion of the McBSP continues to function during external McBSP continues to function during external clock activity periods. The McBSP sends a request clock activity periods. The McBSP sends a request to activate the PERIPH and DMA idle domains to activate the PERIPH and DMA idle domains when it needs to be serviced. If the domains were when it needs to be serviced. If the domains were idle, they are made idle again after the McBSP has idle, they are made idle again after the McBSP has been serviced.been serviced.


ESIEE, Slide 53

Emulation FREE and SOFT BitsEmulation FREE and SOFT Bits

FREE and SOFT are special emulation bits FREE and SOFT are special emulation bits that determine the state of the serial port that determine the state of the serial port clock when a breakpoint is encountered in the clock when a breakpoint is encountered in the high-level language debugger.high-level language debugger. If the FREE bit is set to 1If the FREE bit is set to 1

upon a software breakpoint, the clock continues to run upon a software breakpoint, the clock continues to run (free runs) and data still shifts out. When FREE = 1, the (free runs) and data still shifts out. When FREE = 1, the SOFT bit is a don’t care. SOFT bit is a don’t care.

If the FREE bit is cleared to zero, then the SOFT If the FREE bit is cleared to zero, then the SOFT bit takes effect.bit takes effect.

If the SOFT bit is cleared to zero, then the clock If the SOFT bit is cleared to zero, then the clock stops immediately, thus aborting a transmission. stops immediately, thus aborting a transmission.

If the SOFT bit is set to one and a transmission is If the SOFT bit is set to one and a transmission is in progress, the transmission continues until in progress, the transmission continues until completion of the transfer, and then the clock completion of the transfer, and then the clock halts. halts.

The receiver-side functions in a similar fashion. The receiver-side functions in a similar fashion.


ESIEE, Slide 54

Differences Between C5416 and C5510 McBSPDifferences Between C5416 and C5510 McBSP

Addressing of McBSP registers:Addressing of McBSP registers: C5416C5416: sub-bank system: sub-bank system

Some registers are mapped in data memory page 0: Some registers are mapped in data memory page 0: DRR, DXR + SPSA and SPSDDRR, DXR + SPSA and SPSD SPSAx: McBSP Sub-Address register associated with a SPSAx: McBSP Sub-Address register associated with a

SPSD Sub-bank Data register containing the value for one SPSD Sub-bank Data register containing the value for one of the sub-bank registersof the sub-bank registers

The other registers are sub-bank registers accessed The other registers are sub-bank registers accessed by sub-addresses relative to SPSA.by sub-addresses relative to SPSA.

C5510C5510: Registers are mapped in the I/O space: Registers are mapped in the I/O space Power-down modesPower-down modes

C5416 McBSP

Registers addr.


ESIEE, Slide 55

Configuration of the McBSP 1 of 3Configuration of the McBSP 1 of 3

Receiver/transmitter configurationReceiver/transmitter configurationPlace the McBSP receiver / Place the McBSP receiver /

transmitter in resettransmitter in resetProgram the McBSP registers for the Program the McBSP registers for the

desired receiver / transmitter desired receiver / transmitter operationoperation

Take the receiver / transmitter out of Take the receiver / transmitter out of resetreset


ESIEE, Slide 56

Configuration of the McBSP 2 of 3Configuration of the McBSP 2 of 3 Global behaviorGlobal behavior

Set the receiver pins to operate as McBSP pinsSet the receiver pins to operate as McBSP pins Enable/disable the digital loopback modeEnable/disable the digital loopback mode Enable/disable the clock stop modeEnable/disable the clock stop mode Enable/disable the receive multichannel selection Enable/disable the receive multichannel selection

modemode Data behaviorData behavior

Choose 1 or 2 phases for the receive frameChoose 1 or 2 phases for the receive frame Set the receive word length(s)Set the receive word length(s) Set the receive frame lengthSet the receive frame length Enable/disable the receive frame-sync ignore functionEnable/disable the receive frame-sync ignore function Set the receive companding modeSet the receive companding mode Set the receive data delaySet the receive data delay Set the receive sign-extension and justification modeSet the receive sign-extension and justification mode Set the receive interrupt modeSet the receive interrupt mode


ESIEE, Slide 57

Configuration of the McBSP 3 of 3Configuration of the McBSP 3 of 3 Frame-sync behaviorFrame-sync behavior

Set the receive frame-sync modeSet the receive frame-sync mode Set the receive frame-sync polaritySet the receive frame-sync polarity Set the SRG frame-sync period and pulse Set the SRG frame-sync period and pulse

widthwidth Clock behaviorClock behavior

Set the receive clock modeSet the receive clock mode Set the receive clock polaritySet the receive clock polarity Set the SRG clock divide-down valueSet the SRG clock divide-down value Set the SRG clock synchronization modeSet the SRG clock synchronization mode Set the SRG clock mode [choose an input Set the SRG clock mode [choose an input

clock]clock] Set the SRG input clock polaritySet the SRG input clock polarity


ESIEE, Slide 58

Configuration of the McBSP with CSLConfiguration of the McBSP with CSL Example of the DSK-CCS tutorial Example of the DSK-CCS tutorial

audioIO.caudioIO.c of Chapter 4 for the ‘C5416. of Chapter 4 for the ‘C5416. First we examine the file audioIOcfg_c.c First we examine the file audioIOcfg_c.c

that configures the DSP,that configures the DSP, Then we explain how to automatically Then we explain how to automatically

generate it with the GUI interface of CCS.generate it with the GUI interface of CCS. Parameters: Parameters:

The McBSP 2 is usedThe McBSP 2 is used Single phase modeSingle phase mode 32 bits words.32 bits words.

List of files of the example to examineList of files of the example to examine audioIOcfg.haudioIOcfg.h audioIOcfg_c.caudioIOcfg_c.c


ESIEE, Slide 59

File audioIOcfg.hFile audioIOcfg.h /* Do *not* directly modify this file. It was */

/* generated by the Configuration Tool; any */ /* changes risk being overwritten. */ /* INPUT audioIO.cdb */ #define CHIP_5416 1 /* Include Header Files */ #include <std.h> #include <hst.h> #include <swi.h> #include <tsk.h> #include <log.h> #include <sts.h> #include <csl_mcbsp.h> #ifdef __cplusplus extern "C" { #endif extern HST_Obj RTA_fromHost; extern HST_Obj RTA_toHost; extern SWI_Obj KNL_swi; extern TSK_Obj TSK_idle; extern LOG_Obj LOG_system; extern STS_Obj IDL_busyObj; extern MCBSP_Config mcbspCfg0; extern MCBSP_Handle C54XX_DMA_MCBSP_hMcbsp; extern void CSL_cfgInit(); #ifdef __cplusplus } #endif /* extern "C" */

Includes the Chip Support Includes the Chip Support Library for the McBSPLibrary for the McBSP

Defines variablesDefines variables


ESIEE, Slide 60

Example of McBSP configuration file Example of McBSP configuration file 1st part of the file audioIOcfg_c.c1st part of the file audioIOcfg_c.c

/* Do *not* directly modify this file. It was */ /* generated by the Configuration Tool; any */ /* changes risk being overwritten. */ /* INPUT audioIO.cdb */ /* Include Header File */ #include "audioIOcfg.h" /* Config Structures */ MCBSP_Config mcbspCfg0 = { 0x0000, /* Serial Port Control Register 1 */ 0x0200, /* Serial Port Control Register 2 */ 0x00a0, /* Receive Control Register 1 */ 0x0000, /* Receive Control Register 2 */ 0x00a0, /* Transmit Control Register 1 */ 0x0000, /* Transmit Control Register 2 */ 0x1f00, /* Sample Rate Generator Register 1 */ 0x003f, /* Sample Rate Generator Register 2 */ 0x0000, /* Multichannel Control Register 1 */ 0x0000, /* Multichannel Control Register 2 */ 0x0083, /* Pin Control Register */ 0x0000, /* Receive Channel Enable Register Partition A */ 0x0000, /* Receive Channel Enable Register Partition B */ 0x0000, /* Receive Channel Enable Register Partition C */ 0x0000, /* Receive Channel Enable Register Partition D */ 0x0000, /* Receive Channel Enable Register Partition E */ 0x0000, /* Receive Channel Enable Register Partition F */ 0x0000, /* Receive Channel Enable Register Partition G */ 0x0000, /* Receive Channel Enable Register Partition H */

SPCR1=0, SPCR2=0x200

All receive channel enable registers RCERx are set to 0

RCR1=0x00a0, RCR2=0XCR1=0x00a0, XCR2=0

SRGR1=0x1f00, SRGR2=0x003f

MCR1=0x0000, MCR2=0x0000PCR=0x0083


ESIEE, Slide 61

Example of McBSP Configuration FileExample of McBSP Configuration FileLast Part of the FileLast Part of the File

0x0000, /* Transmit Channel Enable Register Partition A */ 0x0000, /* Transmit Channel Enable Register Partition B */ 0x0000, /* Transmit Channel Enable Register Partition C */ 0x0000, /* Transmit Channel Enable Register Partition D */ 0x0000, /* Transmit Channel Enable Register Partition E */ 0x0000, /* Transmit Channel Enable Register Partition F */ 0x0000, /* Transmit Channel Enable Register Partition G */ 0x0000 /* Transmit Channel Enable Register Partition H */ }; /* Handles */ MCBSP_Handle C54XX_DMA_MCBSP_hMcbsp; /* * ======== CSL_cfgInit() ======== */ void CSL_cfgInit() { C54XX_DMA_MCBSP_hMcbsp = MCBSP_open(MCBSP_PORT2, MCBSP_OPEN_RESET); MCBSP_config(C54XX_DMA_MCBSP_hMcbsp, &mcbspCfg0); }

All transmit channel enable registers XCERx are set to 0

Using CSL to open and initialise the McBSP 2.Using CSL to open and initialise the McBSP 2.


ESIEE, Slide 62

File audioIOcfg_c.c 1 of 3File audioIOcfg_c.c 1 of 3

SPCR1 = 0, SPCR2 = 0x0200, Serial Port Control SPCR1 = 0, SPCR2 = 0x0200, Serial Port Control RegistersRegisters RJUST=0, CLKSTP=0, DXENA=0, RINTM=0, RSYNCERR=0, RJUST=0, CLKSTP=0, DXENA=0, RINTM=0, RSYNCERR=0,

RRST=0RRST=0 FREE=1, SOFT=0, FRST=GRST=XINTM=XSYNCERR,XRST=0FREE=1, SOFT=0, FRST=GRST=XINTM=XSYNCERR,XRST=0

RCR1 = 0x00A0, RCR2 = 0, Receive Control RegistersRCR1 = 0x00A0, RCR2 = 0, Receive Control Registers RWDLEN1=101 = 32 bits words, RFLEN1=0 = 1 word per frameRWDLEN1=101 = 32 bits words, RFLEN1=0 = 1 word per frame RDATDLY=0, 0 bit data delayRDATDLY=0, 0 bit data delay RFIG=0, received frame-sync not ignoredRFIG=0, received frame-sync not ignored RCOMPAND=0, no compandingRCOMPAND=0, no companding RWLEN2=0RWLEN2=0 RFRLEN2= 0RFRLEN2= 0 RPHASE = 0 = 1 phase per frame, RWLEN2 and RFRLEN2 ignored.RPHASE = 0 = 1 phase per frame, RWLEN2 and RFRLEN2 ignored.

XCR1 = 0x00A0, XCR2 =0 same remarks as for RCR, XCR1 = 0x00A0, XCR2 =0 same remarks as for RCR, Transmit Control RegisterTransmit Control Register..


ESIEE, Slide 63

File audioIOcfg_c.c 2 of 3File audioIOcfg_c.c 2 of 3

SRGR1 = 0x1F00, SRGR2 = 0x003F, Sample Rate SRGR1 = 0x1F00, SRGR2 = 0x003F, Sample Rate Generator RegistersGenerator Registers CLKGDV =0, divide down value for CLKGCLKGDV =0, divide down value for CLKG FWID = 0x1F=31, frame-sync pulse width for FSG = 32 CLKG FWID = 0x1F=31, frame-sync pulse width for FSG = 32 CLKG

cyclescycles FPER=0x3F=63, Frame-sync period bits for FSG, the period FPER=0x3F=63, Frame-sync period bits for FSG, the period

between frame-sync pulses on FSG is 64 CLKG cycles.between frame-sync pulses on FSG is 64 CLKG cycles. FSGM=0, if FSXM=1 in PCR, the McBSP generates a frame-sync FSGM=0, if FSXM=1 in PCR, the McBSP generates a frame-sync

pulse when DXR is copied in XSR. But here FSXM=0 (see PCR).pulse when DXR is copied in XSR. But here FSXM=0 (see PCR). CLKSM=0, the input clock for SRGR is taken on CLKS pin or CLKSM=0, the input clock for SRGR is taken on CLKS pin or

CLKR pin depending on SCLKME bit in PCR. Here CLKR pin depending on SCLKME bit in PCR. Here SCLKME=1=signal on CLKR.SCLKME=1=signal on CLKR.

CLKSP=0, CLKS pin polarity, the rising edge on CLKS pin drives CLKSP=0, CLKS pin polarity, the rising edge on CLKS pin drives the clock signal CLKG and FSG.the clock signal CLKG and FSG.

GSYNC=0, no clock synchronizationGSYNC=0, no clock synchronization

MCR1 = 0, MCR2 = 0, no multichannel selection, MCR1 = 0, MCR2 = 0, no multichannel selection, Multichannel Control RegistersMultichannel Control Registers


ESIEE, Slide 64

File audioIOcfg_c.c 3 of 3File audioIOcfg_c.c 3 of 3 PCR = 0x0083, Pin control RegisterPCR = 0x0083, Pin control Register

CLKRP=1, CLKXP=1, clock polarityCLKRP=1, CLKXP=1, clock polarity As CLKRM=0, CLKR is an input and the received data is As CLKRM=0, CLKR is an input and the received data is

sampled on the rising edge of CLKR.sampled on the rising edge of CLKR. transmit data is driven on falling edge of CLKX.transmit data is driven on falling edge of CLKX.

FSRP=FSXP=0, frame-sync pulses are active high.FSRP=FSXP=0, frame-sync pulses are active high. DRSTAT=0, DXSTAT=0, not applicable here.DRSTAT=0, DXSTAT=0, not applicable here. CLKSTAT=0,not applicable here.CLKSTAT=0,not applicable here. SCLKME=1, SRGR input clock is taken from CLKR pin SCLKME=1, SRGR input clock is taken from CLKR pin

(CLKSM=0).(CLKSM=0). CLKRM=CLKXM=0, not in DLB so the CLKR and CLKX CLKRM=CLKXM=0, not in DLB so the CLKR and CLKX

pins are inputs that suppies the internal clocks.pins are inputs that suppies the internal clocks. FSRM=FSXM=0, Receive and transmit frame-sync is FSRM=FSXM=0, Receive and transmit frame-sync is

supplied by an ext source via FSR and FSX pins.supplied by an ext source via FSR and FSX pins. RIOEN=XIOEN=0, the McBSP pins are not GPIO pinsRIOEN=XIOEN=0, the McBSP pins are not GPIO pins IDLEEN=0, the McBSP remains active when the PERIPH IDLEEN=0, the McBSP remains active when the PERIPH

domain is idled.domain is idled. RCERx and XCREx = 0, There is no multichannel RCERx and XCREx = 0, There is no multichannel

selectionselection


ESIEE, Slide 65

Example using the ‘C5416 DSK 1 of 2Example using the ‘C5416 DSK 1 of 2 Create a new project iomcbsp.pjt and Create a new cdb file Create a new project iomcbsp.pjt and Create a new cdb file


ESIEE, Slide 66

Example using the ‘C5416 DSK 2 of 2Example using the ‘C5416 DSK 2 of 2 Save (File>Save) the new configuration file Save (File>Save) the new configuration file

under the project directory: iomcbsp.cdbunder the project directory: iomcbsp.cdb Add to the project two of the files generated Add to the project two of the files generated

at the previous step: the configuration file at the previous step: the configuration file (*.cdb) and the linker command file (*.cmd).(*.cdb) and the linker command file (*.cmd).

Copy the file audioIO.c of chapter ‘ example Copy the file audioIO.c of chapter ‘ example in the project directory and rename it in the project directory and rename it iomcbsp.ciomcbsp.c

Modify the main source file: iomcbsp to Modify the main source file: iomcbsp to include the header file iomcbspcfg.h include the header file iomcbspcfg.h generated at the configuration step generated at the configuration step

and add iomcbsp.c to the project.and add iomcbsp.c to the project. Modify build options:Modify build options:

Project>Build Options to add the Project>Build Options to add the dsk5416f.lib library and set use far calls.dsk5416f.lib library and set use far calls.


ESIEE, Slide 67

Configuring the McBSP using the McBSP Configuring the McBSP using the McBSP Configuration Manager of the CSL GUIConfiguration Manager of the CSL GUI


ESIEE, Slide 68

Configuring the McBSP using the CSL GUI 1 of 4Configuring the McBSP using the CSL GUI 1 of 4


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Modify:Modify: « Receive Lengths », « Transmit Lengths » to set « Receive Lengths », « Transmit Lengths » to set

word length to 32 bitsword length to 32 bits « Sample_Rate Gen », « Sample_Rate Gen »,

choose generator clock source=BCLKRchoose generator clock source=BCLKR set frame width to 32 and frame period to 64.set frame width to 32 and frame period to 64.

« Transmit Mode », clock polarity = falling edge« Transmit Mode », clock polarity = falling edge « General »« General »

Set Breakpoint Emulation to do not stop to set FREE = 1.Set Breakpoint Emulation to do not stop to set FREE = 1.

Save the new iomcbsp.cdb file and look at the Save the new iomcbsp.cdb file and look at the iomcbspcfg_c.c file. It should be quite similar to iomcbspcfg_c.c file. It should be quite similar to the audioIOcfg_c.c file for the initialization the audioIOcfg_c.c file for the initialization part.part.


ESIEE, Slide 72

View of iomcbspcfg_c.c file at this StepView of iomcbspcfg_c.c file at this Step /* Do *not* directly modify this file. It was */

/* generated by the Configuration Tool; any */ /* changes risk being overwritten. */ /* INPUT iomcbsp.cdb */ /* Include Header File */ #include "iomcbspcfg.h" /* Config Structures */ MCBSP_Config mcbspCfg0 = { 0x0000, /* Serial Port Control Register 1 */ 0x0200, /* Serial Port Control Register 2 */ 0x00a0, /* Receive Control Register 1 */ 0x0000, /* Receive Control Register 2 */ 0x00a0, /* Transmit Control Register 1 */ 0x0000, /* Transmit Control Register 2 */ 0x1f00, /* Sample Rate Generator Register 1 */ 0x003f, /* Sample Rate Generator Register 2 */ 0x0000, /* Multichannel Control Register 1 */ 0x0000, /* Multichannel Control Register 2 */ 0x0083, /* Pin Control Register */ 0x0000, /* Receive Channel Enable Register Partition A */ 0x0000, /* Receive Channel Enable Register Partition B */ 0x0000, /* Receive Channel Enable Register Partition C */ 0x0000, /* Receive Channel Enable Register Partition D */ 0x0000, /* Receive Channel Enable Register Partition E */ 0x0000, /* Receive Channel Enable Register Partition F */ 0x0000, /* Receive Channel Enable Register Partition G */ 0x0000, /* Receive Channel Enable Register Partition H */ 0x0000, /* Transmit Channel Enable Register Partition A */ 0x0000, /* Transmit Channel Enable Register Partition B */ 0x0000, /* Transmit Channel Enable Register Partition C */ 0x0000, /* Transmit Channel Enable Register Partition D */ 0x0000, /* Transmit Channel Enable Register Partition E */ 0x0000, /* Transmit Channel Enable Register Partition F */ 0x0000, /* Transmit Channel Enable Register Partition G */ 0x0000 /* Transmit Channel Enable Register Partition H */ }; /* Handles */ /* * ======== CSL_cfgInit() ======== */ void CSL_cfgInit() { }


ESIEE, Slide 73

Configuring the McBSP using the Resource Configuring the McBSP using the Resource Manager of the CSL GUIManager of the CSL GUI

Use the McBSP Resource Manager Use the McBSP Resource Manager menu to generate the menu to generate the MCBSP_open()and the MCBSP_open()and the MCBSP_config() CSL functions.MCBSP_config() CSL functions.

It allows to select, open, initialize a It allows to select, open, initialize a devicedevice We select McBSP 2We select McBSP 2 We ask for the McBSP handle creation We ask for the McBSP handle creation

with the name C54XX_DMA_MCBSP that with the name C54XX_DMA_MCBSP that will be used by the routines of the BSL.will be used by the routines of the BSL.

And we ask for the opening of the McBSP And we ask for the opening of the McBSP handle and for the pre-initialization with handle and for the pre-initialization with object mcbspCfg0.object mcbspCfg0.


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Save the file iomcbsp.cdb Save the file iomcbsp.cdb Open the file iomcbspcfg_c.c Open the file iomcbspcfg_c.c

You should see the instructions for the You should see the instructions for the opening and initialization of the McBSPopening and initialization of the McBSP..


ESIEE, Slide 78

Final version of the iomcbspcfg_c.c FileFinal version of the iomcbspcfg_c.c File /* Do *not* directly modify this file. It was */

/* generated by the Configuration Tool; any */ /* changes risk being overwritten. */ /* INPUT iomcbsp.cdb */ /* Include Header File */ #include "iomcbspcfg.h" /* Config Structures */ MCBSP_Config mcbspCfg0 = { 0x0000, /* Serial Port Control Register 1 */ 0x0200, /* Serial Port Control Register 2 */ 0x00a0, /* Receive Control Register 1 */ 0x0000, /* Receive Control Register 2 */ 0x00a0, /* Transmit Control Register 1 */ 0x0000, /* Transmit Control Register 2 */ 0x1f00, /* Sample Rate Generator Register 1 */ 0x003f, /* Sample Rate Generator Register 2 */ 0x0000, /* Multichannel Control Register 1 */ 0x0000, /* Multichannel Control Register 2 */ 0x0083, /* Pin Control Register */ 0x0000, /* Receive Channel Enable Register Partition A */ 0x0000, /* Receive Channel Enable Register Partition B */ 0x0000, /* Receive Channel Enable Register Partition C */ 0x0000, /* Receive Channel Enable Register Partition D */ 0x0000, /* Receive Channel Enable Register Partition E */ 0x0000, /* Receive Channel Enable Register Partition F */ 0x0000, /* Receive Channel Enable Register Partition G */ 0x0000, /* Receive Channel Enable Register Partition H */ 0x0000, /* Transmit Channel Enable Register Partition A */ 0x0000, /* Transmit Channel Enable Register Partition B */ 0x0000, /* Transmit Channel Enable Register Partition C */ 0x0000, /* Transmit Channel Enable Register Partition D */ 0x0000, /* Transmit Channel Enable Register Partition E */ 0x0000, /* Transmit Channel Enable Register Partition F */ 0x0000, /* Transmit Channel Enable Register Partition G */ 0x0000 /* Transmit Channel Enable Register Partition H */ }; /* Handles */ MCBSP_Handle C54XX_DMA_MCBSP_hMcbsp; /* * ======== CSL_cfgInit() ======== */ void CSL_cfgInit() { C54XX_DMA_MCBSP_hMcbsp = MCBSP_open(MCBSP_PORT2, MCBSP_OPEN_RESET); MCBSP_config(C54XX_DMA_MCBSP_hMcbsp, &mcbspCfg0); }

Opening and initialization Opening and initialization of McBSP2of McBSP2

Creation of the McBSP handleCreation of the McBSP handle


ESIEE, Slide 79

Test the iomcbsp programTest the iomcbsp program

Build the projectBuild the project Load iomcbsp.out in Program memoryLoad iomcbsp.out in Program memory Check the programCheck the program

using a microphone (or a CD output) and using a microphone (or a CD output) and earphones, you should hear the input (mike earphones, you should hear the input (mike or CD) in the earphones (or loudspeaker).or CD) in the earphones (or loudspeaker).

Use tools>C54xx McBSP to view all the Use tools>C54xx McBSP to view all the registers of the McBSP.registers of the McBSP.


ESIEE, Slide 80

ReferencesReferences

User’s guidesUser’s guides Spru302: Spru302:

TMS320C54x DSP Reference Set Volume 5: TMS320C54x DSP Reference Set Volume 5: Enhanced Peripherals.Enhanced Peripherals.

Tms320c5416.pdfTms320c5416.pdf Spru592a:Spru592a:

TMS320VC5501/5502/5509/5510 DSP TMS320VC5501/5502/5509/5510 DSP Multichannel Buffered Serial Port (McBSP) Multichannel Buffered Serial Port (McBSP) Reference Guide.Reference Guide.

dsp c5000 chapter 9 understanding and programming the multi-channel buffered serial port (mcbsp)...

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