cse140: components and design techniques for digital

Sources: TSR, Katz, Boriello & Vahid

CSE140: Components and Design Techniques

for Digital Systems

Midterm Information

Instructor: Mohsen Imani


Midterm Topics

2

In general: everything that was covered in homework 1 and 2 and related

lectures, such as:

• Transistors

• Boolean algebra

• Basic gates

• Logic functions and truth tables

• Canonical forms (SOP and POS)

• Two-level logic minimization

• Kmaps

• Multiplexers (behavior and how to implement logic functions with them)

• Decoders (behavior and how to implement logic functions with them)

Midterm is in PCYNH 122 on Thr 08/24


Midterm Logistics

3

• Do not start the exam until you are told.• Write your name and PID at the top of every page. Write the names of people on your left

and right on the first page.• Turn off and put away all your electronics.• This is a closedbook, closednotes exam. • If you have a question, raise your hand and an exam proctor will come to you.• You have 60 minutes to finish the exam. When the time is finished, you must stop writing.• Report the solutions in the spaces provided.• Only the front pages will be graded. We will not consider anything written on the back of

the pages.• Any student violating UCSD's Academic Dishonesty or UCSD's Student Conduct policies will

earn an 'F' in the CSE140 course and will be reported to their college Dean for administrative processing.

• When returning your exam, also show your student ID.• Write your answers in the space provided. To get the most partial credit, clearly show all

the steps of your work.• Full credit may not be given for correct answers with no work shown.



for Digital Systems

Sequential Circuit Introduction

Latches and Flip-Flops


– S = 1, R = 0:

then Q = 1 and Q = 0

– S = 0, R = 1:

then Q = 1 and Q = 0

SR Latch Analysis

R

S

Q

Q

N1

N2

0

1

1

00

0

R

S

Q

Q

N1

N2

1

0

0

10

1


R

S

Q

Q

N1

N2

0

0

R

S

Q

Q

N1

N2

0

0

0

Qprev

= 0 Qprev

= 1– S = 0, R = 0:

then Q = Qprev

– Memory!

– S = 1, R = 1:

then Q = 0, Q = 0

– Invalid State

Q ≠ NOT Q

SR Latch Analysis

R

S

Q

Q

N1

N2

1

1

0

00

0


S

R Q

Q

SR Latch

Symbol

• SR stands for Set/Reset Latch

– Stores one bit of state (Q)

• Control what value is being stored with S, R

inputs

– Set: Make the output 1

(S = 1, R = 0, Q = 1)

– Reset: Make the output 0

– (S = 0, R = 1, Q = 0)

– Hold: Keep data stored

(S = 0, R = 0, Q = Qprevious)

SR Latch Symbol


Avoiding S=R=1 Part 1:

Level-Sensitive SR Latch

• Add input “C”

– Change C to 1 only after S and R are stable

– C is usually a clock (CLK)

R1

S1S

C

R

Level-sensitive SR latch

Q


D Latch Truth Table

S

R Q

Q

Q

QD

CLKD

R

S

S R Q

0 0 Qprev

0 1 0

1 0 1

Q

1

0

CLK D

0 X

1 0

1 1

D

X

1

0

Qprev


D Latch

Symbol

CLK

D Q

Q

• Two inputs: CLK, D

– CLK: controls when the output changes

– D (the data input): controls what the output changes to

• Function

– When CLK = 1,

D passes through to Q (transparent)

– When CLK = 0,

Q holds its previous value (opaque)

• (Mostly) avoids invalid case Q = Q’

D Latch Summary


D Latch Truth Table

S

R Q

Q

Q

QD

CLKD

R

S

S R Q

0 0 Qprev

0 1 0

1 0 1

Q

1

0

CLK D

0 X

1 0

1 1

D

X

1

0

Qprev


D-Latch

12https://courses.cs.washington.edu/courses/cse370/08wi/pdfs/lectures/14-Flip-flops.pdf


The D flip-flop

13https://courses.cs.washington.edu/courses/cse370/08wi/pdfs/lectures/14-Flip-flops.pdf


Latches versus flip-flops

14


The master-slave D

15

http://www.falstad.com/circuit/e-masterslaveff.html


Bit Storage Overview

16

D flip-flop

D latch

master

D latch

servant

DmQm

Cm

DsD

Clk

Qs’

Cs Qs

Q’

Q

S

R

D

Q

C

D latch

Only loads D value present at

rising clock edge, so values

can’t propagate to other flip-

flops during same clock cycle.

Tradeoff: uses more gates

internally than D latch, and

requires more external gates

than SR – but gate count is

less of an issue today.

SR can’t be 11 if D is

stable before and while

C=1, and will be 11 for only

a brief glitch even if D

changes while C=1.

Problem: C=1 too long

propagates new values

through too many latches:

too short may not enable a

store.

S1

R1

S

Q

C

R

Level-sensitive SR latch

S and R only have effect

when C=1. We can

design outside circuit so

SR=11 never happens

when C=1. Problem:

avoiding SR=11 can be a

burden.

R (reset)

S (set)

Q

SR latch

S=1 sets Q to 1,

R=1 resets Q to 0.

Problem: SR=11

yield undefined Q.


Rising vs. Falling Edge D Flip-Flop

17

D Q’

Q

Q’D

Q

Symbol for rising-edge

triggered D flip-flop

Symbol for falling-edge

triggered D flip-flop

Clk

rising edges

Clk

falling edges

Internal design:

Just invert servant

clock rather than

master

The triangle

means clock

input, edge

triggered


Internal

Circuit

D Q

CLKEN

DQ

0

1D Q

EN

Symbol

• Inputs: CLK, D, EN– The enable input (EN) controls when new data (D) is stored

• Function– EN = 1: D passes through to Q on the clock edge

– EN = 0: the flip-flop retains its previous state

Enabled D-FFs


Additional D-FF Features

19

• Reset (set state to 0) – R

– synchronous: Dnew = R' • Dold (when next clock edge arrives)

– asynchronous: doesn't wait for clock

• Preset or set (set state to 1) – S (or sometimes P)

– synchronous: Dnew = Dold + S (when next clock edge arrives)

– asynchronous: doesn't wait for clock

• Both reset and preset

– Dnew = R' • Dold + S (set-dominant)

– Dnew = R' • Dold + R'S (reset-dominant)

• Selective input capability (input enable or load) – LD or EN

– multiplexor at input: Dnew = LD' • Q + LD • Dold

– load may or may not override reset/set (usually R/S have priority)


Registers and Counters

20


Building blocks with FFs: Basic Register

21

I3 I2 I1 I0

Q3 Q2 Q1Q0

reg(4)D Q D Q D Q D Q

OUT1 OUT2 OUT3 OUT4

CLK

IN1 IN2 IN3 IN4

• Register: a sequential component that can store multiple bits

• A basic register can be built simply by using multiple D-FFs


Shift register

• Holds & shifts samples of input

22

D Q D Q D Q D QIN

OUT1 OUT2 OUT3 OUT4

CLK


Pattern Recognizer

• Combinational function of input samples

23

D Q D Q D Q D QIN

OUT1 OUT2 OUT3 OUT4

CLK

OUT


Counters

24

D Q D Q D Q D QIN

OUT1 OUT2 OUT3 OUT4

CLK

• Sequences through a fixed set of patterns

• Note: definition is general

• For example, the one in the figure is a type of counter

called Linear Feedback Shift Register (LFSR)


General Counters

25

EN

DCBA

LOAD

CLK

CLR

RCO

QDQCQBQA

"1"

"0""0""0""0"

"0"

EN

DCBA

LOAD

CLK

CLR

RCO

QDQCQBQA

"1"

"0""1""1""0"

•Default operation: count up

•QA-QD counter output

•A-D parallel load data

•LOAD enables data load

•RCO ripple carry out

•CLR clears data

•EN counter enable

Similar signals can also be

used for registers

You can generalize these ideas to build

multifunction registers/shifters/counters with a

variety of control signals (load, clear, enable, etc.)


Finite State Machines

26


Circuit Specifications

• Combinational Logic– Truth tables, Boolean equations, logic diagrams (no feedback)

• Sequential Networks: State Diagram (Memory)– State and Excitation Tables

– Characteristic Expression

– Logic Diagram (FFs and feedback loops)

27

Combinational

CLK CLK

A B C DX

Y

CLKRTL: Register-Transfer Level Description


Finite State Machines: Two Bit Counter Example

S0S0

S1S1

S2S2

S3S3

State Diagram State Table

Q1(t) Q0(t) Q1(t+1) Q0(t+1)

0 0 0 1

0 1 1 0

1 0 1 1

1 1 0 0

Current

state

Next State

S0 S1

S1 S2

S2 S3

S3 S0

2 bit Counter

Symbol/ CircuitFor example:

S0: Breakfast

S1: Lunch

S2: Dinner

S3: Sleep

For example:

Count up to 11


29

Q1(t) Q0(t) Q1(t+1) Q0(t+1)

0 0 0 1

0 1 1 0

1 0 1 1

1 1 0 0


State Table

Q1(t) Q0(t) Q1(t+1) Q0(t+1)

0 0 0 1

0 1 1 0

1 0 1 1

1 1 0 0

Which is the most likely circuit realization of the two

bit counter?

Q0(t)

Q1(t)

DQ

Q’

DQ

Q’

CLK

Circuit with 2 flip flops

B.

Combinational

circuit

Combinational

circuit

Circuit with no flip flops

A.

Q0(t)

Q1(t)

DQ

Q’

CLK

Circuit with one flip flop

C.

Combinational

circuit


State Table

Q1(t) Q0(t) Q1(t+1) Q0(t+1)

0 0 0 1

0 1 1 0

1 0 1 1

1 1 0 0

D0(t) = Q0(t)’

D1(t) = Q0(t) Q1(t)’ + Q0(t)’ Q1(t)

Two Bit Counter Circuit

Q0(t)

Q1(t)

DQ

Q’

DQ

Q’

CLK

Implementation of 2-bit counter

We store the current state

using D-flip flops so that:

• Inputs to the combinational

circuit don’t change while

the next output is

computed

• The transition to the next

state only occurs at the

rising edge of the clockD0(t)

D1(t)


FSM Definition

• FSM consists of

– Set of states

– Set of inputs, set of outputs

– Initial state

– Set of transitions

• Only one can be true at a time

• FSM representations:

– State diagram

– State table

32

a

b

I

A

B


FSM Controller Design Process with a

Three Bit Counter Example

33

C3 C2 C1 N3 N2 N1

0 0 0 0 0 1

0 0 1 0 1 0

0 1 0 0 1 1

0 1 1 1 0 0

1 0 0 1 0 1

1 0 1 1 1 0

1 1 0 1 1 1

1 1 1 0 0 0

010

100

110

011001

000

101111

3-bit up-counter

D Q D Q D Q

OUT1 OUT2 OUT3

CLK

"1"

FSM

State Table with Assigned State Patterns Circuit

1. State Diagram

2. State Table

3. State Assignments

4. Excitation Table

(present state, inputs; next state, outputs)

5. Circuit


C1 C2

CLK

x(t)

y(t)

Mealy Machine

S(t)

C1 C2

CLK

x(t) y(t)

Moore Machine

S(t)

Mealy and Moore Machines

Output is the only function of current state

ONLY!

Output is the function of the present state

as well as the input!

yi(t) = fi(X(t), S(t))yi(t) = fi(S(t))


35

A. Mealy State machine

B. Moore state machine

C. Can be both

D. I don’t know

What’s this state machine?


Life on Mars?

36

This pattern recognizer should have

A.One state because it has one output

B.One state because it has one input

C.Two states because the input can be 0 or 1

D.More than two states because ….

E.None of the above

Mars rover has a binary input x. When it receives the input

sequence x(t-2, t) = 001 from its life detection sensors, it

means that the it has detected life on Mars and the output

y(t) = 1, otherwise y(t) = 0 (no life on Mars).


Mars Life Recognizer FSM

37

S1S00/0

1/0

0/0

1/1

S20/0

1/0

Which of the following diagrams is a correct Mealy solution

for the 001 pattern recognizer on the Mars rover?

A.

S1S00/0

1/0

1/0

0/0

S21/1

B. 0/0

C. Both A and B are correct

D. None of the above


38

State Diagram => State Table with State Assignment

State Assignment

S0: 00

S1: 01

S2: 10

S(t)\x 0 1

S0 S1,0 S0,0

S1 S2,0 S0,0

S2 S2,0 S0,1

S(t)\x 0 1

00 01,0 00,0

01 10,0 00,0

10 10,0 00,1

Q1(t+1)Q0(t+1), y

C1 C2

CLK

x(t)

y(t)

Mealy Machine

S(t)

S1S00/0

1/0

0/0

1/1

S20/0

1/0


39

State Diagram => State Table => Excitation Table => Circuit

Q1(t) Q0(t)\x 0 1

00 01,0 00,0

01 10,0 00,0

10 10,0 00,1

id Q1Q0x D1 D0 y

0 000 0 1 0

1 001 0 0 0

2 010 1 0 0

3 011 0 0 0

4 100 1 0 0

5 101 0 0 1

6 110 X X X

7 111 X X X

C1 C2

CLK

x(t)

y(t)

Mealy Machine

S(t)


40

0 2 6 4

1 3 7 5

x(t)

Q1

0 1 X 1

0 0 X 0

Q0D1(t):

D1(t) = x’Q0 + x’Q1

D0 (t)= Q’1Q’0 x’

y= Q1x


id Q1Q0x D1 D0 y

0 000 0 1 0

1 001 0 0 0

2 010 1 0 0

3 011 0 0 0

4 100 1 0 0

5 101 0 0 1

6 110 X X X

7 111 X X X


41

D1(t) = x’Q0 + x’Q1

D0 (t)= Q’1Q’0 x’

y= Q1x

DQ

Q’

DQ

Q’

Q1

Q0

D1

D0

Q0

Q1

x’

x

y

Q’1

Q’0

x’


C1 C2

CLK

x(t)

y(t)

Mealy Machine

S(t)


Q1Q0\x 0 1

00 01,0 00,0

01 10,0 00,0

10 10,0 11,0

11 01,1 00,1

Q1(t+1)Q0(t+1), y

ID Q1Q0x D1 D0 y

0 000 0 1 0

1 001 0 0 0

2 010 1 0 0

3 011 0 0 0

4 100 1 0 0

5 101 1 1 0

6 110 0 1 1

7 111 0 0 1

S(t)\x 0 1

S0 S1,0 S0,0

S1 S2,0 S0,0

S2 S2,0 S3,0

S3 S1,1 S0,1

Moore Mars Life Recognizer: Summary

S1

0

S0

0

0

1

0

1S2

0

0

1

S3

1

1 0


id Q1Q0x D1 D0 y

0 000 0 1 0

1 001 0 0 0

2 010 1 0 0

3 011 0 0 0

4 100 1 0 0

5 101 1 1 0

6 110 0 1 1

7 111 0 0 1

0 2 6 4

1 3 7 5

x(t)

Q1

1 0 1 0

0 0 0 1

Q0D0(t):

0 2 6 4

1 3 7 5

x(t)

Q1

0 1 0 1

0 0 0 1

Q0D1(t):

0 2 6 4

1 3 7 5

x(t)

Q1

0 0 1 0

0 0 1 0

Q0y(t):

Mars Life Recognizer: Summary


44


45


for Digital Systems

Review questions


Example 1: Multiplexers

01

00

10

11

4:1 MUX

s1 s0

b d

a

c

c

b

d

outw

z

• Derive each intermediate signal as a function of a, b, c and d

1

s


Example 2: Multiplexers

• Implement the following function using a 4:1 MUX

F(a,b,c) = a’b’c + a(bc +bc’)


Example 3: Decoders

48

A0

A1

3:8 Decoder

000

001

010

011

100

101

110

111

A2

A0 A1 A2

a

c’

w

a

b

• Derive each intermediate signal as a function of a, b, and c

s

z

out


Example 4: Decoders

49

• Implement the following function using a 3:8 Decoder

F(a,b,c) = abc + a(b’c +bc’)


50

Multiple-Output Circuits

• Many circuits have more than one output

• Can give each a separate circuit, or can share gates

• Ex: F = ab + c’, G = ab + bc

Option 1: Separate circuits Option 2: Shared gates


Primes and Essential Primes

Given the following function:

F(A,B,C,D) =∑m(0,2,6,7,8,10) + ∑d(1,11,12,15)

a) List all prime implicants

b) Identify the essential prime implicants

c) Give min cover in SoP (Sum-of-Product) form

51

A

D

C

B


K-maps and Muxes

52

A

D

C

B

F(A,B,C,D)= Π M(2, 3, 6, 8, 9, 12, 13, 14)


Mux/Demux

53


Design problem – distance between numbers

• Design a circuit that gives the absolute distance between

the two numbers (e.g. x=3 y=1 d=2)

54


NAND gates implementation

55


Decoder

• Implement F(A,B, C) = A’C’ + AC’ with a minimum size

circuit. You may use a 2:4 decoder and minimum number of

other gates.

56

cse140: components and design techniques for digital

Documents