CSE140: Components and Design Techniques CSE140: Components and Design Techniques for Digital Systems

Boolean algebra & logic circuits

Tajana Simunic Rosing

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Boolean algebrag• Boolean Algebra

– B = {0, 1} { , }– Variables represent 0 or 1 only– Operators return 0 or 1 only

Basic operators– Basic operators• • is logical AND: a AND b returns 1 only when both a=1 and b=1• + is logical OR: a OR b returns 1 if either (or both) a=1 or b=1

’ is logical NOT: NOT a returns the opposite of a (1 if a=0 0 if a=1)• ’ is logical NOT: NOT a returns the opposite of a (1 if a=0, 0 if a=1) – All algebraic axioms hold

a b ANDa b OR0011

0101

0001

0011

0101

0111

a01

NOT10

OR AND NOT

2

xy F F

xy

Fx

Axioms and theorems of Boolean algebrag• identity

1. X + 0 = X 1D. X • 1 = X• null

2. X + 1 = 1 2D. X • 0 = 0• idempotency:

3. X + X = X 3D. X • X = X• involution:

4. (X’)’ = X• complementarity:

5. X + X’ = 1 5D. X • X’ = 0• commutativity:y

6. X + Y = Y + X 6D. X • Y = Y • X• associativity:

7. (X + Y) + Z = X + (Y + Z) 7D. (X • Y) • Z = X • (Y • Z)

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( ) ( ) ( ) ( )

Axioms and theorems of Boolean algebra (cont’d)• distributivity:

8. X • (Y + Z) = (X • Y) + (X • Z) 8D. X + (Y • Z) = (X + Y) • (X + Z)

• uniting:9. X • Y + X • Y’ = X 9D. (X + Y) • (X + Y’) = X

• absorption:10. X + X • Y = X 10D. X • (X + Y) = X11. (X + Y’) • Y = X • Y 11D. (X • Y’) + Y = X + Y

• factoring:12. (X + Y) • (X’ + Z) = 12D. X • Y + X’ • Z =

X • Z + X’ • Y (X + Z) • (X’ + Y)• concensus:

13. (X • Y) + (Y • Z) + (X’ • Z) = 13D. (X + Y) • (Y + Z) • (X’ + Z) =X • Y + X’ • Z (X + Y) • (X’ + Z)

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Axioms and theorems of Boolean algebra (cont’d)

• de Morgan’s:g14. (X + Y + ...)’ = X’ • Y’ • ...14D. (X • Y • ...)’ = X’ + Y’ +

...li d d M ’• generalized de Morgan’s:

15. f’(X1,X2,...,Xn,0,1,+,•) = f(X1’,X2’,...,Xn’,1,0,•,+)

• establishes relationship between • and +

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Axioms and theorems of Boolean algebra (cont’d)• Duality

– a dual of a Boolean expression is derived by replacing • by +, + by •, 0 by 1, and 1 by 0, and leaving variables unchanged

– any theorem that can be proven is thus also proven for its dual!– a meta-theorem (a theorem about theorems)

• duality:16. X + Y + ... ⇔ X • Y • ...

• generalized duality:generalized duality:17. f (X1,X2,...,Xn,0,1,+,•) ⇔ f(X1,X2,...,Xn,1,0,•,+)

Diff t th d M ’ L• Different than deMorgan’s Law– this is a statement about theorems– this is not a way to manipulate (re-write) expressions

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Proving theoremsg• Using the axioms of Boolean algebra:

– e.g., prove the theorem: X • Y + X • Y’ = Xg , p

distributivity (8) X • Y + X • Y’ = X • (Y + Y’)complementarity (5) X • (Y + Y’) = X • (1)p y ( ) ( ) ( )identity (1D) X • (1) = X

– e.g., prove the theorem: X + X • Y = X

identity (1D) X + X • Y = X • 1 + X • Yidentity (1D) X + X • Y = X • 1 + X • Ydistributivity (8) X • 1 + X • Y = X • (1 + Y)identity (2) X • (1 + Y) = X • (1)identity (1D) X • (1) = X

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Proving theorems exampleg p• Prove the following using the laws of Boolean algebra:

– (X • Y) + (Y • Z) + (X’ • Z) = X • Y + X’ • Z( ) ( ) ( )

(X • Y) + (Y • Z) + (X’ • Z)

identity (X • Y) + (1) • (Y • Z) + (X’ • Z)

complementarity (X • Y) + (X’ + X) • (Y • Z) + (X’ • Z)

distributivity (X • Y) + (X’ • Y • Z) + (X • Y • Z) + (X’ • Z)

commutativity (X • Y) + (X • Y • Z) + (X’ • Y • Z) + (X’ • Z)

factoring (X • Y) • (1 + Z) + (X’ • Z) • (1 + Y)

null (X • Y) • (1) + (X’ • Z) • (1)

8identity (X • Y) + (X’ • Z)

Proving theorems (perfect induction)g (p )• Using perfect induction (complete truth table):

– e.g., de Morgan’s:

X Y X’ Y’ (X + Y)’ X’ • Y’

g , g

(X + Y)’ = X’ • Y’NOR is equivalent to AND with inputs complemented

X Y X Y (X + Y) X • Y0 0 1 10 1 1 01 0 0 11 1 0 0

(X • Y)’ = X’ + Y’NAND is equivalent to OR

X Y X’ Y’ (X • Y)’ X’ + Y’0 0 1 10 1 1 01 0 0 1with inputs complemented 1 0 0 11 1 0 0

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Example that Applies Boolean Algebra Propertiesp pp g p• Want automatic door opener

circuit (e.g., for grocery store)• Found inexpensive chip that

computes:– Output: f=1 opens door– Inputs:

• p=1: person detectedh 1 it h f i h ld

• f = c’hp + c’hp’ + c’h’p– Can we use it?

• h=1: switch forcing hold open• c=1: key forcing closed

– Want open door when• h=1 and c=0, or,• h=0 and p=1 and c=0

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CSE140: Components and Design Techniques for Digital Systems

Combinational circuit building blocks:Building gates from transistors

Tajana Simunic Rosing

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Inverter delay• Delay: estimate using Rn & Cg; RP=2Rn

Fx

NOT

x01

F10

x

1

F = x’

1 11 1

x

0 0 00 0

1

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Basic CMOS gates

Fxxy F

NORNOT

Fx

NAND 1

x y

1y

x001

y010

F111

x001

y010

F100

x01

F10

y yy

Fy

xx

x

y

F

1 1 01 1 0

x

001

F = x’x

0

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• Implement logic operators using transistors– Call those implementations logic gates

AND/OR gatesg

OR AND

• OR/AND are harder to make than NOR/NAND

x0

y0

F0

x0

y0

F0

xy F F

xy

011

101

001

011

101

111

1 11

F= x or y

1

x y

F’y

y

x

1

F=x & yF’

0

0

y

x0

xy

0

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Completeness of NANDp• Any logic function can be implemented using just NAND

gates. Likewise for NOR. Why?g y– Need AND, OR and NOT

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XOR/XNOR Gates

• XOR = x’y + xy’ = ( xy + x’y’)’ (Exclusive OR)XOR XNOR

• XNOR = (x’y + xy’)’ = xy + x’y’ (Exclusive OR)x00

y01

F10

x00

y01

F01

11

01

01

11

01

10

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Number of Possible Boolean Functions• # of possible functions of 2 variables:

– 22 rows in truth table, 2 choices for each2(22) 24 16 ibl f ti

a00

b01

0 or 1 2 choices0 or 1 2 choices

F

– 2(2 ) = 24 = 16 possible functions• N variables

– 2N rows2(2N) possible functions

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01

0 or 1 2 choices0 or 1 2 choices

24 = 16possible functions– 2(2 ) possible functions

• Cost

p

f0000

b010

a001

f1000

f2001

f3001

f4010

f5010

f6011

f7011

f8100

f9100

f10101

f11101

f12110

f13110

f14111

f151110

001

11

01

10

11

00

01

10

11

00

01

10

11

00

01

10

11

0

AND

b a b

XOR

b

OR

b

NO

R b

NO

R b b’ a’

AND

b 1

a A

a X a

a N

a XN

a N

A

• a’ (F12) and b’ (F10): require 2 transistors for an inverter (not gate)• a nor b (F4) and a nand b (F14): require 4 transistors

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a nor b (F4) and a nand b (F14): require 4 transistors • a or b (F7) and a and b (F1): require 6 transistors • a = b (F9) and a ⊕ b (F6): require 12 transistors

Circuits for binary additionAi Bi Sum Cout0 0 0 00 1 1 0

y• Half adder (add 2 1-bit numbers)

– Sum =0 1 1 01 0 1 01 1 1 1

– Cout =

• Full adder (carry-in to cascade for multi-bit adders)Ai Bi Cin Sum Cout0 0 0 0 00 0 1 1 00 1 0 1 0

( y )– Sum =– Cout =

0 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 1

AB

S1 1 0 0 11 1 1 1 1

CinS

AB

CinCout

18AB

Cout

Example: 4-bit binary adderp y• Inputs: A, B, Carry-in• Outputs: Sum Carry-out A A A A A

CinCout

Outputs: Sum, Carry out

AB

Cout

S

A A A A AB B B B B

S S S S S

CinCout

a3

FA

b3 a2b2

cibaFA

ciba

a1b1

FAciba

a0 b0 ci

FAciba

co s

co s3 s2 s1

co s co s

s0

co s

(a)

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Choosing different realizations of a function

A B C Z0 0 0 00 0 1 10 1 0 0

Which is the best realization and why?

• Reduce number of levels of gatesfewer level of gates implies reduced signal0 1 0 0

0 1 1 11 0 0 01 0 1 11 1 0 1

– fewer level of gates implies reduced signal propagation delays

– minimum delay configuration typically requires more gates

• Reduce number of inputs1 1 1 0

two-level

• Reduce number of inputs– fewer inputs implies smaller and thus

faster gates; fan-in can be limited• Reduce number of gates

f t ll i ittwo-level realization

– fewer gates means smaller circuits -directly influences manufacturing costs

• Exploring tradeoffs between increased circuit delay and size

multi-level realization

– tools to generate different solutions– logic minimization: reduce number of

gates and complexity– logic optimization: reduction while trading

off against dela

20XOR gate

off against delay

DeMorgan and CMOSg• Use it to figure out P & NMOS parts of gates

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Rules for making gatesg g

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Another way of making CMOS gatesy g g

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CMOS Examplep

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Another examplep

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One more examplep

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CMOS Example• The rules:

– NMOS connects to GND, PMOS to power supply Vdd, p pp y– Duality of NMOS and PMOS – Rp ~ 2 Rn => PMOS in series is much slower than NMOS in series

Implement Z sing CMOS Z (A + BC)’• Implement Z using CMOS: Z = (A + BC)’

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Another CMOS Example• Implement F using CMOS: F=A*(B+C)

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Summaryy• What we covered thus far:

– Number representationsp– Switches, MOS transistors, Logic gates– Boolean algebra

Supplement: NMOS and PMOS transistor characteristics– Supplement: NMOS and PMOS transistor characteristics

• What is next:– Combinational logic:

• Representations• Minimization• Implementations

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