chp 2- mos design and layout
TRANSCRIPT
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MOS Design and Layout
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Layout (the Final Frontier!)
Schematic
Transistors
Stick Diagram
VLSI Layout
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pullup
network
VDD
pulldown
networkVSS
outinputs
CMOS Logic Circuits
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Basic Idea = duality between pull-ups and pull-downs.
The structure of the pFET array is the dual of the nFET array!
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Stick Diagrams VLSI design aims to translate circuit concepts onto
silicon.
Stick diagrams are a means of capturing topography
and layer information - simple diagrams.
Stick diagrams convey layer information throughcolor codes (or monochrome encoding.
Does not show exact placement, transistor sizes,
wire lengths, wire widths, tub boundaries, or anyother form of compliance with layout or design rules.
Useful for interconnect visualization, preliminarylayout, layout compaction, power/ground routing,
clock routing, etc.
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MOS Layers in Stick DiagramsMetal 1
Metal 2
Poly
ndiff
pdiff
Can also draw
in shades of
gray/line style.
Blue
Purple
Red
Green
Yellow
ContactsBlack
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PMOS and NMOS Stick Diagrams
S
D
G B
G B
D
S
NMOS Transistor
PMOS Transistor
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Vdd
Vss
CMOS Inverter Stick Diagram
Demarcation Line
A A
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CMOS NAND GATE
Vdd
Vss
A
B
O/P
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Stick Diagram - Example I
NOR Gate
OUT
B
A
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Logic Circuits -- Duality
1. Every input is connect to both an nFET and a pFET.
2. Two logic arrays are required - one for pull up to +5v,
one for pull down to ground.
3. When the inputs are stable, only one logic block conducts.
4. Series connected nFETs produce a NAND function.
Parallel connected nFETs produce a NOR function
5. Series connected pFETs produce a NOR function.
Parallel connected pFETs produce a NAND function
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Stick Diagram - Example II
Power
Ground
B
C
OutA
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Factors influencing MOS Layers in Stick Diagrams
Cost:
i) The Layer which costs more, should
be used few times.
ii) The Layer which costs less, shouldbe used frequently.
iii) The order of layers in terms of decreasing cost:
a)Polysilicon b) N-diff & P-diff c) Metal.
Complexity:
If the Layers cross over each other frequently, thencomplexity increases and vice-versa.
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Logic Circuits I.
Multiplexer Example
A
S
BY
Y = S * A + S * B
Y = (S*A) + (S*B)
= (S*A) * (S*B)
Y = NAND( NAND(S,A),NAND(NOT(S),B))
DEF: (P*Q) = NAND(P,Q)
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Y = NAND(NAND(S,A),NAND(NOT(S),B))
N
NS
A
Vss
Vd
P P
NAND(S,A)
N
P
NOT(S)
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Y = NAND( NAND(S,A),NAND(S,B))
Vss
Vd
N
N
P P
B
NAND(NOT(S),B)S
A N
N
P P
N
P
S
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Y = NAND(P,Q)
Vss
Vd
N
N
P P
B
S
A N
N
P P
N
P
P Q
N
N
P P
Y
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Sticks Layout for 2:1 MUX
Vdd
Vss
A
BS
S
Area = 17 * 4 = 68 2
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NMOS Encoding
Name of Layer Stick Encoding Color
Polysilicon Red
N-diff, N-active Green
Metal1 Blue
Implant Yellow
Contact Cut Black
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NMOS Depletion and Enhancement
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Stick diagram of nMOS invertor
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NMOS Logic Example
Y=(A.B+C)
A
B C
VDD
VSS
Y
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BiCMOS Encoding
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Stick diagram of BiCMOS invertor
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Layout
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Why Design Rules
When "drawing layouts from stick diagram, there are rules that apply tospacing and sizes.
Scalability of Layout is achieved by defining the unit of measure of yourdrawing.
For example, if you draw a box to represent the diffusion mask, how big isthat box in terms of the actual size of the diffusion region created in thesilicon wafer?
One approach is to set up a translation between the scale used for thedrawing.
For example, when creating this Word document, there is a "ruler" on thetop defining the page, with units "1," "2," "3," etc.
These numbers represent inches when you print out the page withmagnification = 1.
The size of the box below is easily measured with a ruler.
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DESIGN RULES
Mask layers are tools formanufacturing of ICs.
Manufacturing processes haveinherent limitations in accuracy.
Design rules specify geometry of
masks which will providereasonable yields. i.e. size andspacing of layers.
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Design rules (Contd..)
Allow translation of circuits(usually in stick diagram orsymbolic form) into actual
geometry in silicon Interface between circuit
designer and fabricationengineer
Compromise
designer - tighter,smaller
fabricator - controllable,reproducible
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Lambda Based Design Rules
Design rules based on single parameter, (lambda) :abstractunit.
Scale the design to the appropriate actual dimensions using(.25m) when the chip is to be manufactured.
Properties:
1) Simple for the designer
2) Wide acceptance
3) Provide feature size independent way of setting out mask
4) If design rules are obeyed, masks will produce working
circuits
5) Minimum feature size is defined as 2
6) Used to preserve topological features on a chip
7) Prevents shorting, opens, contacts from slipping out of area
to be contacted
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Lambda Based Design Rules
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Design rules for layers
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Design rules for Transistors
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Design rules for Contacts
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Design rules for Contacts
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Contact cuts
Butting Contact:
Poly to n-diff (p-diff)
using metal.
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Double Metal Process Rules
Metal2 is another metal layer which isDark Blue or Purple.
Metal2 should be used for global powerand Clock rails.
Metal1 should be used for local signaland power rails.
The Contact between metal2 to metal1contact is calledVIA.
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Advantages and Disadvantages
Advantages
Enables technology changes
Enable design reuse
Reduce design cost
Disadvantages Not optimal design
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2 Double Metal Double PolyCMOS/BiCMOS Rules - Layers.
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2 Double Metal Double PolyCMOS/BiCMOS Rules - Transistors
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2 Double Metal Double PolyCMOS/BiCMOS Rules - Contacts
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N-well Spacing and Width
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BiCMOS NPN Transistor Layout
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Interconnect - Wiring Concepts
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Basic Wiring Concepts Interconnections between the Layers in the IC are represented by
wires.
These Wires have parameters such as
Resistance Capacitance
Delay
Rise and Fall Time Estimation.
These parameters have different values for different Technologies
(1.2m, 2m, 5 m).
Interconnect parameters impact
reduce reliability
effect performance and power consumption
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Modern Interconnect
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RESISTANCE
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Sheet Resistance (Rs)
Resistance of a square slabof Conducting layer or
material is SheetResistance (Rs) .
Length (L) = Width (W)
Parameters of the layer.
Let is Resistivity
Let A is Area.
t w L
X
Y
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Sheet Resistance (Rs)
Rs=/t where = Resistivity,
t = Thickness,
Rs is Independent of Area of square. Rs of Layers depends on Resistivity and Thickness.
For Poly and Metal Layers
Resistivity and Thickness are known easily.
For Diffusion layers Diffusion Depth - Thickness.
Doping Level Resistivity.
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Sheet resistance for layers
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Silicide
Silicides: WSi2, TiSi2, PtSi2and TaSi
Silicides are the interconnecting medium forthe Polysilicon due to its low resitivity thanPolysilicon.
Properties: Conductivity: 8-10 times better than Poly Resistivity : very less then Poly
Examples:
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Silicide - Polycide Gate MOSFET
n+n+
SiO2PolySilicon
Silicide
p
Silicides: WSi2, TiSi2, PtSi2and TaSiConductivity: 8-10 times better than Poly
Resistivity : very less then Poly
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Dealing with Resistance
Selective Technology Scaling
Use Better Interconnect Materials
reduce average wire-length
e.g. copper, silicides
More Interconnect Layers
reduce average wire-length
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Interconnect Resistivity - Metals
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Intel 0.25 micron Process
5 metal layers
Ti/Al - Cu/Ti/TiN
Polysilicon dielectric
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CAPCITANCE
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Area Capacitance of Layers
Conductive Layers are separated by
dielectric in MOS Transistor, so parallel
plate capacitive effects must be
present.
Area Capacitance is denoted by C.
C = 0insA / D Farads
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Standard Area Capacitance values
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Standard unit of Capacitance
Standard unit of Capacitance is the
gate to channel capacitance of MOS
Transistor having W=L feature size.
It is denoted by Cg.
Cg can be evaluated for MOStransistors of different feature size.
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Multilayer capacitances
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Wiring Capacitances
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Area Capacitance - Parallel Plate Model
SiO2
Substrate
L
W
H
tox
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Fringing fields Capacitance
For wide conductors with W >> H, capacitance to substrate (of any groundplane) can be determined as a parallel plate capacitor
For most real conductors in todays IC technology, fringing fields contributea major part of the line capacitance and must be included in thecapacitance calculations.
For W =~ H (below), fringing fields add more than the parallel plate portion tothe total line capacitance.!
R. W. KnepperSC571, page 4-15
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Fringing Capacitance effect for different W,H values
W - H/2H
+
(a)
(b)
W>>H
W=H W=H/2
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Fringing Capacitance: Values
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Interlayer Capacitance
Substrate
SiO2
Insulator
Level1
Level2
Creates Cross-talk
The capacitance effects when multiple layers cross or underlies
another is known interlayer capacitance.
This Capacitance leads to Cross-talk.
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Peripheral capacitance
N-diffusion regions form junction with p-well andP-diffusion regions form junction with n-well,which leads to Peripheral capacitance.
The smaller area of diffusion regions leads tohigh value of peripheral capacitance.
Diffusion formed by implant have negligible
peripheral capacitance due to negligible depth. This capacitance value is greater than area
capacitance.
Interconnect Cross-section for Dual Metal, Single Poly System
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Delay Unit ()
When one standard gate area capacitance(1Cg) is charged through one feature size ofn-channel resistance (1Rs), then delay unit() is
= 1Rs x 1Cg sec.
Delay unit can be calculated for 5m, 2m,
1.2m technologies respectively.
value can be increased by a factor of 2 or 3,if we consider worst case delays.
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Delay Unit ()
Delay unit value is approximately equal to Transit time(sd).
Since Transit time depends on Vds, so as Delay unit ().
So, can be calculated with Vds. All timings in the system can assessed with , so is
the fundamental time unit.
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Inverter Delays
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Series NMOS Inverters Delay
Pull-down delay = Rpd x 1 Cg
Pull-up delay = Rpu x 1 Cg
Asymmetry in rise and fall due to resistance differencebetween pull-up and pull-down (factor of 4) (due to
mobilities of carriers)
Delay through a pair of inverters is (fall time) + 4
(rise time)
Delay through a pair of NMOS inverters is therefore 5
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Series CMOS Inverters Delay
Pull-down delay = Rpd x 2 Cg
Pull-up delay = Rpu x 2Cg
Asymmetry in rise and fall due to resistance differencebetween pull-up and pull-down (factor of 2.5) (due to
mobilities of carriers)
Delay through a pair of inverters is 2 (fall time) + 5
(rise time)
Delay through a pair of CMOS inverters is therefore 7
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Formal Estimation of CMOS Inverter Delay
A CMOS Inverter discharges or charges through a Loadcapacitor CL , through which we can find Rise and FallTimes.
Rise Time Estimation:
Fall Time Estimation:
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Factors effecting Rise and Fall Time Delays
Mobility:
Since mobility of electrons is 2.5 times greater thanmobility of holes, Rise times have 2.5 times more delay
than Fall times.So, the Width of P-Channel should be 2.5 times greaterthan n-channel.
Load capacitance:
Both Rise and Fall times are proportional. Source Voltage:
Both Rise and Fall times are inversely proportional.
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Effects of Delay Unit
In high speed digital circuits, signals on an interconnect line
are delayed by , which places a limiting factor on the
speed of the network
VLSI processing are directed toward minimizing both
Rsand Cg.
Circuit designers are then faced with creating the fastest
switching network within the limits of delay.
Buffers may be used in long lines to reduce the total line
delay.
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Propagation Delays
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Cascaded Pass Transistors
Pass Transistors are used in series or parallel for switchlogic.
If a signal Vdd is sent through a series of pass transistors,
then the signal is degraded to Vdd-Vtp. A pass transistor can be assumed as RC network during
the operation.
Propagation Delay (p) can be calculated w.r.t distance xof the network.
Overall Delay (d) is of n pass transistors can also becalculated through the series RC network.
If n increases then d increases. So, the max value of n=4.
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Long Poly and Diffusion wires
Long Polysilicon wires also represents RC networks,which increase signal delay.
This results in slow rise time and then noise.
If noise is present, output values will switch between0 and 1 for inverters.
Long Diffusion wires have high C value, which alsoincrease signal delay.
So both Poly and diffusion wires should be used forshorter distances only.
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Minimizing Propagation Delay
In series pass transistors network, if a repeater is placed after 4
pass transistors, then delay will be decreased.
For Polysilicon wires, use of repeaters (buffers or inverters).
1) speed-up the rise time.
2) guard the effects of noise.
So the output will not be toggled especially for inverters.
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Nature of Interconnect
Local Interconnect
Global Interconnect
SLocal = STechnology
SGlobal = SDie
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IDEAL WIRE
No impact on electrical behaviour ofcircuits
Whole wire is an equi-potential region
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Scaling of MOS Circuits
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Scaling - Introduction
VLSI technology is constantly evolvingtowards smaller line widths
Reduced feature size generally leads to Better / faster performance
More gate / chip
More accurate description of moderntechnology is ULSI (ultra large scaleintegration.
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Scaling - Introduction
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Properties of IC effected by Scaling
Minimum feature size.
Number of gates on one chip.
Power dissipation.
Maximum operational frequency.
Die size
Production cost.
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Full Scaling
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Scaling Rules
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Scaling Models
Constant Electric field Scaling
Constant Voltage Scaling
Combined Voltage and Dimensionscaling.
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Constant Electric field Scaling
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Constant Electric field ScalingBefore Scaling After scaling
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Constant Electric field Scaling
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Constant Voltage Scaling
Scaling Factors - Combined
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Scaling Factors Combinedvoltage & Dimension scaling
In our discussions we will consider 2scaling factors, and
1/ is the scaling factor for VDD andoxide thickness D
1/ is scaling factor for all other linear
dimensions We will assume electric field is kept
constant
Scaling Factors for Device
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Scaling Factors for DeviceParameters
It is important that you understand how the followingparameters are effected by scaling
Gate Area
Gate Capacitance per unit area
Gate Capacitance Charge in Channel
Channel Resistance
Transistor Delay
Maximum Operating Frequency
Transistor Current Switching Energy
Power Dissipation Per Gate (Static and Dynamic)
Power Dissipation Per Unit Area
Power - Speed Product
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Limitations of scaling
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Substrate Doping
Built-in-potential VB dependson substratedoping level NB.
VB should be added toVdd for obtainingeffective voltage.
To scale down depletion width, NB should beincreased andVB should also increase.
Then Vdd should also be scaled.
Now the total is the sum of VB andVdd
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Channel Length (L)
Scaling of Length depends on photolithographictechnology.
If Channel length (L) scaling is more, then
depletion width decreases and depletion
region of source comes closer to drain.
To maintain proper transistor action, Channel Lengthshould be twice the depletion width.
It also depends on substrate doping and supplyvoltage.
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Scaling Limits
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Scaling of Interconnects
Resistance:
Resistance of track R ~ L / wt
R (scaled) ~ (L / ) / ( (w/ )*
(t /))
R(scaled) = R
Therefore resistance increaseswith scaling.
Thickness should be scaled lessto decrease resistance.
t w L
A
B
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Scaling - Time Constant
Time constant of track connected to gate,
T = R * Cg
T(scaled) = R * ( / 2) *Cg = ( / ) *R*Cg
Let = , therefore T is unscaled!
Therefore delays in tracks dont reduce with scaling
Therefore as tracks get proportionately larger, effectgets worse
Cross talk between connections gets worse becauseof reduced spacing
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Scaling - Time Constant (Contd..)
Scaling device dimensions lengthens theinterconnections in the chip.
So resistance, capacitance and time constant
increases. The effects are
1) Increased Propagation delay.
2) Signal decay.3) Clock Skew.
But delay of device will not increase.
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Scaling - Time Constant (Contd..)
Remedies:
Multilayer interconnections with thicker and widerconductors reduce both R and C.
Inclusion of cascaded drivers and repeaters in longinterconnects.
Optical fibers, Lasers are used as longer interconnects dueto its advantage of high speed.
The values of R and C are very less for optical fibers whencompared to Metal (Al).
Integration of GaAs with optical fibers is more compatiblethan integration of Silicon with optical fibers