challenges in modeling layout systematic effects in...
TRANSCRIPT
-
Challenges in Modeling
Layout Systematic Effects
in Compact Device Models
Andrzej J. Strojwas
PDF Solutions, Inc., San Jose, CA
Carnegie Mellon University, Pittsburgh, PA
MOS-AK/GSA Workshop
Seville, September 17, 2010
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2
Outline
Motivation
Variability sources and trends
Analog/RF Modeling Challenges
SOC Modeling Challenges
pdBRIX for the 28/20nm technology node
Conclusions
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3
Technology scaling enablers
Strain and Substrate engineering remain major performance boosters
after HK MG introduction (32 nm IBM Alliance and Intel)
Process complexity continues to increase despite (or along with) the benefits
from HK-MG
Considered to continue towards next nodePerformance booster Impact on NMOS Impact on PMOS
Dual Stress Liner
(Gate First)
Mobility improvement from Tensile
liner
Mobility improvement from
Compressive liner
eSiGe N/A Mobility improvement from Compressive stress
Contact-induced strain Bar contacts with recessed NMOS Active
N/A
Gate induced strain
(Metal Gate Last)
N/A Additional Strain allowed by
Replacement Gate
SMT - Stress Memorization
(Gate First)
Mobility improvement due to
Strained Poly induced stress
N/A
S/D emb SiC Mobility improvement from longitudinal Tensile stress
N/A
Substrate orientation (100) Beneficial across wide range of stress level
(110) better for hole mobility,
gain deteriorate with stress level
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4
Outline
Motivation
Variability sources and trends
Analog/RF Modeling Challenges
SOC Modeling Challenges
pdBRIX for the 28/20nm technology node
Conclusions
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5
Variation Trends: Total Variation
Identical structure data presented here (no layout
variability impact included)
Total variation is increasing with scaling
At 32 nm node, narrow transistors have 3s variability >
45%, diminishing the benefits of scaling
NMOS Idrive Variability
0
2
4
6
8
10
12
14
45nm:
Narrow
65 nm:
Narrow
90 nm:
Narrow
45 nm:
wide
65 nm:
Wide
90 nm:
Wide
Technology
s/ m
(%
)
PMOS Idrive Variabilty
0
2
4
6
8
10
12
45nm:
Narrow
65 nm:
Narrow
90 nm:
Narrow
45 nm:
wide
65 nm:
Wide
90 nm:
Wide
Technology
Sig
ma/M
ean
(%
)
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6
Random Variability
Random variations play an
important role
Line edge roughness (LER)
Random dopant fluctuations
(RDF)
Metal gate/High-K saves us
for one generation only:
32nm/28nm
RDF impact can be
minimized by choosing
different transistor
architectures (FinFET, Ultra
Thin Body or Fully Depleted
SOI)
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7
Transistor Layout Effects
Poly corner rounding
Dummy location
Poly end cap
Active corner
Active width
Transistor location
Active-well spacing
Well-well spacing
Active extension
Contact count
Contact position
Active-active spacing
Stress layer boundaries
32/28nm logic has 2000+ unique transistors to characterize & model
45, 000+ DOE levels required to characterize transistor models
Assuming 8 replicas and Kelvin/leakage arrays more than 400k transistors
needed in a test chip for full characterization
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Layout Effects in Nanometer Technologies
Systematic variation
()Root causes
Impact at the 45/32nm
technology node
Gate poly orientation Poly lithography N/A
Gate poly pitches Poly OPC and lithography
Stress Layers
Loading effects from Etch and
film deposition
3-5% - printability
15% - poly pitch related stress
5% - contact space related stress
Poly corner rounding Poly OPC and lithography 15%
Transistor location in
multi-gate transistor
Poly patterning and stress
impacted by local neighborhood
differences
15%
Active corner rounding OPC and lithography, stress 7%
Un-modeled narrow
width effects
Stress effects, poly step height
Gate to active edge STI stress, e-SiGe stress 10-20% for PMOS with e-SiGe
Well proximity Implant scattering
Nwell-Pwell separation Gate counterdoping and
misalignment
Contact density and
placement
Silicide sheet resistance and
stress layers
Printability and stress effects increase systematic layout variation
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9
Outline
Motivation
Variability sources and trends
Analog/RF Modeling Challenges
SOC Modeling Challenges
pdBRIX for the 28/20nm technology node
Conclusions
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10
Transistor Care-abouts vs Applications
DigitalBaseband Analog RF (< 5GHz)
Logic SRAM
IDSAT Critical
IOFF Critical Somewhat critical
(SNR degradation)
Not critical
VTSAT Critical
Igate Critical Impacts Ids matching, SNR
Cgg (Covl+Cgb) Critical
Cj Critical
Gm at low Ids Not critical Critical
Gds Not critical Critical
Mismatch For Clock
trees etc
Show
stopper
Critical
Linearity (IP3) Not Critical Somewhat critical Critical
fT, fmax Not critical Critical
Noise (1/f, NFmin) Not critical Critical (SNR
degradation)
Critical
Rsub Low Rsub for latchup High for Q
Analog/RF designs have different/additional care-abouts from digital logic
& SRAM technology drivers
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Consequence of Transistor Scaling for Analog/RF
Care-about 45/40nm 32 nm MG/HiK 32nm Poly/SiON
Intrinsic gain (gm/gds)
(Lmin, Vgs=Vds=Vdd/2)
~10 Similar or better due to gm h
and (potentially) gds i
Similar to or better
than 40nm due to gm
Gate Leakage ~0.75 nA/um2 25-1000X lower Same or higher than
45 nm
Mismatch nMOS Avt ~ 3.0
mV/um
Significantly better than 40
nm & Poly/SiON
Avt same as 40 nm,
min area matching
worse
Linearity Degraded, but potentially
less compared to Poly/SiON
Degraded due to
scaling
1/f noise ~1e-11 V2.um2/hz Same as 45/40 Potentially degraded
due to nitridation
fT/fmax ~370/410 GHz Higher than 45/40 Higher than 45/40
Layout dependence Severe Similar to Poly/SiON Similar to 40nm HP
NF Similar to Poly/SiON Improved by scaling
Thermal Stability Potentiality worse Same as 40nm
Reliability (NBTI/HCI) > 10 years Same as Poly/SiON (>10 yrs)
PBTI could be an issue
Potentially degraded
due to nitridation
Process cost/other risks Std CMOS cost Double patterning
Higher than Poly/SiON
Double patterning
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Transistor Scaling Impact Summary
The 32/28 nm technology node has distinct technology choices, each with its advantages and risks
In additional they share some common risks, like increased layout sensitivity
All the consequences of these choices on Analog/RF design are unclear
The trade-off is more clear for digital logic design and SRAM
Poly/SiON
Next generation of a proven technology; better understood trade-off in terms of performance and cost
In general devices will have worse electrostatics compared to MG/HiK, with its attendant impact on Analog/RF design (linearity, matching, leakage)
Reliability degradation as a consequence of Tox scaling
Metal Gate/Hi-K
Benefits of devices with much better electrostatics (matching, linearity, leakage)
Improved reliability due to larger Tox(physical) a Lower E-field
However, new phenomena like Thermal stability, Resistor TC
Process cost
Accurate and comprehensive characterization will be essential for effective utilization of either of the technology choices for Analog/RF design
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13
Analog/RF Design in 40nm and 32nm Technology Nodes
40nm Process the best analog/RF process since 130 nm [Klaas Bult -Broadcom Analog/RF CTO at 2009 ESSDERC Panel Discussion]
All analog devices use minimum L (same as digital)
Large area (equivalent width) devices used to average RDF effects
Full dummification: very few layout patterns
Mismatches modeled precisely based on Si characterization results
Small number of patterns to characterize
Very aggressive shrink achieved
No area penalty due to dummification
32/28nm processes with MGHK:
Improved transistor matching
Intel uses only 2 L values in their SOCs: one for digital and one of analog transistors [Mark Bohr - Intel at 2009 ESSDERC Panel Discussion]
Full dummification to eliminate layout systematics
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14
Outline
Motivation
Variability sources and trends
Analog/RF Modeling Challenges
SOC Modeling Challenges
pdBRIX for the 28/20nm technology node
Conclusions
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15
Layout Dependency Increasingly Important
Performance dependence on layout increasing
Model accuracy decreasing
Idoff vs Ion, split by wafer
150 200 250 300 350
Ion (uA/um)
1E-12
1E-11
1E-10
1E-09
1E-08
Id
off
(A
/um
)
S 345 13
S 345 14
S 3 Sim_SS
S 3 Sim_TT
S 3 Sim_FF
wafer
1 / 1
Slow model
Typical model
Fast model
45/40nm PMOS Measurement
vs. SPICE
Single L, multiple W
Idsat/W
45/40nm PMOS Measurement Layout
Dependency
Measured % Idr Change due to Layout Effects
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
printa
bility
str
ess
cente
r/edge
gate
s
corn
er
roundin
g
exte
nsio
n
variation
(PM
OS
)
corn
er
roundin
g
Poly Active
% I
dr
ch
an
ge f
rom
no
min
al
65nm
45nm
Ioff/W
Key is to evaluate wide range of layout
dependencies relevant to product
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16
Process advancements have made device behavior highly sensitive to the drawn geometry
Modern day modeling methodology fails to accurately model entire design space
Restricting the design space with regular fabrics can provide more accurate models
Device Modeling of Layout Interactions
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Device Modeling of Layout Interactions
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18
Device Modeling of Layout Interactions
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19
Variability: Is this a problem designers should be addressing?
Designers historical perspective:
My world starts with SPICE models and Design Rules. It is up to the Foundry to get the SPICE models correct and the support the entire valid DR space"
Current reality: silicon
Even typical gridded SOC designs can have >10,000 different transistor patterns
Complexity of interaction effects makes it hopeless for foundries to cure this problem
Physics wont change or improve as node matures certain patterns will always have higher variability
Lets restore designers freedom at advanced nodes
Selecting right set of low variability patterns
Validating SPICE models in silicon for those patterns
Ensuring manufacturability of metal patterns used in design
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20
Improved predictabilityrequires limiting the number ofunique patterns
New patterns are created
from cell abutments
Without wavelength scaling the optical interaction remains constant
More cells fall within the same optical region of influence
Need for Limiting Number of Patterns
Problem
pattern
1mm
Pattern
influence
range for
193nm
lithography
45nm
NAND
1mm
32nm
NAND45nm
NAND
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21
Outline
Motivation
Variability sources and trends
Analog/RF Modeling Challenges
SOC Modeling Challenges
pdBRIX for the 28/20nm technology node
Conclusions
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22
Templates: Limited number of single-stage
logic topologies (including all primitives:
INV, NAND, etc.)
We select approximately 70 of them that are
most useful across wide application range
given transistor stack height constraints
Choosing limited set of layout constructs
to implement templates provides pattern
predictability
Well chosen layout constructs can facilitate
exhaustive qualification of all possible
patterns including neighborhoods
All logic cells and functions can be
constructed as combinations of the qualified
template layout set
pdBRIX Logic Templates
Reduce variability through pdBRIX design
Exhaustively characterize all patterns used
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23
Selected based on:
Litho printability
SRAM compatibility
Yield optimization
Product needs such as redundancy
FABRICS:
2-D grid environment defining allowed poly
and metal shapes
pdBRIX Library Creation Infrastructure
Co-optimized with fabrics and library:
Functions selected for optimal library coverage
Layouts co-optimized with fabrics for best area, power, and performance
Minimize number of patterns created
TEMPLATES:
Small set of single stage logic functions
built on Fabrics
Silicon predictability achieved by:
Merging, embedding, and abutting silicon qualified templates
pdBRIX ensures zero new silicon layout patterns are created
Tighter (simplified) SPICE models
STANDARD CELL LIBRARIES:
Complete standard cell library assembled from
templates
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Controlling layout patterns enables exhaustive qualification of the layout space over the relevant
interaction range
Fewer Patterns Better Predictability
pdBRIX solution space
Pattern regularity
Construction by templates
1
10
100
1000
10000
100000
1000000
0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 4
Pa
tte
rn C
ou
nt
Interaction Range (# of pitches)
30 gridded cell lib
Non-gridded cell lib trajectory
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25
32/28nm Bulk Fabric Fabricated
Fabric chosen to accommodate manufacturing objectives and template
requirements for design
Fabric characteristics
Fully gridded transistors
Limited diffusion jogs
Relaxed metal pitches
Limited two-way metal patterns
100% active contact redundancy (9T+)
Portable to 28nm
Qualifying layout constructs
8T, 10T and 13T silicon qualified
9T, 11T, 12T and 14T+ available
via virtual qualificationX = !( E(A+B)(C+D) + F )
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26
500
550
600
650
700
750
800
850
Wrong-Way Poly Various Line-Ends pdBRIX Line-Ends
Io
n/u
m
Fabric Optimization: Parametric Variability Control
Limited set of regular
design can eliminate
over half of NMOS
Idsat variability due to
poly effects
More predictive
transistor
performance in std.
cell & IP layout
NMOS RVT Idsat Variability Inner-Quartile Plot
Id
sa
t (M
ed
ian
)
Wrong-way
neighborhood &
RDR allowed
line-ends
RDR
allowed
line-ends
pdBRIX
patterns
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28LP NMOS Idsat Layout Dependency
0%
5%
10%
15%
20%
25%
30%
1 4 7 10 13 16 19 22 25 28 31 34 37 40 43 46 49 52 55 58 61 64 67
Idsat
(uA
/um
) ab
so
lute
% c
han
ge
pdBRIX Patterns
Active edge
& neighborhood
Contact
count,
location
Active
corner
effects
Poly
corner &
line-end
Contact
count,
location
Active edge
& neighborhood
Poly
corner
Poly
line-end
Sample of DR-valid Patterns
NMOS Impact of Device Layout Neighborhoods
Transistor layout and layout neighborhood can significantly impact
transistor performance
~35% reduction in Idsat variability due to layout & neighborhood for
pdBRIX NMOS transistors
pdBRIX limits total number of transistor logic patterns
Can avoid high variability patterns
Enables more accurate Si-to-SPICE matching of limited layout patterns
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28
28LP NMOS Idsat Layout Dependency
BRIX Patterns
Sample of DR-valid Patterns
Idsat
(uA
/um
) ab
so
lute
% c
han
ge
PMOS Impact of Device Layout Neighborhoods
Active edge
& neighborhoodPoly/active
contact
Active corner
effects
Active edge
& neighborhoodActive
contact
Active corner
effects
Poly
line-end
~30% reduction in Idsat variability due to layout & neighborhood for pdBRIX PMOS transistors
pdBRIX transistors can be qualified & modeled over all patterns. Cannot insure performance over all DR-compliant patterns in an SoC
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29
2010 Symposia on VLSI Technology and Circuits29
Enabling Design With Low Variability
0
0.25
0.5
0.75
1
0 5 10 15 20 25
CDF of |DIdr| vs. Reference
25%
50%
75%
100%
15%25%
5%
|DIdr|
Templates-based
DR-based
Significantly tighter transistor
performance distribution possible from
limiting transistor neighborhoods
Source PDF Solutions
po
pu
lati
on
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30
Achieves 22/20nm Pattern Control
103
Block Area (um)
Cou
nt
104
105
106
102 104 105 106103
Pattern Count vs. Block Area
22/20nm node, 2 pitch interaction range
Template based
library
RDR based
library
SMO
alg.
limit
Templates provide
pattern constraint
beneficial for
source-mask
optimization
algorithms
Source PDF Solutions
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31
Outline
Motivation
Variability sources and trends
Analog/RF Modeling Challenges
SOC Modeling Challenges
pdBRIX for the 28/20nm technology node
Conclusions
-
32
pdBRIX Templates Improve Model - Hardware
Correlation
Templates: Model = Hardware helps achieve working first silicon
New simplified interface between foundry and std. cell / IP designers
Templates plus basic (process-integration driven) design rules replace increasing complex design rule manuals
Results in correct by construction IP
Enable compatibility across foundries
Templates achieve Model = Hardware from:
Comprehensive Si verification enabling foundry to focus on specific patterns
Low layout pattern count compatible with SMO / DPT
Elimination of product-specific hot spots or yield loss mechanisms
Limited transistor patterns enable complete Si-to-SPICE validation
Templates have been validated:
40nm: adopted by Toshiba
32/28nm: validated on IBM Alliance CVs
22/20nm: validated with ASML/Brion Tachyon SMO (Si verification underway)
Fabless: adopted at 20nm
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33
Conclusions
Variability crisis continues although MGHK architecture helps for one generation (32/28nm)
Si-SPICE mismatch has become a key limiter
Systematic layout effects must be eliminated
Proposed comprehensive methodology for design-process co-optimization to reduce the cost per good die
Extensively verified in silicon
Regular design methodology with limited number of patterns only viable means for advanced lithography solutions such as SMO and interference assisted lithography
Current methodology can be used to concurrently determine the optimal lithography and design solutions for application domain
Successfully Implemented in the 22/20nm technology node
Product Design
Objectives
Circuit
Design Style
Silicon
Characterization
First-Pass
Silicon Success
PatternsDPT,
MEBM, IL
Templates
Litho Choices
Layout
Design Style