ele704/ee8502 analog cmos integrated circuits mos device layout techniques

ELE704/EE8502 Analog CMOS Integrated Circuits

MOS Device Layout Techniques

Fei Yuan, PhD. PEng.Department of Electrical & Computer Engineering

Ryerson UniversityToronto, Ontario, Canada

Copyright (c) Fei Yuan 2010

Copyright (c) F. Yuan 2010 (1)

Preface

This tutorial covers the fundamentals of CMOS device layout techniques, including process designrules, MOS devices (resistors, capacitors, and transistors) and the layout of MOS devices. Materialsof this tutorial are drawn from various published texts, lecture notes, and research papers. Please

report any error to Prof. F. Yuan at @ee.ryerson.ca.


Table of Contents

• Process Design Rules

• Layout of Resistors

• Layout of Capacitors

• Layout of MOS Transistors

• References


Process Design Rules

• Minimum Width Rules

• Minimum Space Rules

• Minimum Extension Rules

• Overlap Rules


Minimum Width Rules

⊲ The minimum width of polygon defines the limits of a fabricationprocess.

⊲ A violation of the minimum width rules potentially results in anopen circuit in the offending layer.

An open circuit may be created during fabrication.

A narrow path may be created during fabrication - large currents

passing through a narrow path cause the path to act like a fuse.

Figure 1: Design rule - min. width


Minimum Space Rules

Figure 2: Design rule - min. space

⊲ To avoid an unwanted short circuit between two polygons during

fabrication, S1 > Smin, where Smin is set by process.


Minimum Extension Rules

Figure 3: Design rule - min. extension

⊲ Some geometries must extend beyond the edge of others by a

minimum value.

⊲ Typical example - gate poly must have a minimum extension beyondthe active area to ensure proper transistor action at the edge.


Overlap Rules

⊲ Apply to polygons on different layers.

⊲ Misalignment between polygons may result in either unwanted open

or short circuit connections.

Figure 4: Design rule - overlap


Layout of Resistors

• Poly Resistors

⊲ Silicided poly resistors

⊲ Non-silicided poly resistors

• Diffusion Resistors

• Layout of Resistors

⊲ Layout of Standard Resistors

⊲ Layout of Shielded Resistors

⊲ Layout of Matched Resistors

⊲ Layout of Large Resistors


Silicided Poly Resistors

SiO2

p−substrate

SiO2

Silicide

Metal contacts

Silicidated polySilicide

Metal−1 L

W

Solicidated poly

H

Figure 5: Silicided poly resistor

⊲ Poly in standard digital CMOS processes is silicided to reduce sheetresistance. Typical sheet resistance : from 1 − 2Ω per unitarea.(Typical 0.18µ CMOS processes : R2≈8Ω/2 with error ±30%).

⊲ R = R2(L/W ) + 2Rc, where Rc=contact resistance.

⊲ Error : ±100 − 200 % (Typical 0.18µ CMOS processes : ±30%). If

silicided poly resistors are used, care should be taken for theparasitic resistance of metal wires and contacts (Typical 0.18µCMOS processes : 0.07Ω/2 for Metal layers. 8Ω/contact, and

2.5Ω/Via).


Non-Silicided Poly Resistors

SiO2

p−substrate

SiO2

Silicide

Metal contacts

Non−silicidated polySilicide

Metal−1

Non−silicidated poly

L

W

H

Figure 6: Non-silicided poly resistor

⊲ R = R2(L/W ), where R2=sheet resistance. Sheet resistance : from

50Ω to few hundred ohms per unit area . Error : ±20 %. (Typical0.18µ CMOS processes: R2≈3410Ω/2 with error ±15%).

⊲ Small parasitic capacitances to substrate.

⊲ Superior linearity.

⊲ High cost due to the extra mask needed to block silicide layer.


Diffusion Resistors

• n-well Resistors

SiO2

p−substrate

Silicide

Metal contacts

n+ n+

n−well

n−well

n+−diffusion

W

L

Figure 7: Structure of n-well resistors

⊲ Sheet resistance : ≈1kΩ per unit area (500Ω/2 with error ±30% fortypical 0.18 µ CMOS processes).

⊲ Large error : ≈±40% (≈±30 % for typical 0.18 µ CMOS processes).

Used only if absolute value is not critical.

⊲ Large parasitic capacitance between n-well and substrate.

⊲ Resistance is strongly voltage-dependent and highly nonlinear.


Diffusion Resistors (cont’d)

• Parasitic Capacitances

SiO2

p−substrate

n+ n+n−well

Depletionregions

junction cap.

Figure 8: Capacitance of n-well resistors

⊲ A large parasitic capacitance to the substrate - nonlinearvoltage-dependent junction capacitor

CJ =CJo

√

1 + VR

φ

(1)

where VR= reverse biasing voltage of the junction, φ=built-inpotential of the junction, CJo=junction capacitance at zero reverse

biasing voltage.

⊲ n-well resistors are quite noisy since (i) all disturbances/noise from

substrate can be coupled directly onto the resistors and (ii) when atime-varying current flows through a n-well resistor, it interacts

with the substrate via the parasitic junction capacitance betweenthe n-well and the substrate.



• Voltage Dependence

p−substrate

n+ n+

V = V

A B

DDV < VA B B

terminal voltagesCross−section area varies with

Narrow depletionregions

Wide depletionregion

Figure 9: Voltage-dependence of the resistance of n-well resistors

⊲ Depletion width varies with terminal voltages.

xn =

√

√

√

√

√

2ǫ

q

VR + φ

ND(1 + ND

NA

xp =√

2ǫq

VR+φ

NA(1+NAND

(2)

⊲ The cross-section area varies with terminal voltages - resistance isterminal voltage-dependent.



• Width Dependence

Depletion region

Weff

Wd

Wd

W1

A B

Depletion region

Weff

Wd

Wd

W2

A B

width (um)1 50

800

600

R

Figure 10: Width-dependence of the resistance of n-well resistors

⊲ To reduce the voltage dependence of resistance, the width of theresistors should not be made too small.

⊲ Normalized resistance error :

Reff,1

R1=

1

1 − 2Wd

W1

Reff,2

R2=

1

1 − 2Wd

W2

(3)

Since W1 > W2,Reff,1

R1

> Reff,2

R2

.


⊲ Wide resistors are less affected by terminal voltages −→ lowernonlinearity.

⊲ Typical 0.18µ 1P6M+silicide 1.8V CMOS processes require

W > 2.0µm.


Layout of Resistors

• Standard Resistors

45

45

Metal−1

R R

Recommended resistor layout1. Resistance at the corners cannot extimated accurately2. Current flow at the corner is not uniform

Figure 11: Standard layout of resistors

⊲ Avoid 90 degree angle. 45 degree is recommended.


Layout of Resistors (cont’d)

• Shielded Resistors

Shielding resistors

RR

S

S

S

VSS

Figure 12: Layout of shielded resistors (S = shielding resistors)

⊲ Shielding resistors are connected to a constant voltage source toprevent self-coupling of the resistor R/inter-coupling with others.

⊲ Widely used in analog/RF design.

⊲ Caution - a mutual capacitance between the resistor and its shieldexist.



• Matched Resistors - Inter-Digitized Layout

Dummy

resistorDummy resistor

R1 R2

R1 R2

Figure 13: Layout of matched resistors

⊲ Inter-digitized layout minimizes the effect of process variation in

x-direction.

⊲ Dummy resistors are added to ensure both resistors have theexactly same environment - the same approach is also often used for

matching capacitors.



• Matched Resistors with Temperature Consideration

PowerdevicesR1 R2

R1 R2

R2 experienceshigh temperature

Temperature effects on R1 and R2are identical (ideally)

Temperature gradient

Figure 14: Layout of matched resistors with temperature consideration


Layout of Resistors

• Standard Resistors (cont’d)

Figure 15: Standard layout of resistors



• Large Resistors

R R

p+ diffusion

p−substrate

p+ p+

n+

n−welln+−diffusion

metal−1

Figure 16: Layout of large resistors

⊲ Use n-well resistors for resistors of a large resistance because n-well

resistors have a large sheet resistance).

⊲ n-well resistors have strong interaction with substrate −→ affectneighboring devices.


⊲ Large n-well resistors are usually enclosed by a substrate shieldingring, also known as guard ring, to isolate the resistors from

neighboring devices.



• Large Resistors (cont’d)

Figure 17: Layout of large resistors


Layout of Capacitors

• Key Parameters

⊲ Linearity

⊲ Parasitic capacitance to substrate

⊲ Series resistance - resistance of capacitor plates

⊲ Capacitance per unit area

• Types of IC Capacitors

⊲ Poly-diffusion capacitors

⊲ MOS capacitors

⊲ Poly-poly capacitors - not available in standard CMOS processes

⊲ Metal-poly capacitors - capacitance is small, area consuming.

⊲ Metal-metal capacitors - capacitance is small, area consuming.


Poly-Diffusion Capacitors

n+SiO2

p−substrateDepletion

Bottom−plate capacitance

Inter−plate capacitance Poly

Silicide

Figure 18: Poly-diffusion capacitor

⊲ Most commonly used, particularly in digitally-oriented CMOS

processes.

⊲ Good linearity, C = Co(1 + a1v + a2v2) with a1 = 0.0005/v,

a2 = 0.00005/v2, typically.

⊲ Good accuracy (≈±5%).

⊲ Nonlinear bottom-plate capacitance.

⊲ Bottom-plate parasitic capacitance ≈20% of inter-plate capacitance.


MOS Capacitors

Vc

C

Vt0

n+ n+

− +Vc

n+ n+

Inversion layer

p−substeate

− +Vc

Channel resistance Ron

Gate series resistance

Ron/2 Ron/2

Lumped model of MOS capacitor (neglect series resistance)

Cch

Ron /4

Stable capacitance in strong inversion

Distributed model of MOS capacitor (neglect series resistance)

Figure 19: MOS capacitor

⊲ MOS transistors are biased in strong inversion to have a stable

capacitance.

⊲ Channel resistance: Ron = 1gon

≈1

µnC′

ox(WL

)(VGS−VT )2

.


⊲ Channel capacitance :

Cch = C ′

ox(WL) (4)

.

⊲ Intrinsic time constant of MOS capacitors when the lumped model

is used

τ =

(

Ron

4

)

Cch =L2

n

4µn(VGS − VT )(5)

⊲ Intrinsic time constant of MOS capacitors when the distributed

model is used

τ =1

3

[

L2n

4µn(VGS − VT )

]

(6)

⊲ Reducing Ln increases τ −→ Minimum channel length should be

used.

⊲ Non-negligible channel resistance (Ron) lowers the quality factor (Q)of the capacitor

Q =Power stored

Power dissipated=

1/ωC

Ron


Layout of MOS Capacitors

• Minimize Gate Series Resistance & Channel

Resistance - Multi-Finger Structure

C C C C C

n+ diffusion

Lmin

Metal−1

Poly gateGate series resistance

Metal−1

C C C C C

Poly gate

Lmin

Metal−1

(a) Single finger structure

− Large source/substrate & drain/substrate capacitances− Large gate series resistance

(b) Multi−finger structure

Figure 20: Layout of MOS capacitor

⊲ Multi-finger structure minimizes gate series resistance.

⊲ Multi-finger structure minimizes source/substrate &drain/substrate parasitic capacitances.


Layout of Capacitors (cont’d)

• Matched Capacitors - Minimize the Effect of Oxide

Thickness Gradient - Common Centroid Structure.

C1

C2

C1

C2

C2

C2

C2

C2

C2

C2

C1

C1

C1

C1

C1

C1

C1

C2

Figure 21: Layout of matched capacitor

⊲ Common centroid structure minimizes the effect of oxide thicknessvariation in both x and y-directions.

⊲ Dummy capacitors are needed to ensure the same environment forC1 and C2.



• Large Capacitors

C1

C2

C2

C1

n−welln+

dummy cap.

dummy cap.

n−well biasing

Poly−2

Poly−1

Figure 22: Layout of large matched capacitor

⊲ C1 and C2 are 2-poly capacitors.

⊲ n-well is employed as a charge collector to shield the interaction

between the bottom plate and substrate.

⊲ n-well is biased at multiple points and connected to a constantvoltage source.



• Matched Capacitors (cont’d)

Figure 23: Layout of matched capacitor



• Undercut Effect

top plate

bottom plate

b

a

x

x

C 4C

Perimeter reduction not the same

Same perimeter reduction

Figure 24: Undercut effect

⊲ Top plate is smaller than the bottom plate despite their identicaldrawn dimensions.

⊲ Bottom plate area : A = abTop plate area : A′

≈A − 2(a + b)x = A − px, where p=drawn

perimeter.

⊲ Because x is fixed for a given technology, to get the same area

reduction, the same perimeter reduction is required −→ usemultiple unit caps connected in parallel.


Layout of MOS Transistors

• Criteria for MOS Transistor Layout

⊲ Minimize gate series resistance.

⊲ Minimize source/drain resistances.

⊲ Minimize source/substrate & drain/substrate parasitic

capacitances.


Layout of MOS Transistors (cont’d)

• Layout of MOS Transistors

D

S

G

D

G

Sn+−diffusion

Poly

Series resistance of drain

Series resistance of source

Figure 25: Layout of MOS Transistors

⊲ Large gate series resistance (7.8±2.5Ω/2 for typical 0.18µ CMOS

processes).

⊲ Large distributed resistance of source/drain (6.8±2.5Ω/2 for n+and 7.2±2.5Ω/2 for p+ in typical 0.18µ CMOS processes.

⊲ Large source/substrate and drain/substrate parasitic capacitances.

⊲ Non-uniform gate/source/drain voltages. Non-uniform current flow−→ M1 carries the most current and Mn carries the least current).



• Minimize Source/Drain Resistances −→ Multiple

Contacts

G

S

D

Metal−1

Poly

Use as many contacts as possible

Figure 26: Layout of MOS Transistors (multiple contacts at source/drain)

⊲ Better contact at source/drain −→ high reliability & smaller

contact resistance (R = Rc/N , where N=number of contacts).

⊲ Smaller source/drain resistances (series resistance is negligible butlateral resistance still exists).

⊲ Large source/substrate and drain/substrate parasitic capacitances.

⊲ Large gate series resistance.

Gate is too long.

Contacts are not allowed on the gate above the channel (hightemperature required to form contacts may destroy the thin gate

oxide).



• Minimize Source/Substrate and Drain/Substrate

Parasitic Capacitances −→ Multi-Finger Structure

n+ diffusion

M1

M2

M3

M4

Shared source

Shared drain

D

S

G

Poly gate

Figure 27: Layout of MOS Transistors (multi-finger structure

⊲ Better contact −→ high reliability/smaller contact resistance.

⊲ Reduced source/drain resistances.

⊲ Reduced source/substrate and drain/substrate parasiticcapacitances (shared sources/drains).

⊲ Reduced gate series resistance (multiple gates connected in parallel).

⊲ Reduced silicon area.



• Matched MOS Transistors

M1 M2

D(M1)

D S D S D S D S D S

n+ diffusion

G(M2)

G(M1)

D(M2)

M2

M2

M1

M2

M1

M1

M1

M2

M2

M1

Figure 28: Layout of matched MOS Transistors

⊲ Matched transistors are used extensively in both analog and digital

CMOS circuits.

⊲ Use inter-digitized layout style.



• Matched MOS Transistors (cont’d)

Figure 29: Layout of matched MOS Transistors


References

⊲ A. Hastings, The Art of Analog Layout, 2nd Ed. Prentice-Hall,2006.

⊲ B. Razavi, Design of Analog CMOS Integrated Circuits,McGraw-Hill, 2001.

⊲ D. Clein, CMOS IC Layout - Concepts, Methodologies, and Tools,

Boston, 1999.

⊲ J. Franca and Y. Tsividis, editors, Design of Analog-Digital VLSI

Circuits For Telecommunications and Signal Processing, 2nd Ed.,

Prentice-Hall, 1994.

⊲ M. Ismail and T. Fiez editors, Analog VLSI - Signal and

Information Processing, McGraw-Hill, 1994.


ele704/ee8502 analog cmos integrated circuits mos device layout techniques

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