chapter+7+-+sequential+systems (1)

7/25/2019 Chapter+7+-+Sequential+Systems (1)

1/33

INTRO. TO COMP. ENG.

CHAPTER VII-1

SEQUENTIAL SYSTEMS

R.M. Dansereau; v.1.0

CHAPTER VII

CHAPTER VII

SEQUENTIAL SYSTEMS - LATCHES & REGISTERS

Reading Material: Ch. 7 of Wakerly Latches and Registers in eBook


2/33


CHAPTER VII-2

SEQUENTIAL SYSTEMS

SEQUENTIAL SYST.INTRODUCTION

SEQUENTIAL SYSTEMS-INTRODUCTION

Logistics: Exam 2 on next Tuesday (March 10) Will cover the following chapters from the ebook:

Number Systems -- SM, DRC, RC, Arithmetic addition, subtraction,

Building Blocks combinational circuits, and Latches and Registers -- sequential circuits

Homework #5 is posted and due Sunday(3/8) at 11:55 pm


Taxonomy of Computing Structures/Designhierarchy

Assembly Language

Instruction Set

Memory Datapath Controller

Storage Functional Units State Machines

uil!ing loc"s

#ates

S$itches an! %ire


3/33


CHAPTER VII-2

SEQUENTIAL SYSTEMS

SEQUENTIAL SYST.INTRODUCTION


Sofar...So far we have dealt only

with combinational logic

where the output is formed

from the current input.

Sequential systems

Sequential systems extend the idea of combinational logic by including a

system state, or in other wordsmemory, to our system.

This allows our system to perform operations that build on past

operations in asequentialmanner (i.e.one after another).

Timing diagrams will be needed to analyze the operation of many

sequential systems.

Input


tCombinational

Logic

Outpu


4/33


CHAPTER VII-3

SEQUENTIAL SYSTEMS

SEQUENTIAL SYST.MEALY & MOORE MACHINES


Mealy machine

Sequential system where

output depends on current

input and state.

Moore machine

Sequential system where

output depends only on

current state.

InputCombinational

Logic

OutputSequential System

InputCombinational

Logic

Memory(state)

Output

Sequential System


Memory

(state)

Latchesandflip-flopsare the basic building blocks of most sequential

circuits.


5/33


CHAPTER VII-4

SEQUENTIAL SYSTEMS

STORING BITSSTORING A BIT

SEQUENTIAL SYSTEMS-INTRODUCTION-MEALY & MOORE

Since there are propagation delays in real components, this time delay can

be used to store information.

For instance, the following buffer has a propagation delay of tpd.

A F

tpd

Timin

gDiagram

A

FR.M. Dansereau; v.1.0


6/33


CHAPTER VII-5

SEQUENTIAL SYSTEMS

STORING BITSEEDBAC! LOO"S

SEQUENTIAL SYSTEMSSTORING BITS-STORING A BIT

If we wish to store data for an indefinite period of time, then a feedback

loop can be used to maintain the bit.

tpdtpd

0 0 1 1

1tpd2

1tpd2

Can replace buffer with two inverters!

R.M. Danserea

u; v.1.0


7/33


CHAPTER VII-5

SEQUENTIAL SYSTEMS

STORING BITSEEDBAC! LOO"S

SEQUENTIAL SYSTEMSSTORING BITS-STORING A BIT

If we wish to store data for an indefinite period of time, then a feedback

loop can be used to maintain the bit using two inverters

How do we get the bit we want to store into the feedback loop?


Analoganalysis ofcircuit


8/33


CHAPTER VII-9

SEQUENTIAL SYSTEMS

LATCHESSR LATCH #NOR GATES$

LATCHES-CONSTRUCTING A LATCH-SR LATCH -NAND GATES-MIXED LOGIC EQUIV.

The SR latch also uses feedback to store a bit.

Recall:A

BNOR0 0 10 1 01 0 0

1 1 0

R (reset)

S (set)

Q

Q


SRQ Q

1 0 1 0001 0 (after S = 1, R =

0)0 1 0 1

000 1 (after S = 0, R =

1)1 1 0 0(invalid)

S R Q Q

0 0 Q Q

0 1 0 11 0 1 0

1 1 0 0


9/33


CHAPTER VII-9

SEQUENTIAL SYSTEMS

LATCHESSR LATCH #W/ ENABLE$

LATCHES-CONSTRUCTING A LATCH-SR LATCH -NAND GATES-MIXED LOGIC EQUIV.

The SR latch also uses feedback to store a bit.

R (reset)

S (set)

Q

Q


CLKS R Q Q

0 X X QQ

1 1 0 1 0

1 0 0 1 0 (after S = 1, R = 0)

1 0 1 0 1

1 0 0 0 1 (after S = 0, R = 1)1 1 1 0 0 (invalid)

CLK

Recall:A BNAND0 0 1

0 1 01 0 01 1 0

CLKS R Q Q Action

0 X X QQ No Change/Hold

1 0 0 QQ No Change/Hold

1 0 1 0 1 Reset1 1 0 1 0 Set

1 1 1 0 0 (invalid)


10/33


CHAPTER VII-8

SEQUENTIAL SYSTEMS

LATCHES

SRLATCH #NAND GATES$

NAND gates can also be used to create a latch, this time anSRlatch.

LATCHES-D LATCH (WITH TG)-NAND PRIMITIVES-CONSTRUCTING A LATCH

Notice that this latch is level-sensitive.

S(set)

R (reset)

Q

Q


Recall:

A BNAND0 0 10 1 11 0 11 1 0

S R Q Q1 0 0 1

110 1(after S = 1, R =

0)0 1 1 0

111 0(after S = 0, R =

1)0 0 1 1(invalid)


11/33


CHAPTER VII-10

SEQUENTIAL SYSTEMS

LATCHESSR LATCH %ITH CONTROL

LATCHES-SR LATCH -NAND GATES-MIXED LOGIC EQUIV.-SR LATCH -NOR GATES

A control line can be added to theSRlatch as follows forming an SR latch

R

This control line makes it possible to decide when the inputsSandR

are allowed to change the state of the latch.


Q

CLK

Q

S

R

S


12/33

LATCHESINTRO. TO COMP. ENG.CHAPTER VII-11

SEQUENTIAL SYSTEMS D LATCH #%ITH SRLATCH$

A D latch can be implemented using what is effectively the SR latch with a

control line as follows.

LATCHES-MIXED LOGIC EQUIV.-SR LATCH -NOR GATES-SR LATCH W/ CONTROL

Note that as long asCLK1, that the latch will change according to

the value ofD.

Q

CLK

Q

S

R

D



13/33


CHAPTER VII-12

SEQUENTIAL SYSTEMS

LATCHESTIMING DIAGRAMS

LATCHES-SR LATCH -NOR GATES-SR LATCH W/ CONTROL-D LATCH

Timing diagrams allow you to see how a sequential system changes with

time using different inputs.

For instance, a timing diagram for aD latchmight look like thefollowing.

CLK

D

Q

Q

Time



14/33


CHAPTER VII-6

SEQUENTIAL SYSTEMS

STORING BITSLOADING A BIT

SEQUENTIAL SYSTEMSSTORING BITS-STORING A BIT-FEEDBACK LOOPS

To store a bit, we need a way of loading an input bit into the structure and

making/breaking the connection in the feedback look.

One way of breaking connections is to use transmission gates.

Q

Agets temporarily stored in the inverters whenS1 1andS2

0. Then settingS1

0andS2

1,Agets

held in the feedback loop.R.M. Dansereau; v.1.0

QA TG

TGS1

S2Note: The latch is level-sensitive.

IfAchanges whileS1= 1, then

Qwill change as well.


15/33


CHAPTER VII-7

SEQUENTIAL SYSTEMS

LATCHESD LATCH #%ITH TG$

STORING BITS-STORING A BIT-FEEDBACK LOOPS-LOADING A BIT

The previous example is a data latch (D latch) if bothS1andS2are

controlled by a single lineCas follows.

Q

The control lineCmight be derived from theclock signal, or a signal

from thecontroller/sequencerin the microprocessor.


QD TG

TG

C

(Enable)

Note: The latch is level-sensitive.

IfDchanges whileC = 1,thenQwill change as well.


16/33


CHAPTER VII-13

SEQUENTIAL SYSTEMS

LATCHESTRANS"ARENCY #1$

LATCHES-SR LATCH W/ CONTROL-D LATCH-TIMING DIAGRAMS

Latches like the D latch are termedtransparentorlevel-sensitive.

This is because, when enabled, theoutput follows the input.

Enable

Q

Q

Note:Transparen

t

Transparent Latch

IN OUT

Enable



17/33


CHAPTER VII-14

SEQUENTIAL SYSTEMS

LATCHESTRANS"ARENCY #'$

LATCHES-D LATCH-TIMING DIAGRAMS-TRANSPARENCY

The following behaviour is observed for Enable = 0 and Enable = 1.

IN OUT

1

IN OUT

0

Storedbit

Transparent Latch

IN OUT

Enable WhenEnable = 1,latch acts like wire.

WhenEnable = 0,input disconnected andstored bit outputed.



18/33


CHAPTER VII-15

SEQUENTIAL SYSTEMS

LATCH EXAMPLE"ROBLEMS %( TRANS"ARENCY

LATCHES-D LATCH-TIMING DIAGRAMS-TRANSPARENCY

A problem with latches is that they are level-sensitive.

A momentary change of input changes the value passed out of the latch.

This is a problem if the input of a latch depends on the output of the same

latch.

Example:Design a system that flips a stored bit wheneverEnablegoes

high. An inexperienced engineer might design the following.

Transparent Latch

How will this design behave?

Will the bit flip once when theEnablesignal goes high?

Answer:The output willfollow the input, which

happens to keep

changing.

Enable



19/33


CHAPTER VII-16

SEQUENTIAL SYSTEMS

LATCH EXAMPLE"ROBLEMS %( TRANS"ARENCY

LATCHESLATCH EXAMPLE-PROB W/TRANSPARENCY

Lets analyze the timing behaviour of this poor design.

Enable

A

B

BA

Notice that instead of the desired

bit flip whenEnable=1, that the

input oscillates. This is

because the output depends

directly on the input sinceAand

Bappear to be connected by a

wire.

Enable



20/33


CHAPTER VII-17

SEQUENTIAL SYSTEMS

LATCH EXAMPLEELIMINATING TRANS"ARENCY

LATCHESLATCH EXAMPLE-PROB W/TRANSPARENCY

The problem with transparent, level-sensitive latches can be fixed by

splitting the input and output so that they are independent.

New solution: Consider the following improved design that flips a

stored bit wheneverEnablegoes high.This design now uses a master

and a slave transparent latches to separate the input from the output.

Transparent Latch

Transparent Latch

Enable EnableMaster Slave



21/33


CHAPTER VII-18

SEQUENTIAL SYSTEMS

LATCH EXAMPLETIMING DIAGRAM

LATCHESLATCH EXAMPLE-PROB W/TRANSPARENCY-ELIMIN. TRANSPARENCY

Lets analyze the timing behaviour of this improved design.

Transparent Latch

Transparent Latch

AB C

Enable

Enable

A

B

C

EnableEnable



22/33


CHAPTER VII-19

SEQUENTIAL SYSTEMS

LATCH EXAMPLELATCH BEHA)IOUR

LATCH EXAMPLE-PROB W/TRANSPARENCY-ELIMIN. TRANSPARENCY-TIMING DIAGRAM

A B C01

A B C10

The behaviour of the master and the slave transparent latches can be

thought of as follows.Enable = 1

bit


Enable = 0

bit


23/33


CHAPTER VII-20

SEQUENTIAL SYSTEMS

FLIP-FLOPSSINGLE BIT STORAGE

LATCH EXAMPLE-ELIMIN. TRANSPARENCY-TIMING DIAGRAM-LATCH BEHAVIOUR

A flip-flop is a single bit storage unit with two stages (master/slave):

First stage, or master, to accept input (flip)

Second stage, or slave, to give output as received by the first stage(flop)

A number of different types of flip-flops exist such as the SR, SR, D,

and JK flip-flops. You may wish to review Chapter 4 regarding these

types.

Transparent Latch

IN OUT IN OUT

Enable EnableEnable

Transparent Latch



24/33


CHAPTER VII-21

SEQUENTIAL SYSTEMS

FLIP-FLOPSEDGE TRIGGERED

LATCH EXAMPLEFLIP-FLOPS-SINGLE BIT STORAGE

A common and useful type of flip-flop are edge triggered flip-flops.

Positive edge triggered flip-flops

Negative edge triggered flip-flops

Transparent Latch

IN OUT

EnableEnable

Transparent Latch

OUT

Enable Enable

Transparent Latch

INTransparent Latch



25/33


CHAPTER VII-22

SEQUENTIAL SYSTEMS

FLIP-FLOPSNEGATI)E EDGE TRIGGERED

LATCH EXAMPLEFLIP-FLOPS-SINGLE BIT STORAGE-EDGE TRIGGERED

The output C, which is also the bit stored, appears to change on the

negative edge of the Enable transitions.

Transparent Latch

Transparent Latch

A B CEnableEnable

IN OUT

Enable

Enable

A

B

C



26/33


CHAPTER VII-23

SEQUENTIAL SYSTEMS

FLIP-FLOPS"OSITI)E EDGE TRIGGERED

FLIP-FLOPS-SINGLE BIT STORAGE-EDGE TRIGGERED-NEG. EDGE TRIGGERED

The output C, which is also the bit stored, appears to change on the

positive edge of the Enable transitions.

Transparent Latch

A B C

Transparent Latch

Enable

Enable

IN OUT

Enable

Enable

A

B

C



27/33


CHAPTER VII-24

SEQUENTIAL SYSTEMS

FLIP-FLOPSNON*IDEAL %( DUAL*"HASE

FLIP-FLOPS-EDGE TRIGGERED-NEG. EDGE TRIGGERED-POS. EDGE TRIGGERED

The previous timing diagrams are in an ideal case. In reality, an

implementation with delays might have the following timing diagram.

C

Notice thatEnable/Enableare replaced with1/2, which arenon-

overlappingphases (normally generated from a dual-phase clock).

1

2

AB

Propagationdelays shiftthe outputs andskew transitions



28/33


CHAPTER VII-25

SEQUENTIAL SYSTEMS

FLIP-FLOPSDUAL*"HASE ENABLE

FLIP-FLOPS-NEG. EDGE TRIGGERED-POS. EDGE TRIGGERED-NON-IDEAL W/DUAL-

Why use non-overlapping, dual-phase signals for the latch enable?

What happens if the latch enable input flip simultaneously?

How about if propagation delays cause one latch to change enable

state slightly before the other?

The goal is to ensure that themaster latch has latchedthe input

before the slavelatch tries takes this bit from the master.

If the master has not latched, the slave sees the input transparently!!!

A non-overlapping, dual-phase enable solves this problem.

Transparent Latch

Transparent Latch

1 2

IN OUT IN OUT

1 2


1-bit

flip-flop


29/33


CHAPTER VII-26

SEQUENTIAL SYSTEMS

REGISTERSREGISTERS ROM LI"*LO"S

FLIP-FLOPS-POS. EDGE TRIGGERED-NON-IDEAL W/DUAL--DUAL-PHASE ENABLE


Assembly Language

Instruction Set

Memory Datapath Controller

Storage FunctionalUnits

StateMachines

uil!ing loc"s#ates

S$itches an! %ire


30/33


CHAPTER VII-26

SEQUENTIAL SYSTEMS

REGISTERSREGISTERS ROM LI"*LO"S

FLIP-FLOPS-POS. EDGE TRIGGERED-NON-IDEAL W/DUAL--DUAL-PHASE ENABLE

In essence, a flip-flop is a 1-

bit register.

An n-bit register can be

formed by grouping n flip-

flops together.

1-bitflip-flop

121-bit

flip-flop

12

1-bitflip-flop

12

A0

A1

An+1

12


D0

D1

Dn+1


31/33


CHAPTER VII-27

SEQUENTIAL SYSTEMS

REGISTERSREAD(%RITE CONTROL #1$

FLIP-FLOPSREGISTERS-REGISTERS F/FLIP-FLOPS

When a clock is used, such as the non-overlapping, dual-phase clock1

and2, we want control over when a new value is written into a register

(instead of writing a new value every clock cycle).

A read/write control is therefore required.

One poor design might be as follows for a 1-bit register.

What is the problem with this design?

Transparent Latch

Transparent Latch

1 2

OUTIN

Read/Write



32/33


CHAPTER VII-28

SEQUENTIAL SYSTEMS

REGISTERSREAD(%RITE CONTROL #'$

FLIP-FLOPSREGISTERS-REGISTERS F/FLIP-FLOPS-READ/WRITE CONTROL

A better design might be as follows

Read/Write

When Read/Write =0, the output is feed back into the master latch.

When Read/Write =1, the input is feed into the master latch.

Transparent Latch

Transparent Latch

1 2

IN

OUT



33/33


CHAPTER VII-29

SEQUENTIAL SYSTEMS

REGISTERSREAD(%RITE CONTROL #,$

FLIP-FLOPSREGISTERS-REGISTERS F/FLIP-FLOPS-READ/WRITE CONTROL

A different design approach might be as follows

Read/Write

What problems might exist with this design?

One issue might be that both latch enables are0when R/W

=0.

Transparent Latch

Transparent Latch

1 2

IN OUT

R M Dansereau; v 1 0

chapter+7+-+sequential+systems (1)

Documents