unit 12- sequential logic systems 2

Digital Electronic Systems Unit 12

SEQUENTIAL LOGIC SYSTEMS 2

Development of the Flip-FlopFlip-flops are bistable synchronous devices. This means that the output has two stable states and can only change state at a specified point on a triggering input called the Clock (C). This point is usually the transition of the clock signal from low to high (or high to low). The output can only change in synchronisation with the clock.

Consider again a gated S-R latch. The output of the latch can only change when the enable input EN is high. Now, replace this asynchronous enable signal by a synchronous clock signal C. If this clock signal is processed to produce a series of pulses that are narrow compared with the clock period, the gated S-R latch will act as an edge-triggered S-R flip-flop. The output will only change state during these pulses.

Therefore, an asynchronous gated S-R latch, converts readily to an edge-triggered S-R flip-flop. This conversion is shown below.

The moment C goes from 0 to 1, a pulse is generated (EN=1) and the state of S and R cause a change firstly in gates #3 and #4 and then in gates #1 and #2. At all other times, EN = 0 and the flip-flop holds its current state regardless of the states of S and R. This can be seen from the timing diagram shown below.

1


On the rising edge of each clock pulse the output Q will change depending on the control inputs S and R. Since the rising or positive transition of the clock results in triggering of the flip-flop, the flip-flop is said to be positive edge-triggered. If the clock signal was inverted before applying to the pulse transition detector circuit (pulse narrowing circuit), the flip-flop would be negative edge-triggered.

The summary symbol for an S-R flip-flop is as follows. The triangle on the clock input indicates that the flip-flop changes state only on the edge of a clock pulse.

2


A method of edge triggering - Pulse Transition Detector Circuit (Pulse narrowing circuit)

There is a small delay through the inverter on one input to the NAND gate. This implies that the inverted clock pulse arrives at the NAND gate a few nanoseconds after the non-inverted clock pulse. This produces an output spike with a time duration of a few nanoseconds (the gate delay of an inverter).

D Type Flip-FlopA D type or Data flip-flop is in effect a 1-bit memory. The D Type flip-flop is constructed by connecting the S input and the R input of an S-R flip-flop via an inverter, as shown below.

The summary symbol for this (positive edge-triggered) D-type flip-flop is given below.

3


The summary symbol for a negative edge-triggered D type flip-flop is as follows.

The truth table for a D flip-flop is given below. Note that there are only two states possible, D=0 (S=0 and R=1) or D=1 (S=1 and R=0).

D CLK S R Comments

0 0 1 0 1 Reset (stores a 0)

1 1 0 1 0 Set (stores a 1)

An example of a timing diagram for a positive edge triggered D flip-flop is given below.

4


PRESET and CLEAR in Sequential Logic

For the flip-flops discussed, the S-R and D inputs are called synchronous inputs because the data on these inputs is transferred to the flip-flop’s output only on the triggering edge of the clock pulse. The data is transferred synchronously with the clock.

Most integrated circuit flip-flops also have two asynchronous inputs. These inputs affect the state of the flip-flop independent of the clock. They can be used to determine initial condition of the Q output. They are normally labeled PRESET (PRE) and CLEAR (CLR). An active level on the preset input will set the flip-flop, and active level on the clear will reset the flip-flop. In the example of the positive edge triggered flip-flop below, the preset and clear are active-LOW. For synchronous operation, both preset and clear

must be kept high.

It is good design practice to use these asynchronous inputs only for initialisation of the system to a know state.

5


J-K Type Flip-FlopIn S-R flip-flops the condition S=R=1 results in what is known as the “race condition”. This problem is overcome by the use of the J-K flip-flop, which does not allow the race condition to occur.

The J-K flip-flop is widely used. It has the advantage that it has no invalid state (unlike the S-R flip-flop). An S-R flip-flop can be converted to a J-K flip-flop by adding two AND gates as follows.

The resulting truth table is as follows

J K C Q Comments

0 0 Q0 The output remains unchanged after a clock pulse. NO CHANGE

0 1 0 1 The output goes to 0 after a clock pulse. RESET

1 0 1 0 The output goes to 1 after a clock pulse. SET

1 1 Q0 The output changes state after a clock pulse. TOGGLE

The summary symbol for a J-K flip-flop is as follows

6


J-K flip-flop with asynchronous Preset and Clear inputs

The following is the logic diagram for a J-K flip-flop with asynchronous preset and clear . Preset and clear will override the effect of the synchronous inputs, J, K and the clock.

The summary symbol for this circuit is as follows.

7


Toggle Flip-FlopA T (or Toggle) flip-flop is constructed by connecting the J-input and the K-input of a J-K flip-flop together.

The truth-table reduces to

J K C Q Comments

0 0 Q0 The output remains unchanged after a clock pulse. (no change)

1 1 Q0 The output changes state after a clock pulse. (toggle)

Ex 1: What is the output Q if the T input is set to 1 ? Assume that Q is preset to 1. Fill in Q and on the timing diagram. Comment on the result.

8


Master-Slave flip-flopsMaster-slave flip-flops are a class of flip-flop, which has largely been replaced by the edge-triggered devices. However, they may still be encountered in some existing equipment.

As an example, consider the master-slave D flip-flop. It consists of two D-latches connected together as follows.

With this arrangement, the transfer of data from the input to the output of the flip-flop occurs on the rising edge of the clock pulse. This means that the flip-flop is positive edge triggered.

When C=0 the master latch is transparent and the output follows D. As soon as the clock changes from 0 to 1, the master latch is disabled and stabilises (it cannot change). Output

of the slave latch is transparent and follows the value of . Therefore the value of is the same as the value of D on the rising edge of the clock. The summary symbol for the above circuit is the same as before.

9


Summary of the difference between a latch and a flip-flopA latch is level sensitive. It continuously samples the input while the enable signal is high (or low). On the other hand, a flip-flop is edge sensitive. It samples the input only at the low-to-high (or high-to-low) transition of the clock.

Flip-flop applicationsFlip-flops are commonly used to store several bits of data from parallel lines. D type flip-flops are commonly used for such an application. The clock inputs of each of the flip-flops are connected together, so that the same clock pulse triggers every flip-flop.

Flip-flops are used to divide the frequency of a periodic clock waveform. J-K (or T) flip-flops are used in this application.

Another important application of flip-flops is digital counters. Negative edge-triggered J-K flip-flops are used in this application.

10

unit 12- sequential logic systems 2

Documents