unit 11- sequential logic systems 1

Digital Electronic Systems Unit 11

SEQUENTIAL LOGIC SYSTEMS 1

Introduction

Up to now, we have considered only combinational logic circuits. Combinational logic circuits are digital circuits where the output is totally dependent on the values of the present inputs and does not depend on the sequence with which the inputs are applied, nor on any past input values. We now consider sequential logic circuits. Sequential logic circuits are digital circuits whose output depends on past as well as present input values. That is, the output depends on memorising previous input combinations as well as the present input combination. Sequential circuits can be categorised as clocked (synchronous) and unclocked (asynchronous).

This unit provides a brief introduction to some basic sequential circuits and proceeds to describe the latch in more detail.

Multivibrators

The most common electronic circuit for storing a single binary digit, or bit, is a Flip-Flop. The Flip-Flop belongs to a family of sequential logic circuits known as multivibrators. There are three types of multivibrators:

1. The bistable

2. The mononstable

3. The astable

1. There are two categories of bistable devices, the Latch and the Flip-Flop. Bistable devices have two stable states called SET and RESET and can remain in either state indefinitely, making them useful as storage devices. The basic difference between a Latch and a Flip-Flop is the way in which they are changed from one state to the other. The Flip-Flop is the basic building block for registers, counters and memories.

2. The monostable multivibrator, commonly called a one-shot, has only one stable state. It produces a single controlled-width pulse in response to a triggering input. It is generally used as a timing device and is used in the triggering circuit of an oscilloscope.

3. The astable multivibrator has two unstable states and switches constantly, or oscillates, from one state to the other. In digital electronics it is used to generate clock pulses.

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The S-R (Set-Reset) Latch

The fundamental building block of asynchronous sequential systems is the S-R Latch. A latch is a bistable multivibrator, that is, it has two stable states. A latch reacts to changes of input logic levels as they occur. (A Flip-Flop only reacts to inputs after it is enabled by a clock pulse).

There are two possible implementations of an S-R Latch:

Active LOW LatchThe Active LOW implementation involves cross connecting two NAND gates.

Active HIGH S-R LatchThe Active HIGH implementation involves cross-connecting two NOR gates.

Active LOW Latch

Active-Low Input Latch

The output from one gate is fed back into the input of the other gate. This produces regenerative feedback. This means that the next state of the output is dependent on the present state.

Let Q0 represent the present output state and let Q represent the next output state. Let represent the inverse of the present output state and let represent the inverse of the next output state.

Now consider the set of four input conditions.

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Case 1:

Then and . Therefore the outputs remain unchanged.

Case 2:

The output of the lower NAND is . This output is fed back as an input to the upper NAND gate . Therefore the latch is RESET.

Case 3:

The output of the upper NAND is . This output is fed back as an input to the lower NAND gate . Therefore the latch is SET.

Case 4:

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A low on either input to a 2-input NAND gate forces the output of that NAND gate to a logic HIGH. Therefore, for the cross-coupled NAND gates, both outputs will go HIGH. (

and ). The output is invalid because the complementary operation of the outputs is violated.

Furthermore, if change from the 00 condition to the 11 condition simultaneously, the next state of the latch cannot be reliably predicted. As there is some small difference in the propagation delay of the gates, one of the gates will dominate in it’s transition to the LOW input state. This will force the output of the slower gate to remain high.

The operation of the Active Low Latch may be summarised with a simple truth table.

S R Q Comments0 0 1 1 NC NC No Change, Latch remains in current state0 1 1 0 0 1 Latch RESET1 0 0 1 1 0 Latch SET1 1 0 0 1 1 INVALID condition

Active High S-R Latch

A similar analysis can be performed on this circuit to produce the following truth table.

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S R Q Comments0 0 NC NC No Change, Latch remains in current state0 1 0 1 Latch RESET1 0 1 0 Latch SET1 1 0 0 INVALID condition

The only difference between this active high S-R latch and active low latch is for the invalid condition – the value of Q and is high for the former and low for the latter.

Consider now a sequence of actions carried out on an Active High S-R Latch.

ACTION Q0 S R Q CONCLUSIONAssume 0 0 0 0 1 This is a stable stateApply 1 to S 0 1 0 1 0 Unstable; Q changesQ0 becomes 1 1 1 0 1 0 This is a stable stateRemove 1 from S 1 0 0 1 0 Stable state after SETApply 1 to S 1 1 0 1 0 No change in QRemove 1 from S 1 0 0 1 0 Stable state after SETApply 1 to R 1 0 1 0 1 Unstable; Q changesQ0 becomes 0 0 0 1 0 1 This is a stable stateRemove 1 from R 0 0 0 0 1 Stable state after RESETApply 1 to S and R 0 1 1 0 0 Unacceptable because = Q

These actions can be summarised in the following state diagram.

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An example of a timing diagram for an S-R latch is given below.

Summary symbols for an S-R latch are as follows. The latch on the left has active high inputs and the latch on the right has active low inputs.

Gated S-R Latch

This latch is identical to an S-R latch except that the latch has an extra enable input. The control inputs (S and R) are only allowed to change the state of the latch when the enable input is asserted. Shown below are two implementations of a Gated S-R Latch.

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Shown below are the truth table and an example of a timing diagram for the Gated S-R Latch.

En S R Q Comments0 X X NC NC No Enable, this implies no response from the Latch1 0 0 NC NC No Change, Latch remains in current state1 0 1 0 1 Latch RESET1 1 0 1 0 Latch SET1 1 1 1 1 INVALID CONDITION

Note that for the invalid condition, if built using the AND-NOR configuration.

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As can be seen from the timing diagram when the Gated S-R Latch is enabled, it acts identically to the ungated Latch. The point of interest in this timing diagram is the stage at which the Enable is Low and the S control input goes HIGH and there is no response from the output Q. Then when the Enable goes HIGH the output Q is able to respond to the current control input status. Like before, the Gated S-R Latch has a summarised symbol, which is shown below.

Gated D latch

The gated D latch is the same as the gated S-R latch except that the set and reset inputs are combined into one data input, D.

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Shown below are the truth table and an example of a timing diagram for a gated D latch.

En D Q Comments0 X NC NC No Enable, this implies no response from the Latch.

The output remains in the current state 1 0 0 1 Latch RESET1 1 1 0 Latch SET

The gated D latch has a summary symbol, which is shown below.

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unit 11- sequential logic systems 1

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