chap 3.3~3.5 construction an arithmetic logic unit (alu) jen-chang liu, spring 2006

Chap 3.3~3.5Construction an Arithmetic Logic Unit (ALU)

Jen-Chang Liu, Spring 2006

What is “Computer Organization”?

I/O systemProcessor

Compiler

Operating

System(Windows, etc)

Application (programs)

Digital Design

Circuit Design

Instruction Set Architecture

Datapath & Control

transistors

MemoryHardware

Software Assembler

Highlevel

Lowlevel

Arithmetic Logic Unit (ALU)MIPS CPU

CPU

Registers

$0

$31

Arithmeticunit

Multiplydivide

Lo Hi

Coprocessor 1 (FPU)

Registers

$0

$31

Arithmeticunit

Registers

BadVAddr

Coprocessor 0 (traps and memory)

Status

Cause

EPC

Memory

Floating point

Outline in old textbook Ch. 4.4: Simple ALU: logical op.s, add, subCarry lookahead adder Ch. 4.5: Multiplication Ch. 4.6: Division

ALU (Arithmetic Logic Unit) The brawn of the computer Functions

Arithmetic: add, sub Logical: AND, OR, NOT…

MIPS uses 32-bit word, we need a 32-bit-wide ALU 1-bit ALU 32-bit ALU 1-bit ALU

input1 bit

output1 bit

control signal

input1 bit

Basic hardware building blocks

c = a . bba

000

010

001

111

b

ac

b

ac

a c

c = a + bba

000

110

101

111

10

01

c = aa

a0

b1

cd

0

1

a

c

b

d

1. AND gate (c = a . b)

2. OR gate (c = a + b)

3. Inverter (c = a)

4. Multiplexor (if d = = 0, c = a; else c = b)

(MUX)

Truth table:

AND

1-bit logical unit for AND, OR

b

0

1

Result

Operation

a

•1-bit control signal to choose operation from MUX

1-bit ALU

1-bit Addition Binary addition

Input/output for full adder

1

0

(0) 1

1

1

(1) 0

(0)

1

1

(1) 1

(1)

0

0

(0) 1

(1)

0

0

(0) 0

(0)

0

0

(0) 0

(0) (Carries)

97108/Patterson Fig 4.03

Sum

CarryIn

CarryOut

a

b

1-bit ALU: Addition (cont.) Input/output truth table

3 inputs 2 outputs

1-bit ALU: Addition (cont.) Truth table -> logical equation

Logical equation -> logical gates

CarryOut = (b•CarryIn)+(a•CarryIn)+(a•b)+(a•b•CarryIn)

AND OR

b

CarryOut

a

CarryIn

t

b

0

2

Result

Operation

a

1

CarryIn

CarryOut

1-bit ALU: AND, OR, ADD

Data lineControl line

How do theylook like ininstructions?

32-bit ALU =

32 1-bit ALU

Result31a31

b31

Result0

CarryIn

a0

b0

Result1a1

b1

Result2a2

b2

Operation

ALU0

CarryIn

CarryOut

ALU1

CarryIn

CarryOut

ALU2

CarryIn

CarryOut

ALU31

CarryIn

(ripple carry adder)

ALU: What about Sub ( 減 ) ? For 2’s complement

1-bit ALU for sub

a-b = a+(-b) = a+b+1

complement: invert each bit of b

0

2

Result

Operation

a

1

CarryIn

CarryOut

0

1

Binvert

b

32-bit ALU with Sub

Result31a31

b31

Result0

CarryIn

a0

b0

Result1a1

b1

Result2a2

b2

Operation

ALU0

CarryIn

CarryOut

ALU1

CarryIn

CarryOut

ALU2

CarryIn

CarryOut

ALU31

CarryIn

(ripple carry adder)

Let this CarryInbe 1 when sub

Binvert

What about other instructions?

Now,we have the following operations in ALU and, or add, sub

Other MIPS instructions: slt: set on less than beq, bne: branch on equality

Implement slt Recall

slt $t0,$s0,$s1 $t0 = 1 if $s0<$s1

Since $t0 is a 32-bit register0 0 0… …0 0 0 ?

1 if $s0 < $s10 otherwise

Always 031 0bit

1. Check $s0<$s1 ? => $s0 - $s12. Set output to 0 or 1

12

How to compare using ALU?

Compare a and b

a < b => (a-b) < 0 negative

(a-b) sign bit of (a-b)

a >= b => (a-b) >= 0 non-negative

Set the result to 1when sign bit is 1

1

0

slt : 1th modification For the 1-bit ALU

0

3

Result

Operation

a

1

CarryIn

CarryOut

0

1

Binvert

b 2

Less

0

3

Result

Operation

a

1

CarryIn

0

1

Binvert

b 2

Less

Set

Overflowdetection

Overflow

a.

b.

We add a input signal for output

slt: 2nd modification

0

3

Result

Operation

a

1

CarryIn

CarryOut

0

1

Binvert

b 2

Less

0

3

Result

Operation

a

1

CarryIn

0

1

Binvert

b 2

Less

Set

Overflowdetection

Overflow

a.

b.

31-th 1-bit ALU(sign bit)

Sign bit !!!

(2 bits)(1 bit)

+

Seta31

0

ALU0 Result0

CarryIn

a0

Result1a1

0

Result2a2

0

Operation

b31

b0

b1

b2

Result31

Overflow

Binvert

CarryIn

Less

CarryIn

CarryOut

ALU1Less

CarryIn

CarryOut

ALU2Less

CarryIn

CarryOut

ALU31Less

CarryIn

Modification:1. Less input2. Set bit

Implement beq, bne Check for equality of two registers

a=b => (a-b) = 0 Logical implementation: OR all output

bits after sub

Zero = (Result31+Result30+…+Result1+Result0)

所有 bit 為 0, 設 Zero=1

Seta31

0

Result0a0

Result1a1

0

Result2a2

0

Operation

b31

b0

b1

b2

Result31

Overflow

Bnegate

Zero

ALU0Less

CarryIn

CarryOut

ALU1Less

CarryIn

CarryOut

ALU2Less

CarryIn

CarryOut

ALU31Less

CarryIn

Modification:1. Zero output2. Merge 1st CarryIn an

d BitInvert (Bnegate) 兩者只有在減法時為 1

(1 bit) (2 bits)

ALU control line function0 00 and0 01 or0 10 add1 10 sub1 11 slt

Symbolic diagram for ALU

ALU ResultZero

Overflow

a

b

ALU operation

CarryOut

operation function0 00 and0 01 or0 10 add1 10 sub1 11 slt

a b

Outline Simple ALU: logical op.s, add, sub Multiplication

3 versions of multiplication hardware division

Multiplication: startup example

Multiplicand 1 0 0 0Multiplier x 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 + 1 0 0 0 Product 1 0 0 1 0 0 0

Multiplier 1 0 0 1Multiplier 1 0 0 1Multiplier 1 0 0 1Multiplier 1 0 0 1

* Multiplication is done by iterative addition

1st version of mult. hardware

64-bit ALU

Control test

MultiplierShift right

ProductWrite

MultiplicandShift left

64 bits

64 bits

32 bits

•32-bit multiplication•32-bit x 32-bit = 64-bit

LSB


1st version of mult. algorithm

Done

1. TestMultiplier0

1a. Add multiplicand to product andplace the result in Product register

2. Shift the Multiplicand register left 1 bit

3. Shift the Multiplier register right 1 bit

32nd repetition?

Start

Multiplier0 = 0Multiplier0 = 1

No: < 32 repetitions

Yes: 32 repetitions

64-bit ALU

Control test


ProductWrite

MultiplicandShift left

64 bits

64 bits

32 bits

Drawbacks of 1st version Half of the 64-bit of the multiplicand is

always 0 64-bit ALU for 32-bit multiplication


*why not shift the product right ?

0 0 0 0 0 0 0 00 0 0 0 1 0 0 0

1 0 0 0 x 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 + 1 0 0 0 0 0 0 0

1 0 0 00 1 0 0 00 0 1 0 0 00 0 0 1 0 0 01 0 0 1 0 0 0

2nd version of mult. hardware


Write

32 bits

64 bits

32 bits

Shift right

Multiplicand

32-bit ALU

Product Control test

1 0 0 0 x 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 + 1 0 0 0 0 0 0 0

1 0 0 00 1 0 0 00 0 1 0 0 00 0 0 1 0 0 01 0 0 1 0 0 0

Drawbacks of 2nd version The right 32-bit of the product is

initially 0 We take advantage that

Multiplier and product both shift right at each step

3rd version of mult. hardware

ControltestWrite

32 bits

64 bits

Shift rightProduct

Multiplicand

32-bit ALU

000…00000000 multiplier

Signed multiplication The last algorithm will work for signed

number, if Right shifting of the product must preserve

the sign !!! Example:

11100011 11110001

00011111111111111111111111111111 11000000000000000000000000000000

Hi Lo

01000000000000000000000000000000X $t2

01111111111111111111111111111111$t1

Multiplication in MIPS

mult $t1, $t2 # t1 * t2No destination register: Product could be 6

4 bits; need two special registers to hold it3-step process

00011111111111111111111111111111$t3

11000000000000000000000000000000$t4mflo $t4

mfhi $t3(move from Hi)

Arithmetic Logic Unit (ALU)MIPS CPU

CPU

Registers

$0

$31

Arithmeticunit

Multiplydivide

Lo Hi

Coprocessor 1 (FPU)

Registers

$0

$31

Arithmeticunit

Registers

BadVAddr

Coprocessor 0 (traps and memory)

Status

Cause

EPC

Memory

Floating point

Outline Simple ALU: logical op.s, add, sub Multiplication Division

3 versions of division hardware

Division: startup example

QuotientDivisor 1000 1001010 Dividend

• division => Iterative subtraction• Human judge whether subtract or not, how does machine do it ?

1

-10000010

001

01011010-1000

10 Remainder

Simplified example 4-bit division: 0111/0010

0 0 0 0 0 1 1 1 - 0 0 1 0

1 1 1 0 0 1 1 1

negative => 不減=> 還原被除數

0 0 0 0 0 1 1 1 - 0 0 1 0

1 1 1 1 0 1 1 1


0 0 0 0 0 1 1 1 - 0 0 1 0

1 1 1 1 1 1 1 1


0 0 0 0 0 1 1 1 - 0 0 1 0

0 0 0 0 0 0 1 1

positive => 可減=> 商數 1

Simplified example (cont.)

0 0 0 0 0 0 1 1 - 0 0 1 0

0 0 0 0 0 0 0 1

positive => 可減=> 商數 11

餘數

1st version of div. hardware

64-bit ALU

Controltest

QuotientShift left

RemainderWrite

DivisorShift right

64 bits

64 bits

32 bits

* Both operands are 32 bits

00….0000 Dividend

000…00

Divisor 000…00

When to subtract?

Done

Test Remainder

2a. Shift the Quotient register to the left,setting the new rightmost bit to 1

3. Shift the Divisor register right 1 bit

33rd repetition?

Start

Remainder < 0

No: < 33 repetitions

Yes: 33 repetitions

2b. Restore the original value by addingthe Divisor register to the Remainder

register and place the sum in theRemainder register. Also shift the

Quotient register to the left, setting thenew least significant bit to 0

1. Subtract the Divisor register from theRemainder register and place the result in the Remainder register

Remainder > 0–

可減不可減，還原

Drawbacks of 1st version Half of the 64-bit of the dividend is

always 0 64-bit ALU for 32-bit division

2nd version of div. hardware

Controltest

QuotientShift left

Write

32 bits

64 bits

32 bits

Shift left

Divisor

32-bit ALU

Remainder00….0000 Dividend

3rd version of div. hardware

Write

32 bits

64 bits

Shift leftShift right

Remainder

32-bit ALU

Divisor

Controltest000…000 Dividend Remainder Q Remainder Q1Q2

Example: 0111/0010

Division in MIPS

div $t1, $t2 # t1 / t2

Quotient stored in LoBonus prize: Remainder stored in Himflo $t3 #copy quotient to t3mfhi $t4 #copy remainder to t43-step process

chap 3.3~3.5 construction an arithmetic logic unit (alu) jen-chang liu, spring 2006

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