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Chapter 14: Arithmetic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 14-1
Chapter 14: Arithmetic Modules
Department of Electronic Engineering
National Taiwan University of Science and Technology
Prof. Ming-Bo Lin
Chapter 14: Arithmetic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 14-2
Syllabus
ObjectivesAddition and subtractionMultiplicationDivisionArithmetic and logic unit
Chapter 14: Arithmetic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 14-3
Objectives
After completing this chapter, you will be able to:Describe both addition and subtraction modulesUnderstand the principles of carry-look-ahead (CLA) adderUnderstand the essential ideas of parallel-prefix addersDescribe the basic operations of multiplicationDescribe the basic operations of divisionDescribe the designs of arithmetic-logic unit (ALU)
Chapter 14: Arithmetic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 14-4
Syllabus
ObjectivesAddition and subtraction
Carry-look-ahead (CLA) addersParallel-prefix adders
MultiplicationDivisionArithmetic and logic unit
Chapter 14: Arithmetic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 14-5
Bottleneck of Ripple-Carry Adder
Bottleneck of n-bit ripple-carry adderThe generation of carries
Ways of carry generation carry-look-ahead (CLA) adder parallel-prefix adders:
• Kogge-Stone adder• Brent-Kung adder
others
Chapter 14: Arithmetic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 14-6
A CLA adder
Definition carry generate (gi): gi = xi · yi
carry propagate (pi): pi = xi ⊕ yi
iii cps ⊕=
iiii cpgc ⋅+=+1
0001 cpgc +=
001011
000111112 )(gppgpg
cpgpgcpgc++=
++=+=
Chapter 14: Arithmetic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 14-7
A Carry-Lookahead Generator
Chapter 14: Arithmetic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 14-8
A CLA Adder
Chapter 14: Arithmetic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 14-9
A CLA Adder
// a 4-bit CLA adder using assign statementsmodule cla_adder_4bits(x, y, cin, sum, cout);// inputs and outputsinput [3:0] x, y;input cin;output [3:0] sum;output cout;
// internal wireswire p0,g0, p1,g1, p2,g2, p3,g3;wire c4, c3, c2, c1;
// compute the p for each stageassign p0 = x[0] ^ y[0], p1 = x[1] ^ y[1],
p2 = x[2] ^ y[2], p3 = x[3] ^ y[3];
Chapter 14: Arithmetic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 14-10
A CLA Adder
// compute the g for each stageassign g0 = x[0] & y[0], g1 = x[1] & y[1],
g2 = x[2] & y[2], g3 = x[3] & y[3];// compute the carry for each stageassign c1 = g0 | (p0 & cin),
c2 = g1 | (p1 & g0) | (p1 & p0 & cin),c3 = g2 | (p2 & g1) | (p2 & p1 & g0) | (p2 & p1 & p0 & cin),c4 = g3 | (p3 & g2) | (p3 & p2 & g1) | (p3 & p2 & p1 & g0) |
(p3 & p2 & p1 & p0 & cin);// compute Sumassign sum[0] = p0 ^ cin, sum[1] = p1 ^ c1,
sum[2] = p2 ^ c2, sum[3] = p3 ^ c3;// assign carry outputassign cout = c4;endmodule
Chapter 14: Arithmetic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 14-11
A CLA Adder --- Using generate statements
// an n-bit CLA adder using generate loopsmodule cla_adder_generate(x, y, cin, sum, cout);// inputs and outputsparameter N = 4; //define the default sizeinput [N-1:0] x, y;input cin;output [N-1:0] sum;output cout;
// internal wireswire [N-1:0] p, g;wire [N:0] c;// assign input carryassign c[0] = cin;
n 4 8 16 32
f (MHz) 104.3 78.9 53.0 32.0LUTs 8 16 32 64
Virtex 2 XC2V250 FG456 -6
Chapter 14: Arithmetic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 14-12
A CLA Adder --- Using generate statementsgenvar i;generate for (i = 0; i <N; i = i + 1) begin: pq_cla
assign p[i] = x[i] ^ y[i];assign g[i] = x[i] & y[i];
end endgenerate // compute generate and propagation
generate for (i = 1; i < N+1; i = i + 1) begin: carry_claassign c[i] = g[i-1] | (p[i-1] & c[i-1]);
end endgenerate // compute carry for each stage
generate for (i = 0; i < N; i = i + 1) begin: sum_claassign sum[i] = p[i] ^ c[i];
end endgenerate // compute sum
assign cout = c[n]; // assign final carry…
Chapter 14: Arithmetic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 14-13
Syllabus
ObjectivesAddition and subtraction
Carry-look-ahead (CLA) adderParallel-prefix adders
MultiplicationDivisionArithmetic and logic unit
Chapter 14: Arithmetic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 14-14
Parallel-Prefix AddersThe prefix sums
s[i,0] = xi xi-1 … x1 x0
where 0 ≤ i < n
From bits k to i
where 0 ≤ i < n, k ≤ j < i, 0 ≤ k < n
[ , ] [ , 1] [ , 1] [ , ]
[ , ] , 1] [ , ]
i k i j i j j k
i k i j j k
g g p gp p p
+ +
+
= + ⋅
= ⋅
iiii
iiii
yxp
yxg
⊕=
⋅=
],[
],[
Chapter 14: Arithmetic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 14-15
Parallel-Prefix Adders
The carry of ith-bit adder can be written as
Define group g[i,j] and p[i,j] as a group and denoted as w[i,j] = (g[i,j], p[i,j])
111 −−− ⋅+= iiii cpgc
[ ,0] [ , 1] [ , 1] [ ,0]i i j i j jg g p g+ += + ⋅
Chapter 14: Arithmetic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 14-16
Parallel-Prefix Adders
The operator in w[i,k] = w[i,j+1] w[j,k] is a binary associative operator.
1 1 1i i i ic g p c− − −= + ⋅
[ ,0] [ , 1] [ , 1] [ ,0]i i j i j jg g p g+ += + ⋅
Chapter 14: Arithmetic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 14-17
Kogge-Stone Adder
Chapter 14: Arithmetic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 14-18
Brent-Kung Adder
Chapter 14: Arithmetic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 14-19
Parallel-Prefix Adders
An n-input Kogge-Stone parallel-prefix networka propagation delay of log2n levelsa cost of nlog2n - n + 1 cells
An n-input Brent-Kung parallel-prefix networka propagation delay of 2log2n - 2 levels and a cost of 2n - 2 - log2n cells
Chapter 14: Arithmetic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 14-20
Syllabus
ObjectivesAddition and subtractionMultiplication
Shift-and-add multiplicationBasic array multipliersA signed array multiplier
DivisionArithmetic and logic unit
Chapter 14: Arithmetic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 14-21
Shift-and-Add Multiplication
Chapter 14: Arithmetic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 14-22
Shift-and-Add Multiplication
A sequential implementation
Chapter 14: Arithmetic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 14-23
Syllabus
ObjectivesAddition and subtractionMultiplication
Shift-and-add multiplicationBasic array multipliersA signed array multiplier
DivisionArithmetic and logic unit
Chapter 14: Arithmetic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 14-24
A Basic Array Multiplier
An iterative logic structure
( ) ( )∑∑∑∑∑−+
=
−
=
+−
=
−
=
−
=⋅=⋅⋅⋅⋅⋅=×=
1
0
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1
02222
nm
k
kk
n
j
jiji
m
i
n
j
jj
m
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ii PyxyxYXP
Chapter 14: Arithmetic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 14-25
A Basic Unsigned Array Multiplier
Chapter 14: Arithmetic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 14-26
An Unsigned CSA Array Multiplier
Chapter 14: Arithmetic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 14-27
Syllabus
ObjectivesAddition and subtractionMultiplication
Shift-and-add multiplicationBasic array multipliersA signed array multiplier
DivisionArithmetic and logic unit
Chapter 14: Arithmetic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 14-28
A Signed Array Multiplier
Let X and Y be two two’s complement number im
ii
mm xxX 22
2
0
11 ∑+−=
−
=
−−
jn
jj
nn yyY 22
2
0
11 ∑+−=
−
=
−−
∑ ∑+−+∑ ∑=
∑+−
∑+−=
=
−
=
−
=
−+−
−+−
−+−−
+−
=
−
=
−
=
−−
−
=
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2
0
2
0
11
11
211
2
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2
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2
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2
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11
2222
2222
m
i
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mjjm
nini
nmnm
jij
m
i
n
ji
n
j
jj
nn
m
i
ii
mm
yxyxyxyx
yyxx
XYP
Chapter 14: Arithmetic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 14-29
A Signed Array Multiplier
Chapter 14: Arithmetic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 14-30
A Signed Array Multiplier
Chapter 14: Arithmetic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 14-31
Syllabus
ObjectivesAddition and subtractionMultiplicationDivision
Nonrestoring division algorithmImplementations
Arithmetic and logic unit
Chapter 14: Arithmetic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 14-32
An Unsigned Non-restoring Division Algorithm
Chapter 14: Arithmetic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 14-33
An Unsigned Non-restoring Division Algorithm
Chapter 14: Arithmetic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 14-34
An Unsigned Nonrestoring Division Example
Chapter 14: Arithmetic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 14-35
Syllabus
ObjectivesAddition and subtractionMultiplicationDivision
Nonrestoring division algorithmImplementations
Arithmetic and logic unit
Chapter 14: Arithmetic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 14-36
A Sequential Unsigned Non-restoring Division
A sequential implementation
Chapter 14: Arithmetic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 14-37
An Unsigned Array Non-restoring Divider
Chapter 14: Arithmetic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 14-38
Syllabus
ObjectivesAddition and subtractionMultiplicationDivisionArithmetic and logic unit
Basic functionsImplementations
Chapter 14: Arithmetic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 14-39
Arithmetic-Logic Units
Arithmetic unitadditionsubtractionmultiplicationdivision
Logical unitANDORNOT
Chapter 14: Arithmetic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 14-40
Shift Operations
Logical shiftLogical left shiftLogical right shift
Arithmetic shiftArithmetic left shiftArithmetic right shift
Chapter 14: Arithmetic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 14-41
Syllabus
ObjectivesAddition and subtractionMultiplicationDivisionArithmetic and logic unit
Basic functionsImplementations
Chapter 14: Arithmetic Modules
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 14-42
Arithmetic-Logic Units