ca session 02
TRANSCRIPT
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Computer Architecture
Cache Memory
ARASH HABIBI LASHKARI‐
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•
• Capacity
•
Access method• er ormance
• Physical type• Physical characteristics• Organisation
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• – The natural unit of organisation
• um er o wor s –
or Bytes
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• Se uential
–
Start at the beginning and read through in order – Access time depends on location of data and previous
– e.g. tape• Direct
– Individual blocks have unique address – Access is by jumping to vicinity plus sequential search –
ccess me epen s on oca on an prev ous location – e.g. disk
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• Random
–
Individual addresses identify locations exactly – Access time is independent of location or previous
– e.g. RAM• Associative
– Data is located by a comparison with contents of a portion of the store
– access
– e.g. cache
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• – Time between presenting the address and getting
the valid data• Memory Cycle time
– Time may be required for the memory to “recover” before next access
– Cycle time is access + recovery• Transfer Rate
– Rate at which data can be moved
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•
• Volatility• Erasa e• Power consumption
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• • Not always obvious• e.g. inter eave
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•
– Capacity• ow as
–
Time is
money
• How expensive?
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•
• L1 Cache
• Main memory• s cac e• Disk• Optical• Tape
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•
only static RAM (see later)
•
This would
need
no
cache
– How can you cache cache?• This would cost a very large amount
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• • Sits between normal main memory and CPU• May e ocate on CPU c ip or mo u e
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– • • Check cache for this data• I present, get rom cac e ast•
If not present, read required block from main memory to cache
• Then deliver from cache to CPU• Cache includes tags to identify which block of
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•
• Mapping Function• Rep acement A gorit m•
Write Policy• Block Size•
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• • Cache block of 4 bytes
– .e. cac e s nes o ytes•
16MBytes main
memory
• 24 bit address – (224=16M)
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•
memory is up to date
•
I/O may
address
main
memory
directly
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• • Multiple CPUs can monitor main memory
•
Lots of
traffic
• Slows down writes
• Remember bogus write through caches!
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• • Update bit for cache slot is set when update
•
If block
is
to
be
replaced,
write
to
main
memory on y i up ate it is set
• Other caches get out of sync• I/O must access main memory through cache• . .
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• 80386 – no on chip cache• – us ng yte nes an our way set assoc at ve
organization• Pentium (all versions) – two on chip L1 caches – Data & instructions
• Pentium III – L3 cache added off chip• Pentium 4
– L1 caches• y es• 64 byte lines• four way set associative
– L2 cache
• 256k• 128 byte lines• 8 way set associative
–
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