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Bus ArchitectureMemory unit

4096x16

AR

PC

DR

AC

INPR

IR

TR

OUTR

ALUE

16-bit Bus

address

clock

S2S1S0

111

001

010

011

100

101

110

AccessSelect

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Instruction Format

I opcode address011121415

I = 0 means direct memory addressI = 1 means indirect memory address

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The Control Unit

15 14 - 12 11 - 0

Instruction Register (IR)

3x8Decoder

ControlUnit

12

I

SequenceCounter

4x16Decoder

IncrementClearMaster Clock

T15 – T0

D7 – D0 n

Other Inputs

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Decoding the InstructionStart

SC <- 0

AR <- PC

IR <- M[AR], PC <- PC + 1

Decode opcode IR(14-12)AR <- IR(11-0), I<- IR(15)

D7

I I

Execute I/OInstruction

SC <- 0

Execute RegisterInstruction

SC <- 0

AR <- M[AR] Nothing

Execute MemoryInstruction

SC <- 0

T0

T1

T2

T3T3 T3 T3

= 0, memory reference= 1, register or I/O

= 1, I/O = 0, register = 1, indirect = 0, direct

• We’ve seen how to fetch and decode instructions in RTL notation

• We now need to look at how to execute each instruction

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Input/Output Instructions

• Recall the I/O instructions posed a potential problem– Their purpose is to set up loop structures

waiting for an input/output device to become available

– This could cause large amounts of valuable time to be wasted

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Interrupts• To alleviate this problem we introduce interrupts into the

system• Two instructions enable and disable interrupts

– Sometimes we don’t want to be interrupted such as when we’re doing something important or we’re already servicing and interrupt

• ION (enable interrupts)D7IT3B7: IEN ← 1, SC ← 0

• IOF (disable interrupts)D7IT3B6: IEN ← 0, SC ← 0

• We also introduce another flip-flop, R, which tells the system when there is an interrupt to be handled

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Interrupt Cycle

• Interrupts are subroutine calls with a couple of differences– They come at arbitrary times during program

execution– The start address of the interrupt service routine

(subroutine) is a predetermined, fixed location in memory

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R

Fetch/DecodeInstruction

Store return addressM[0] <- PC

IEN

FGI

FGO

ExecuteInstruction

Branch to address 1PC <- 1

Disable interruptsIEN <- 0R <- 0

Notify re: interruptR <- 1

Interrupt Cycle

= 0

= 1

= 0= 1

= 0

= 1

= 0 = 1

Set up the interrupt service routine

Once set-up, the system carries on as usual

I/O device is ready so signal an interrupt

The interrupt service routine ends with a BUN to indirect address 0

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Interrupt Cycle

0 BUN 0x510x000x01

1 BUN 0x00

INTERRUPT SERVICEROUTINE

0x51

0x100x11

0x110 BUN 0x51

0x000x01

1 BUN 0x00

0x51 INTERRUPT SERVICEROUTINE

0x100x11

PC is here when the interrupt occurred

Interrupt cycle sets return address hereand PC here

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Interrupt Cycle Implementation

• To implement the interrupt cycle we introduce the R flip-flop\

• To utilize it we modify our fetch/decode RTL as follows

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Modified Fetch/Decode

T0: AR ← PCT1: IR ← M[AR], PC ← PC + 1T2: D0, … D7 ← Decode IR(12-14), AR ← IR(0-11), I ← IR(15)

R’T0: AR ← PCR’T1: IR ← M[AR], PC ← PC + 1R’T2: D0, … D7 ← Decode IR(12-14), AR ← IR(0-11), I ← IR(15)

• It was this…

• We modify it to this…

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Modified Fetch/Decode

• We must also add the interrupt cycle handler RTL…

RT0: AR ← 0, TR ← PCRT1: M[AR] ← TR, PC ← 0RT2: PC ← PC + 1, IEN ← 0, R ← 0, SC ← 0

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Remainder of Chapter 5

• The remainder of the chapter discusses how to convert the Control Unit RTL into logic gates

• This is really nothing more than defining AND/OR/NOT/XOR gates to handle the conditions on the RTL statements

• Thus, I’m not going to spend any time on it and won’t hold you accountable for it but…

• You should read it over once to get a feel for how all this stuff ties together

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Homework

• Problems 5-9, 5-10, 5-11, 5-12• Due next lecture

SequenceCounter CPU Registers

MemoryLocation

SC PC IR AR DR I AC 135

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5135

3160

DA002150C135

FFFF

47

48

135513651375

1505

Initial Memory Contents47

0C00

3160

A0A0

01FF

PCIR

ARDR

AC

I 1