© Fraunhofer

Stefan Dreiner

BACKSIDE ILLUMINATION TECHNOLOGY FOR CMOS IMAGERS

© Fraunhofer

Outline

Motivation

Investigation of various BSI processes

Chip-to-Wafer process

Wafer-to-Wafer process

Next steps in technology development

Conclusion

© Fraunhofer

Technology

Avalanche Photodiode (APD) operated in Geiger mode

Smart frontside illuminated pixels integrated into standard 0.35µm CMOS process

Unique Selling Points

Lowest Dark-Count-Rate

High uniformity

Picosecond time resolution

High sensitivity in blue and UV

Motivation: Status Frontside Illuminated SPADs

© Fraunhofer

Motivation : MiSPiA smart-pixel for direct TOF

Block diagram (left) and Layout (right) of the SPAD based smart pixel, showing the main components

The pitch is 150µm; the SPAD has 30µm diameter (Pixel fill factor 3.14%)

© Fraunhofer

Motivation: Status Embedded CCD

Design and Development

CMOS/CCD TDI sensor for earth observation and high resolution scanning

Unique Selling Points

Design and Development

High full-well capacity >150,000 e-

Fast TDI integration 100,000 fps

On-chip CDS and multiplexing

High QE with BSI poss ible

© DLR

© Fraunhofer

Motivation: Fraunhofer IMS infrastructure

Equipment for BSI available: CMOS, Electroplating, C2W + W2W Bonding, Grinding, Silicon Plasma Etching, Deep Trench Etching, ALD

© Fraunhofer

Investigation of various BSI processes Market study from Yole Devéloppment for 2015

The hybrid BSI method is the only feasible method for pixelwise connection which is necessary

© Fraunhofer

BSI processes:

SPAD 3D Integration Advantages

Separation of SPAD device and electronics

Higher fill factor

Optimized process flow for SPADs

-> Backside illuminated SPADs

© Fraunhofer

Chip-to-Wafer BSI process at IMS

Process flow:

SOI base wafer is used

Etch stop on buried oxide (BOx)

Chip-to-wafer bonding

SPAD chips are bonded to ROIC wafer

SLID (solid liquid interdiffusion) bonding process for wafer connection

© Fraunhofer

Chip-to-Wafer: Electrical and mechanical connection

Solid-Liquid Interdiffus ion (SLID)

Frame and bumps made of Cu/Sn on CMOS wafer

Equivalent frame and bumps on SPAD wafer

Processing between 300 and 350°C

liquid Sn diffuses into solid Cu

Forming of an intermetallic with high melting point > 500°C

SPAD

SPAD

CMOS-Chip CMOS-Chip

© Fraunhofer

Chip-to-Wafer: BSI SPAD Process Variants

Fully-Depleted (HV) BackSPADs Partially-Depleted (LV) BackSPADs (FSI-like SPAD)

Modified process flow

SPAD is the only device on wafer

Adjustable doping levels

Adjustable temperature budget

Doping Concentration

Electrical Field

High dark current generation -> Backside passivation

non depleted area

© Fraunhofer

Chip-to-Wafer: Options of BSI SPADs

[µm]

Y [

µm

]

X [µm]

X [µm]

Y [

µm

]

Modified wafer material

Thicker Si-film

Doping level

Additional buried layers (Passivation)

Target

Higher PDE for long wavelengths

Better time resolution

© Fraunhofer

Chip-to-Wafer: BSI SPAD Dark Count Rate

0 1 2 3 4 5 6 7 8 9 10 11

103

104

105

106

r = 49µm

r = 48.6µm

r = 45.6µm

r = 46.9µm

r = 48µm

Me

dia

n D

CR

SPAD Distance to Trench [µm]

No Trenches

Above 1 µm SPAD to Trench Distance

there are no major differences in the DCR

r = 49µm

Comparison with FSI(bulk)/BSI(SOI) SPAD

Fill FactorBackSPAD > 70%

DCRBSI(SOI)SPAD ≈ 40 x DCR FSI(bulk)SPAD

© Fraunhofer

Chip-to-Wafer: BSI SPADs 3D Integration Chip-to-Wafer

Chip to Wafer features:

Bond of single detector chips to wafer with electronics

Electrical and mechanical connection by soldering (SLID, Pitch 30µm realized)

Optimized SPAD process possible

High fill factor >70%

Separate yield consideration for SPAD and ROIC

Several thousand Chips produced

Other wafer material for SPADs possible (challenges CuSn bumps, etch stop, CTE)

Low volume capable (complex process)

© Fraunhofer

Wafer-to-Wafer BSI process at IMS

CMP-prepared

surfaces

Oxide-oxide-

bonding

Grinding and

etching

Box removal

ARC deposition

TSµV etch

(simplified)

TSµV and pad

metal deposition

SOI base wafer is used

wafer-to-wafer direct bonding

Etch stop on buried oxide (BOX)

ALD via metal (direct or bridging via)

Backside passivation in development

Direct via Bridging via

© Fraunhofer

Wafer-to-Wafer: Challenge Wafer bonding

Hydrophilic direct Bonding

Wafer cleaning

O2 Plasma and H20 treatment

RT wafer bonding

Annealing 250 °C

Specifications

Wafer bow < 30 µm

Surface roughness ~0.5 nm

Steps < 20nm

No particle

Wafer edge processing

SAM picture with non-bonding areas

removed SOI wafer edge

© Fraunhofer

Wafer-to-Wafer: Through Silicon µVia (TSµV)

Space for v ia in-between SPADs

Landing pad ROIC

Challenge: two level etch stop

© Fraunhofer

SPAD 3D Integration Back-SPADs 3D Integration Wafer-to-Wafer

Wafer to Wafer features

Bond of detector wafer to readout wafer

Mechanical connection using direct bond

Electrical connection via through silicon micro via (TSµV)

Optimized SPAD process possible

High fill factor >70%

Nearly factor 2 less process steps than C2W

Integration of ARC + Backside Passivation, Micro lenses possible

High volume capable bonding technology

First demonstrator in production

ROIC-Wafer

SPAD-Wafer (48x32)

© Fraunhofer

Next steps in technology development: FMD Invest

Forschungsfabrik Mikroelektronik Deutschland

engl. „Research Factory Microelectronics Germany“

Funding from German government targeting micro- and nano- electronic research

Automatic wafer bonder for higher precision bonding

F.A.S.T ALD tool for TSµV filling

Automatic electroplating tool for TSµV filling and SLID bumps

HNA (HF/Nitric/Acetic) etching Tool for silicon wet etching, doping dependent etch rate

© Fraunhofer

Next steps in technology development: Non-SOI Back-SPAD and BSI for embedded CCD

Using EPI-Wafer instead of SOI

Advantages

Reduced Dark Count Rate (SPADs)

Embedded CCD BSI possible

Wafer could be cheaper (depending on epi thickness and doping)

Issues

Etch-Stop -> doping selective etching necessary -> HNA

Backside passivation for fully depleted diodes

No chip to wafer

dZiel

© Fraunhofer

Next steps in technology development: Backside passivation

Issue

Trapping of photogenerated charge

additional dark current due to surface defects

Possible solutions

Implantation + laser annealing (external)

Delta Doping with MBE/low temperature CVD process

Low temperature Pure Boron

ARC Stack with 1nm metal (i.e PT)

High quality ALD layer

UV flooding

Back surface passivation

M. Hoenk, KISS Single Photon Counting Workshop 2010

© Fraunhofer

Summary

BSI solves fill factor issue for smart SPAD pixels and QE issue for embedded CCD

Presentation of two SOI based hybrid BSI technologies (C2W, W2W) for SPAD Sensors

Issues with dark count rate for SOI wafers -> change to bulk wafers

FMD invest enables higher process reliability and throughput as well as bulk wafers for W2W hybrid BSI technology for SPADs and embedded CCD

Backside passivation issue has to be solved especially for fully depleted devices and applications in the UV range

© Fraunhofer

Contact

Head of department CMT

Holger Kappert

Phone: +49 (203) 3783 186

Fax: +49 (203) 3783 266

Email: holger.kappert@ims.fraunhofer.de

Web: www.ims.fraunhofer.de

Head of group HSR

Dr. Stefan Dreiner

Phone: +49 (203) 3783 2993

Fax: +49 (203) 3783 266

Email: stefan.dreiner@ims.fraunhofer.de

Web: www.ims.fraunhofer.de