session 02 v.3
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» Fifth levelD i g i ta l D e s i g n u s i n g V H D L
Session TwoIntroduced by
Cairo-Egypt
Version 03 – June 2012 1
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about Start Group
2
Mahmoud AbdellatifAlaa Salah Shehata Mohamed SalahMohamed Talaat
start.courses@gmail.com www.slideshare.net/StartGroup
www.facebook.com/groups/start.group www.startgroup.weebly.com Start.courses@gmail.com
+ 02 0122-4504158 M.A www.youtube.com/StartGroup2011+ 02 0128-0090250 A.S
Session Two
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Refresh Your Memory
Session Two 3
Find the 7 errors in this code
library IEEE; Entity 5_AND_GATE is Port ( X1 : in std_logic(5 downto 0 ); X2 : in std_logic(5 downto 0 ); Y : out std_logic(5 downto 0 );
); END 5_and_gate;
Architecture Behave of AND_GATE_5 IS
Y <= X1 AND X2 ; END 5_AND_GATE;
AND_GATEX1
X2Y
5
5
5
Refresh Your Memory
Slides
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Refresh Your Memory [Solution]
Session Two 4
library IEEE;USE ieee.std_logic_1164.all; -- 1 Use Package to define
operations on std_logic data typeEntity AND_GATE is -- 2 Don’t Start with number
Port ( X1 : in std_logic_vector(4 downto 0 ); -- 3 wrong data type
X2 : in std_logic_vector(4 downto 0 ); -- 4 4 downto 0
Y : out std_logic_vector(4 downto 0 ) -- 5 No ;);
END AND_GATE;
Architecture Behave of AND_GATE IS -- 6 wrong entity nameBegin --7 Reserved wordY <= X1 AND X2 ; END behave ; -- 8 architecture name
AND_GATEX1
X2Y
5
5
5
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Outline
Session Two 5
Data Objects : Signals
VHDL Statements - Sequential Statements
- What is Process - IF Statement- CASE Statement
- Combinational Logic - Sequential Logic
Mini Project no.1 ALU
2
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Outline
Session Two 6
Data Objects : Signals
VHDL Statements - Sequential Statements
- What is Process - IF Statement- CASE Statement
- Combinational Logic - Sequential Logic
Mini Project no.1 ALU
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Signals
Session Two 7
Signals used to connect between systems or connect components inside a systemSignals represent physical wiring in hardware
Types of signals-- External Signals
-In,Out and Inout ports-Internal connections in structural Description discussed later
-- Internal Signals -Connect devices inside the block -Used for Intermediate calculations
NoteWe use Internal Signals for:
- Avoid illegal port usage situations like Read Output port- Internal Connections ‘wiring’
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Internal Signals
Session Two 8
Signal Declaration
Notewe don’t define a mode for internal signals
architecture <arch_name> of <entity_name> is -- architecture declarations signal <sig_name> : <sig_type>;
.
.begin
<Architecture body>
End <arch_name> ;
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Example 05
Session Two 9
NAND Gate
LIBRARY ieee;USE ieee.std_logic_1164.all;
ENTITY NAND_GATE IS port ( A,B : in STD_LOGIC; C : in STD_LOGIC; D : out STD_LOGIC
);END ENTITY NAND_GATE ;
ARCHITECTURE behave OF NAND_GATE IS
SIGNAL E : std_logic;
BEGIN E <= A and B ; D <= E and C ;
END behave;
AE
BD
C
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Exercise 01
Session Two 10
Write VHDL code for this logic circuit
A
B
C
G
D F
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Exercise 01 [Solution]
Session Two 11
Write the VHDL code for this logic circuit
LIBRARY ieee;USE ieee.std_logic_1164.all;
ENTITY NAND_GATE IS port ( A,B,C,D : in STD_LOGIC; G,F : out STD_LOGIC
);END ENTITY NAND_GATE ;
ARCHITECTURE behave OF NAND_GATE IS
SIGNAL SIG_1 : std_logic;SIGNAL SIG_2 : std_logic;
BEGIN SIG_1 <= A and B ; SIG_2 <= SIG_1 and C ; F <= SIG_2 and D ; G <= SIG_1 ;
END behave;
A
B
C
G
FD
SIG_1
SIG_2
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Outline
Session Two 12
Data Objects : Signals
VHDL Statements - Sequential Statements
- What is Process - IF Statement- CASE Statement
- Combinational Logic - Sequential Logic
Mini Project no.1 ALU
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Combinational Vs. Sequential logic
Session Two 13
in any digital system we can divide the circuits into two types :
Combinational logic circuits implement Boolean functions, so the output in this circuits is function only on their inputs, and are not based on previous outputs.
Sequential circuits compute their output based on input and state(previous outputs), and that the state is updated based on a clock.
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Concurrent & sequential statements
Session Two 14
VHDL has concurrent statements and sequential statements
•Concurrent statements are executed in parallel w.r.t each other.Process statement Assign statement With – select When – else
•Sequential statements are executed in sequence w.r.t each other. Sequential statements should be written inside a “process”
If statement Case statement loop statementsWait and Null statement
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Process
Session Two 15
-What is a ProcessProcess allows writing sequential statements within concurrent
environment Process is like a container that include the sequential statementsProcess declaration
Note<sensitivity_list>:
List of signals/input ports that cause the process to be executed whenever there is a change in their values
Sequential statementsprocess (sensitivity list) begin
sequential statements ; end process ;
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Process
Session Two 16
Statements inside a “process” are read sequentially and executed when the process suspends (“end process” is reached)
very important note:Process executed one time then become ready for a change on its sensitivity list.How is this statement differs from z<= x and y;
Architecture behave of comb_ct is
Begin process (x,y) begin
z <= x and y;h <= x or y; t <= x xor y; …
end process; End behave ;
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IF Statement
Session Two 17
Executes a list of sequential statements when the corresponding condition evaluates to true
V.IMPORTANT ROLEThe branches order is important as they imply a priority
Syntax
<condition> Boolean expression that evaluates to either TRUE or FALSE
If <condition> then -- list of sequential statements
elsif <condition> then -- list of sequential statementselse
-- list of sequential statementsend if;
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CASE Statement
Session Two 18
Makes several conditions on the same signalSyntax
<expression> can be a signal [or a variable (discussed later)]<choice> constants representing one of possible <expression> values.
V.IMPORTANT ROLE -“When others” is a must if not all values of <expression> are covered - Each branch of a Case statement can have any number of sequential statements
case <expression> is when <choice> =>
-- list of sequential statements when <choice> =>
-- list of sequential statements when others =>
-- list of sequential statementsend case;
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Outline
Session Two 19
Data Objects : Signals
VHDL Statements - Sequential Statements
- What is Process - IF Statement- CASE Statement
- Combinational Logic - Sequential Logic
Mini Project no.1 ALU
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Example 06
Session Two 20
Logic GateLIBRARY ieee; USE ieee.std_logic_1164.all;
ENTITY logic_gate IS port ( a, b : in std_logic; C : out std_logic; Sel : in std_logic);END ENTITY logic_gate;
ARCHITECTURE behave OF logic_gate IS BEGIN process ( a, b, Sel ) begin
if (Sel= '1') then C <= a and b; elsif (Sel = ‘0') then '
C <= a or b;else C <= ‘Z’;end if;
end process;END ARCHITECTURE behave;
Logic Gate
A
Sel
CB
Operation = 1 a and bOperation = 0 a or b
What is sensitivity list !!!
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Example 07
Session Two 21
ComparatorLIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY comparator IS port( a, b : in std_logic_vector(7 downto 0);
c : out std_logic_vector(1 downto 0); );
END ENTITY; ARCHITECTURE behave OF comparator ISBEGIN process (a, b) begin if (A = B ) then -- equality c <= "00"; elsif (A > B) then -- greater than c <= "01"; elsif (A < B) then -- greater than c <= "10"; else -- covers other cases c <= “ZZ"; end if; end process; END ARCHITECTURE;
Comparator
A CB
A=B C=“00” A>B C=“01” A<B C=“10”
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Example 08
Session Two 22
4 x 1 Multiplexer
Architecture rtl of mux_case is begin process (a,b,c,d,sel) begin Case sel is When "00" =>
f <= a; When "01" =>
f <= b; When "10" =>
f <= c; When "11" =>
f <= d; when others => -- is "when others“ a must?
f <= ‘Z’; End case; End process; End architecture;
A
Sel
FBCD
Do we need all these signals? On sensitivity list ??
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Lab 01
Session Two 23
Title:Simulation of a 2 X 4 Decoder on ModelSimSimulation of a simple 8-bits Comparator
Goal: Creating new project on ModelSim Simulation of a combinational circuit
Tutorial [1]Slides
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Lab 01
Session Two 24
2 X 4 Decoder
Architecture rtl of dec is begin process (a) begin Case a is When "00" =>
f <= “0001”; When "01" =>
f <= “0010”; When "10" =>
f <= “0100”; When "11" =>
f <= “1000”; when others =>
f <= “ZZZZ”; End case; End process; End rtl ;
a f
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Outline
Session Two 25
Data Objects : Signals
VHDL Statements - Sequential Statements
- What is Process - IF Statement- CASE Statement
- Combinational Logic - Sequential Logic
Mini Project no.1 ALU
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Sequential Circuits
Session Two 26
A digital clock signal is a square wave voltage.In complex circuits a clock with a fixed frequency is used for timing.To store and pass the data or digital signals through, some specific gates are used which are called latches or flip-flops. These are some kind of memory that store their input over their output by a specific level or edge of the clock.
Asynchronous Operation don’t wait clock
Synchronous Operationwait clock to get an input and to produce an output
Clock period
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D-Flip Flop
Session Two 27
Reset Clk Enable Q+
1 - - 0
0 No rising_edge - Q0 Rising_edge 0 Q
0 Rising_edge 1 DD_FF
D
clk
QReset
enable
Clock period
Asynchronous resetSynchronous enable
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D-Latch
Session Two 28
Reset Clk Enable Q+
1 - - 0
0 0 - Q0 1 0 Q
0 1 1 DD_Latch
D
clk
QReset
enable
Clock period
Asynchronous resetSynchronous enable
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D-Latch vs D-Flip Flop
Session Two 29
With a D-latch working on High level of clock , a signal can’t propagate through until the clock is high .
With a rising edge D-Flip-flop, the signal only propagates through on the rising edge.
Clock
D
Q
D_Latch D-Flip Flop
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Example 09
Session Two 30
Simple D-FF
Library ieee; use ieee.std_logic_1164.all;
Entity d_ff is Port( D, clk : in std_logic; Q : out std_logic );end entity;
Architecture behav of d_ff is
Begin process(clk) begin if rising_edge(clk) then Q <= D; end if; end process;
end behav;
D_FF
D
clk
Q
rising_edge() : function defined for std_logic type
Used to detect rising edge of clock
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Example 10
Session Two 31
D-FF with asynchronous reset
Library ieee; use ieee.std_logic_1164.all;
Entity d_ff is Port( d, clk, rst : in std_logic; Q : out std_logic);end entity;Architecture behav of d_ff is Begin process(clk, rst) begin If (rst = '1') then Q <= '0'; elsif rising_edge(clk) then Q <= d; end if; end process;
end behav;
D_FF
D
clk
Q
Since rst has higher priority over the clk edge
then, We put it on sensitivity list
We have now a D Flip Flop with asynchronous reset
Reset
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Example 11
Session Two 32
D-FF with asynchronous reset and clock enable
Library ieee; use ieee.std_logic_1164.all;
Entity d_ff is Port( d, clk, rst,en : in std_logic; Q : out std_logic);end entity;
Architecture behav of d_ff is Begin process(clk, rst) begin If (rst = '1') then Q <= '0'; elsif rising_edge(clk) then
If (en = '1') then Q <= d;
end if; end if; end process;end behav;
Enable has lower priority w.r.t the clk edgeSo we don’t put it in sensitivity list as it has no value and will slow the simulation
We have now a D Flip Flop with asynchronous reset and synchronous enable
Reset Clk Enable Q+
1 - - 0
0 No rising_edge - Q
0 Rising_edge 0 Q
0 Rising_edge 1 D
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Example 12
Session Two 33
D_Latch (positive level)
library ieee; use ieee.std_logic_1164.ALL;
entity d_ff is port(
clk,reset,enable: in std_logic; d: in std_logic; q: out std_logic);
end d_ff;
architecture Behavioral of d_ff is begin process(clk,reset,d) begin if reset = '1' then q<= '0'; elsif clk = '1' then q<= d; end if; end process; end Behavioral;
Latch depend on input every time it changes while clk =‘1’ so if clk still =‘1’ and input changes process should be triggered So, d on sensitivity list
Reset Clk Q+
1 - 0
0 0 Q
0 1 D
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Session Two 34
Start Notes [Synthesis Notes]
D-FF coding rules
FF is a the basic memory unit . We need a lot to register the data. Some rules should be done on flip flop to be written in the right way. You need only to keep in your mind the D-FF code, Latches are not preferred to be used to avoid glitches.
Example of illegal D-FF coding Legal in VHDL but not synthesized
this code also not synthesized
if reset = '1' then q <= '0'; Elsif rising_edge(clk)then q <= d; Elsif d = ‘1’ then q <= not d;end if;
if enable = '1' then if rising_edge(clk)then q <= d; end if; end if;
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Session Two 35
Start Notes [Synthesis Notes]
Example of illegal D-FF coding Register or latch
The Answer is
not latch as d is not in sensitivity listnot register (no clock edges detected)
Reg : Process (clk)beginif clk = '1' then q <= d; end if; End process reg;
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Session Two 36
Start Notes [Simulation Notes]
Read Errors
You Should read the error first , don’t be disturbed. Compilers always give you the position where the error is and also may help you know the reason of the error, you may also search the error on the internet .
Example of common errorsforget end if ; awhen you use else if pattern instead of elsif pattern
if reset = '1' then q<= '0'; Else if clk = '1' then q<= d; end if;
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Session Two 37
Start Notes [Simulation Notes]
Cover all Cases
To make sure that your code is working well, cover all cases that your code go inside. For example, in many cases you may see ‘X’ values that mean there is multiple drivers to a specific signal . Or ‘U’ value for unitialized signals
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Outline
Session Two 38
Data Objects : Signals
VHDL Statements - Sequential Statements
- What is Process - IF Statement- CASE Statement
- Combinational Logic - Sequential Logic
Mini Project no.1 ALU
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Mini Project
Session Two 39
- ALU Arithmetic Logic Unit
It is a circuit capable of executing both kinds of operations, arithmetic as well as logical. Its operation is described next slide as follow :
The output (arithmetic or logical) is selected by the MSB of sel The specific operation is selected by sel’s other three bits.
LogicUnit
Arithmetic Unit
A(7:0)B(7:0)
Cin
SEL(3:0)
C(7:0)
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Mini Project
Session Two 40
Sel Operation Function Unit0000 Y<= a Transfer A
Arithmetic
0001 Y<= a+1 Increment A0010 Y<= a-1 Decrement A0011 Y<= b Transfer B0100 Y<= b+1 Increment A0101 Y<= b-1 Decrement A0110 Y<= a+b Add a and b0111 Y<= a+b+cin Add a and b and carry
1000 Y<= not a Complement a
Logic
1001 Y<= not b Complement b1010 Y<= a AND b AND1011 Y<= a OR b OR1100 Y<= a NAND b NAND1101 Y<= a NOR b NOR1110 Y<= a XOR b XOR1111 Y<= a XNOR b XNOR
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Mini Project
Session Two 41
- Required-VHDL code of this ALU -Verify functionality using ModelSim (Waveforms required)-Use ieee.std_logic_arith.all; package in your design
- Deadline-After Next session
LogicUnit
Arithmetic Unit
A(7:0)B(7:0)
Cin
SEL(3:0)
C(7:0)
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Assignment 02
Session Two 42
Write a code describing a 8-bit Register
Grouping Eight D_FF translated into a Register. Describe it with two outputs Q and inverted Q
Register
D
clk
QReset
Q’
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Summary
Session Two 43
- Signals are used for internal wiring. - Concurrent statements and Sequential statements are statements types of VHDL.- IF ELSIF ELSE and CASE statements should be written inside PROCESS- Process has sensitivity list that should contain all signals have priority than clock.- D-FF is the main memory unit in Digital logic design.
Examples Exercises Labs
5-12 1 1
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Time for Your Questions
Session Two 44
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Download Session 02 Files
Session Two 45
Read Session- 2 Examples carefully to be ready for the next session’s LAB QUIZ
Lab 01 www.startgroup.weebly.com/vhdl-examples.html
Reserved Words of VHDLwww.startgroup.weebly.com/vhdl-examples.html
Related Sessions
Tutorial 1 Refresh Your Memory 1
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Take Your NotesPrint the slides and take your notes here
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Take Your NotesPrint the slides and take your notes here
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See You Next Session .. Don’t miss
Thank
You
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