Approved for Public Domain Release (VS07-0571)

© 2007 BAE Systems

All rights reserved

A System-On-Chip Radiation Hardened

Microcontroller ASIC With Embedded

SpaceWire Router

Richard Berger, Laura Burcin, David Hutcheson, Jennifer Koehler, Marla Lassa, Myrna Milliser, David Moser, Dan Stanley, Randy Zeger, Ben Blalock, Mark Hale

International SpaceWire Conference 2007

2Approved for Public Domain Release (VS07-0571)

© 2007 BAE Systems

All rights reserved

Introduction / Project Goals

• The RAD6000MCTM microcontroller is being designed to consolidate all the

key elements needed for moderate levels of spaceborne computing into a

single ASIC

• It is flexible enough for a wide variety of applications, from instrument

control to “safe mode” back-up

• The RAD6000MC will be manufactured in BAE Systems’ RH15 150nm

radiation hardened technology, with a goal of 10x improvement in power-

performance vs. existing RAD600-based single board computers

• Based on the space-proven RAD6000 CPU, it will include strong software

support for users

– Green Hills Compiler

– VxWorks operating system with possible addition of real time

embedded solution as well

– Easy reuse/migration of existing RAD6000 application code

– Reuse of existing RAD6000 infrastructure

3Approved for Public Domain Release (VS07-0571)

© 2007 BAE Systems

All rights reserved

RAD6000MCTM Features• Processor Units

– RAD6000TM CPU

• Selectable 33 or 66 MHz clock

• Fixed and floating point execution units

• Up to 3 instructions/cycle

• 8KB unified D/I cache

– Embedded Microcontroller (EMC)

• SRAM and Non-volatile Memory with controllers

– 128 KB synchronous SRAM on-chip memory

– 32 KB C-RAMTM non-volatile program store

– External Memory controller for SRAM, DRAM,

C-RAM, etc.

– Direct Memory Access (DMA) controller

• I/O Bus and Communications Interfaces

– 33 MHz, 64-bit PCI interface (version 2.2)

– 16550 compatible UART

– SpaceWire router with 4 serial links

– Dual 1553 interface w/64 KB of on-chip SRAM

• JTAG master and slave test controllers

• Analog interfaces

– 12-bit, 8.25 Msps A-D converter

– 48 input programmable analog multiplexer

– Three 12-bit 1 Ksps D-A converters

• Planned Radiation Characteristics

– Total Dose: 1Mrad (Si)

– Single Event Effects

• <1E-10 errors/bit-day

• Latch-up immune

Mux/A/D

& D/As

PCI

MCC

6000 I/F

DMA

EMC

MISC

CAT

PCI

MCC

6000 I/F

DMA

EMC

MISC

CAT

PCI

- RAM™

32KB

NVRAMPCI

MCC

6000 I/F

DMA

EMC

MISC

CAT

64KB SRAM

Analog I/O

Control

64KB SRAM

64KB SRAM

SpaceWire4 port Router

1553

Conceptual layout shown

4Approved for Public Domain Release (VS07-0571)

© 2007 BAE Systems

All rights reserved

RAD6000MC ASIC Block Diagram

On-Chip Bus (OCB) Connection Medium

Embedded Microcontroller

(EMC)

64

OCB

Master

64

OCB

Slave

64KB

SRAM

Memory

OCB Slave

64KB SRAM

Memory

OCB Slave

6464

Programmable

Interrupt

Discretes

(PIDs)

MISC

32

OCB

Slave

JTAG

32

OCB Slave

JTAG Master

(JTAG)

33 MHz

PCI 2.2

64 64

OCB

Master

OCB

Slave

PCI-64

Clocks/Reset

Clock And

Test (CAT)

32

PLL

OCB Slave

Local Interface

Function (LIF)

64

OCB

Slave (2)

OCB

Master

64

JTAG

32

OCB Master

JTAG Slave

(JTAG)

I/O

RAD6000TM

CPU

External

MemoryCOP

Memory

RAD6000MCTM

Microcontroller ASIC

OCB

Slave

32

COP

Master

33/66MHz

64

1553 A/B

64 64

OCB Slave

D1553 Core

64KB SRAM

UART

UART

32

OCB Slave

Up to 48 External

Analog Inputs

Analog

Multiplexer

A/DConverter

OCB

Master

OCB

Slave

64 3264

Analog I/O

Control (AIC)

OCB

Master

D/AConverter

3 External

Analog Outputs

SpaceWire

Router

and Links

SpaceWire I/F x4

64

OCB

Master

32

OCB

Slave

64

Router I/F (RIF)

OCB

Master

FIF

O

FIF

O

OCB

Master

OCB

Slave

64 3264

Router I/F (RIF)

OCB

Master

FIF

O

FIF

O

32KB C-RAMTM

Memory

64

OCB Slave

Reused

New

Minor ModMajor Mod

DDC IP

Memory

Control

(MCTL)

64 3264

OCB

Master

OCB

SlaveOCB

Master

Direct Memory

Access (DMA)

5Approved for Public Domain Release (VS07-0571)

© 2007 BAE Systems

All rights reserved

RAD6000 Microprocessor

Unified

8KB Data /

Instruction

Cache

Memory Interface Unit

Input / Output Sequencer

UnitInstruction Queue &

Dispatch

Common On-Chip Processor (COP)

Test Unit

Memory Management Unit (MMU)

Memory Bus

w/ECC

I/O Bus

Data / Inst Addr

Data

Virtual

Address

Instructions

Data

Instruction Address

Data

Addre

ss

Data

COP Bus

Controls

to/from

Other Units

Branch Processor& Instruction Fetch

Pipeline

Control

Unit

Fixed Point

Execution Unit (FXU)

Floating Point

Execution Unit (FPU)

Cntl

Instructions

Cntl

Fixed and Floating Point Execution Units

Up to 3

instructions

per cycle:

fixed, float,

and branch)

Unified

L1 cache

Test and

Diagnostics

Unit

6Approved for Public Domain Release (VS07-0571)

© 2007 BAE Systems

All rights reserved

Local Interface Function (LIF) Block Diagram

RAD6000

Memory I/F

RAD6000

Memory Bus

PIO

I/F

RAD6000 I/O Bus

DMA

I/F

Configuration

Registers

OCB Master

I/F

OCB Slave

(0) I/F

OCB Master Stub OCB Slave (0) Stub

Memory

Configuration

I/F

Memory

Request

I/F

Memory

Controller

MC Bus

Memory

Controller

Request

Bus

OCB Slave

(1) I/F

OCB Slave (1) Stub

Contains Base

Address

Registers used

for Address

Translation, to

extend RAD6000

27-bit (128 MB)

address to 4 GB

Wrap feature supports

use of on-chip Start-up

ROM using the C-RAM

core

Additional slave

OCB interface

supports direct

access to external

memory from other

on-chip cores

7Approved for Public Domain Release (VS07-0571)

© 2007 BAE Systems

All rights reserved

RAD6000 Memory Address Translation

RSC_MEM_ADDR (0:23)

3

ADDR (31:0)

Base Address Registers

(8) 16 MB Pages

Base Addr Attr

8 21 3

0’s

To OCB or Memory Controller

The complete address

space is 4 GB, but the

available address space

for the RAD6000 is 2 GB

The other 2 GB is

dedicated for the other

cores within the system

The complete RAD6000

(RSC) memory address

bus is 27 bits

Only the 24 most

significant bits (MSBs) are

brought out, since the

RAD6000 accesses 64-bit

(8 byte) words from

memory

The 3 least significant bits

(LSBs) are shown padded

below with zeros

8Approved for Public Domain Release (VS07-0571)

© 2007 BAE Systems

All rights reserved

On-Chip Bus Slave Memory Address Translation

OCB_ADDR (31:0)

3 Bits (26:24)

ADDR (31:0)

Base Address Regs

(8) 16 MB Pages

Base Addr Attr

8 24

To RSC I/O Bus, OCB, or Memory Controller

Bits (31:24)

Rd Snoop Disable

Wr Snoop Disable

For accesses within the 128 MB RSC

addressable region: The Attr field for that

page determines if the access is snooped

Snooped accesses are passed directly to

the RSC I/O Bus

Non-snooped accesses pick up the Base

Addr field for the page and then are passed

to either the Memory Controller or OCB

For accesses above

the 128 MB RSC

addressable region:

The address is passed

directly to the Memory

Controller – no

snooping

9Approved for Public Domain Release (VS07-0571)

© 2007 BAE Systems

All rights reserved

SpaceWire Router Block Diagram and Features

Time Code

Port

Arbiter

Tx

Rx

Clocks

Crossbar

Routing

Switch

Config.

Port

Reg File

Routing Table

Rx

State

Machine

Config /

Status

Time

Code

Clocks / Timers

Data

StrobeDeserialize FIFO

Char detect Rx time

TxDataStrobe

FIFOSerialize Parity

Cmds Tx time

Rx

State

Machine

Config /

Status

Time

Code

Clocks / Timers

Data

StrobeDeserialize FIFO

Char detect Rx time

TxDataStrobe

FIFOSerialize Parity

Cmds Tx time

Rx

State

Machine

Config /

Status

Time

Code

Clocks / Timers

Data

StrobeDeserialize FIFO

Char detect Rx time

TxDataStrobe

FIFOSerialize Parity

Cmds Tx time

Rx

State

Machine

Config /

Status

Time

Code

Clocks / Timers

Data

StrobeDeserialize FIFO

Char detect Rx time

TxDataStrobe

FIFOSerialize Parity

Cmds Tx time

Rx

State

Machine

Config /

Status

Time

Code

Clocks / Timers

Data

StrobeDeserialize FIFO

Char detect Rx time

TxDataStrobe

FIFOSerialize Parity

Cmds Tx time

Rx

State

Machine

Config /

Status

Time

Code

Clocks / Timers

Data

StrobeDeserialize FIFO

Char detect Rx time

TxDataStrobe

FIFOSerialize Parity

Cmds Tx time

Rx

State

Machine

Config /

Status

Time

Code

Clocks / Timers

Data

StrobeDeserialize FIFO

Char detect Rx time

TxDataStrobe

FIFOSerialize Parity

Cmds Tx time

Rx

State

Machine

Config /

Status

Time

Code

Clocks / Timers

Data

StrobeDeserialize FIFO

Char detect Rx time

TxDataStrobe

FIFOSerialize Parity

Cmds Tx time

• SpaceWire core implementation

– Four SpaceWire ports include

integrated LVDS drivers /

receivers with support for

cold sparing

– Dual ports connected to On-

Chip Bus increase throughput

– 350 MHz maximum data rate

on SpaceWire link interfaces

• Unique switch enhancements

– Bypass Mode ignores

SpaceWire addressing and

fixes route assignment for

packet

– Local header byte indicates

port # received from and

presence of Logical Address

– Network blockage mitigation

by limiting packet length limits

risk of network stalling

Port

Arbiter

Tx

Rx

Port

Arbiter

Tx

Rx

Port

Arbiter

Tx

Rx

Port

Arbiter

Tx

Rx

Port

Arbiter

Tx

Rx

Port

Arbiter

Tx

Rx

To

RIF

an

d O

n-

Ch

ip B

us

External

Port

Tx FIFO

Rx FIFO

32

External

Port

Tx FIFO

Rx FIFO

32

10Approved for Public Domain Release (VS07-0571)

© 2007 BAE Systems

All rights reserved

Programmable Multiplexer and A/D Converter

• Analog Multiplexer with programmable

input configurations, supporting single-

ended, differential, or mixed input signals

• Select signals controlled from Analog I/O

Control digital core

• 12-bit Pipeline A/D converter with 1.5 bits per

stage (single stage shown)

• High performance Sample and Hold circuit with

Operational Transconductance Amplifiers

• Digital error correction tolerates 500 mV of

comparator offset

• Supported by Bandgap Reference circuit to

generate differential reference voltage

All (48)

Single

Ended

Inputs

All (24)

Differential

Inputs

32 Single

Ended

And 8

Differential

16 Single

Ended

and 16

Differential

11Approved for Public Domain Release (VS07-0571)

© 2007 BAE Systems

All rights reserved

Wilkinson Architecture Three Channel D/A Converter

• Wilkinson D/A

converter architecture

– Shared ramp

generator and digital

counter

– Repeated

comparators and

track and hold amps

• Pipelined gray code

digital counter uses

4,096 cycles for 12 bit

resolution @ 1 Ksps

• Track and Hold

samples ramp voltage

when comparator

pulses

• Minimal die and power

dissipation for low

speed conversion

Ramp

Generator

Digital

Counter

Track

and Hold

Amplifier

Digital

Comparator

Track

and Hold

Amplifier

Track

and Hold

Amplifier

Digital

Comparator

Digital

Comparator

12

12-bit

digital

inputs

12

4.125 MHz clock

Initiate

conversion

Analog

out

Analog

out

Analog

out

12Approved for Public Domain Release (VS07-0571)

© 2007 BAE Systems

All rights reserved

Analog Circuit Test Chips

BGR

DAC

Analog

Multiplexer

Pipeline A/D Converter test chip Wilkinson D/A Converter, analog

multiplexer, and Bandgap Reference

test chip

13Approved for Public Domain Release (VS07-0571)

© 2007 BAE Systems

All rights reserved

On-Chip Bus (OCB) Connection MediumOn-Chip Bus (OCB) Connection Medium

Embedded Microcontroller

(EMC)

64

OCB

Master

64

OCB

Slave

Embedded Microcontroller

(EMC)

64

OCB

Master

64

OCB

Slave

64KB

SRAM

Memory

OCB Slave

64KB SRAM

Memory

OCB Slave

6464

64KB

SRAM

Memory

OCB Slave

64KB SRAM

Memory

OCB Slave

6464

Programmable

Interrupt

Discretes

MISC

32

OCB

Slave

JTAG

32

OCB Slave

JTAG Master

(JTAG)

JTAG

32

OCB Slave

JTAG Master

(JTAG)

33 MHz

PCI 2.2

64 64

OCB

Master

OCB

Slave

PCI64

33 MHz

PCI 2.2

64 64

OCB

Master

OCB

Slave

64 64

OCB

Master

OCB

Slave

PCI64

64 3264

OCB

Master

OCB

Slave

DMA

OCB

Master

64 3264 64 3264

OCB

Master

OCB

Slave

DMA

OCB

Master

OCB

Master

OCB

Slave

DMA

OCB

Master

Clocks/Reset

Clock And

Test (CAT)

32

PLL

OCB Slave

Clocks/Reset

Clock And

Test (CAT)

32

PLL

OCB Slave

64

OCB

Slave (2)

OCB

Master

64

JTAG

32

OCB Master

JTAG Slave

(JTAG)

JTAG

32

OCB Master

JTAG Slave

(JTAG)

I/O

RAD6000TM

CPU

External

MemoryCOP

MCTL

Memory

RAD6000MCTM

Microcontroller ASIC

OCB

Slave

32

COP

Master

33/66MHz

64

1553 A/B

64 64

OCB Slave

D1553 Core

64KB SRAM

64 64

OCB Slave

D1553 Core

64KB SRAM

UART

UART

32

OCB Slave

UART

UART

32

OCB Slave

48 External

Analog Inputs

Analog Mux

A/D

Converter

OCB

Master

OCB

Slave

64 3264

Analog I/O

Control (AIC)

OCB

Master

D/A

Converter

3 External

Analog Outputs48 External

Analog Inputs

Analog Mux

A/D

Converter

OCB

Master

OCB

Slave

64 3264 64 3264

Analog I/O

Control (AIC)

OCB

Master

D/A

Converter

3 External

Analog Outputs

SpaceWire

Router

and Links

SpaceWire I/F x4

64

OCB

Master

32

OCB

Slave

64

Router I/F (RIF)

OCB

Master

FIF

O

FIF

O

64

OCB

Master

32

OCB

Slave

64

Router I/F (RIF)

OCB

Master

FIF

O

FIF

O

FIF

O

FIF

O

OCB

Master

OCB

Slave

64 3264

Router I/F (RIF)

OCB

Master

FIF

O

FIF

OOCB

Master

OCB

Slave

64 3264 64 3264

Router I/F (RIF)

OCB

Master

FIF

O

FIF

O

FIF

O

FIF

O

DDC IPDDC IP

In Standby Mode for this applicationIn Standby Mode for this application

Always OperationalAlways Operational

Operational for this applicationOperational for this application

32KB C-RAMTM

Memory

64

OCB Slave

32KB C-RAMTM

Memory

64

OCB Slave

Local Interface

Function (LIF)

Example Application – Robotic Arm Control on

a System With Distributed Computing

Tactile feedback for contact and grip pressure use pressure sensors that will feed into the A/D converter through the multiplexer

Robotic arm control will require control of

actuators for arm motion using one or more joints

with turn/twist and open/close capability that can be supported by the

D/A converters

As a distributed processor with very specific functions, a microkernel

Operating System is viable - external

memory is probably not

required for this application

SpaceWire serial links are used to support high speed data transfers, with routing to other subsystem elements as required

The 1553 interface is not required so it is shut off, freeing up an additional on-chip 64 KB memory block

The PCI bus would not be used – transfers to/from the main processor would occur across SpaceWire links

The RAD6000 would be booted from the on-chip C-RAM non-volatile memory

The RAD6000 floating point execution unit will be used to calculate required turning movements

Limited data is collected and stored, so on-chip memory should be sufficient in this case

14Approved for Public Domain Release (VS07-0571)

© 2007 BAE Systems

All rights reserved

On-Chip Bus (OCB) Connection MediumOn-Chip Bus (OCB) Connection Medium

Embedded Microcontroller

(EMC)

64

OCB

Master

64

OCB

Slave

Embedded Microcontroller

(EMC)

64

OCB

Master

64

OCB

Slave

64KB

SRAM

Memory

OCB Slave

64KB SRAM

Memory

OCB Slave

6464

64KB

SRAM

Memory

OCB Slave

64KB SRAM

Memory

OCB Slave

6464

Programmable

Interrupt

Discretes

MISC

32

OCB

Slave

Programmable

Interrupt

Discretes

MISC

32

OCB

Slave

JTAG

32

OCB Slave

JTAG Master

(JTAG)

JTAG

32

OCB Slave

JTAG Master

(JTAG)

33 MHz

PCI 2.2

64 64

OCB

Master

OCB

Slave

64 64

OCB

Master

OCB

Slave

PCI64

64 3264

OCB

Master

OCB

Slave

DMA

OCB

Master

64 3264 64 3264

OCB

Master

OCB

Slave

DMA

OCB

Master

OCB

Master

OCB

Slave

DMA

OCB

Master

Clocks/Reset

Clock And

Test (CAT)

32

PLL

OCB Slave

Clocks/Reset

Clock And

Test (CAT)

32

PLL

OCB Slave

Local Interface

Function (LIF)

64

OCB

Slave (2)

OCB

Master

64

JTAG

32

OCB Master

JTAG Slave

(JTAG)

JTAG

32

OCB Master

JTAG Slave

(JTAG)

I/O

RAD6000TM

CPU

External

MemoryCOP

MCTL

Memory

RAD6000MCTM

Microcontroller ASIC

OCB

Slave

32

COP

Master

33/66MHz

64

1553 A/B

64 64

OCB Slave

D1553 Core

64KB SRAM

64 64

OCB Slave

D1553 Core

64KB SRAM

UART

UART

32

OCB Slave

UART

UART

32

OCB Slave

48 External

Analog Inputs

Analog Mux

A/D

Converter

OCB

Master

OCB

Slave

64 3264

Analog I/O

Control (AIC)

OCB

Master

D/A

Converter

3 External

Analog Outputs48 External

Analog Inputs

Analog Mux

A/D

Converter

OCB

Master

OCB

Slave

64 3264 64 3264

Analog I/O

Control (AIC)

OCB

Master

D/A

Converter

3 External

Analog Outputs

SpaceWire

Router

and Links

SpaceWire I/F x4

64

OCB

Master

32

OCB

Slave

64

Router I/F (RIF)

OCB

Master

FIF

O

FIF

O

64

OCB

Master

32

OCB

Slave

64

Router I/F (RIF)

OCB

Master

FIF

O

FIF

O

FIF

O

FIF

O

OCB

Master

OCB

Slave

64 3264

Router I/F (RIF)

OCB

Master

FIF

O

FIF

OOCB

Master

OCB

Slave

64 3264 64 3264

Router I/F (RIF)

OCB

Master

FIF

O

FIF

O

FIF

O

FIF

O

DDC IPDDC IP

In Standby Mode for this applicationIn Standby Mode for this application

Always OperationalAlways Operational

Operational for this applicationOperational for this application

32KB C-RAMTM

Memory

64

OCB Slave

32KB C-RAMTM

Memory

64

OCB Slave

Example Application – Small Satellite Flight Computer

Analog interfaces will be used in both directions: actuator or

thruster control (D/A) and sensor health monitoring (multiplexed

A/D), with the EMC assisting in management of collected sensor

data to memory

Traffic between subsystems would travel across the

SpaceWire links and through the router, requiring

operation of the PLL associated with the serial links

and the EMC used to control transfers between the

router and on-chip memory blocks

1553 bus used

for GNC units

such as star

trackers, inertial

measurement

units (IMU), and

reaction wheels

The RAD6000

would run a

robust real-

time Operating

System,

necessitating

use of

additional

external

memory

The DMA core would perform block

memory transfers between on-chip

and external memory

15Approved for Public Domain Release (VS07-0571)

© 2007 BAE Systems

All rights reserved

Summary

• The RAD6000MC is a flexible microcontroller supported by a robust set of

digital and analog interfaces

– A redundant MIL-STD-1553 is provided, with embedded SRAM that can

be used elsewhere if the interface is not used

– A SpaceWire router with 4 serial links and dual internal ports is provided

for high speed transfer with minimal connections

– A 64-bit PCI interface offers increased parallel bus throughput

– Analog/Digital conversion is supported by a programmable multiplexer

– A novel approach was employed to achieve multiple channels of

Digital/Analog conversion with very low power dissipation

• Enhancements have been made to address previous limitations in the

RAD6000 microprocessor’s addressable memory space

• The ASIC is built around a reusable core architecture and heavily leverages

reuse of validated and flight proven designs

• RAD6000MC configuration can be matched to user applications, optimizing

features and power dissipation