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SpaceWire Interface User.doc

SpaceWire CODEC IP

User Manual

Ref: Uod_Link_User

Document Revision: 2.4

Date: 27th March 2009

SpaceWire CODEC IP

User Manual

Ref.:

Issue:

Date:

UoD-Link-User

2.4

27 March 2009

Page: 2 / 69

Page 2 of 69

Document Ref: UoD_Link_User

Issue No: 2.4

Issue Date: 27th March 2009

Author: Chris McClements

VHDL Code: tag uodcodec_cvsrel_2_3

Number of pages in document: 69

Document History: Date Issue Description Ref

6-Oct-2003 draft New UoD CODEC VHDL user manual cmc

19-Apr-2004 1.1 DDR output multiplexer synthesis description updated cmc

27-Oct-05 1.2 Use Latches configuration removed

CFG_SLOWRATE_SYSCLK description updated

cmc

2-July-2007 2.1 Fixed serial reset problem of txencode and transmit clock generators.

cmc

- 2.2 Not released cmc

22 January 2008

2.3 Update with CFG_SLOWCLK_10MHZ reference signal cmc

27 Mar 2009 2.4 Corrections after ESTEC review cmc

SpaceWire CODEC IP

User Manual

Ref.:

Issue:

Date:

UoD-Link-User

2.4

27 March 2009

Page: 3 / 69

Page 3 of 69

I CONTENTS

I CONTENTS ..................................................................................................................................... 3

II LIST OF FIGURES .......................................................................................................................... 6

III LIST OF TABLES ............................................................................................................................ 8

1 SCOPE ............................................................................................................................................ 9

2 APPLICABLE DOCUMENTS ........................................................................................................ 10

3 DEFINITIONS ................................................................................................................................ 11

3.1 TERMS AND DEFINITIONS ........................................................................................................... 11

3.2 VHDL CODE TERMS AND DEFINITIONS ....................................................................................... 11

3.3 DOCUMENT TERMS AND DEFINITIONS ......................................................................................... 12

4 CONFIGURATION MANAGEMENT ............................................................................................. 13

4.1 DIRECTORY STRUCTURE ........................................................................................................... 13

4.1.1 CODEC RTL files ............................................................................................................ 14

4.1.2 VHDL File Hierachy ......................................................................................................... 15

5 FUNCTIONAL OVERVIEW ........................................................................................................... 16

5.1 SYSTEM OVERVIEW ................................................................................................................... 16

5.2 FUNCTIONS ............................................................................................................................... 16

5.2.1 Configuration Overview ................................................................................................... 17

5.2.2 Initialisation State Machine .............................................................................................. 17

5.2.3 Receiver .......................................................................................................................... 17

5.2.4 Receiver Credit Counter .................................................................................................. 18

5.2.5 Receiver Error Recovery ................................................................................................. 18

5.2.6 Transmitter ...................................................................................................................... 18

5.2.7 Transmitter Clock Generator ........................................................................................... 18

5.2.8 Transmitter Credit Counter .............................................................................................. 18

5.2.9 Transmitter Error Recovery ............................................................................................. 18

6 TOP LEVEL CLOCK AND CONFIGURATION INTERFACE ....................................................... 20

6.1 CFG_RXBUF_ADDRLEN ....................................................................................................... 20

6.2 CFG_RATE_NUMBITS .......................................................................................................... 20

6.3 SYSTEM RESET ......................................................................................................................... 20

6.4 SYSTEM CLOCK ......................................................................................................................... 21

6.5 TRANSMIT BIT CLOCK ................................................................................................................. 21

6.5.1 Transmit clock configuration SYS_DEFAULT ................................................................. 23

SpaceWire CODEC IP

User Manual

Ref.:

Issue:

Date:

UoD-Link-User

2.4

27 March 2009

Page: 4 / 69

Page 4 of 69

6.5.2 Transmit clock configuration SYS_SLOWCLK ................................................................ 24

6.5.3 Transmit bit clock configuration SYS_SLOWCLK_DIV ................................................... 25

6.5.4 Transmit bit clock configuration SYS_DIV ...................................................................... 26

6.5.5 Transmit bit clock configuration SYS_EN ....................................................................... 27

6.5.6 Transmit bit clock configuration TXCLK_DEFAULT ........................................................ 28

6.5.7 Transmit bit clock configuration TXCLK_SLOWCLK ...................................................... 29

6.5.8 Transmit bit clock configuration TXCLK_SLOWCLK_DIV .............................................. 30

6.5.9 Transmit bit clock configuration TXCLK_ DIV ................................................................. 31

6.5.10 Transmit bit clock configuration TXCLK_EN ................................................................... 32

6.5.11 Variable data rate and default 10Mbits/sec data rate generation ................................... 33

6.5.12 Double Data Rate outputs ............................................................................................... 34

6.5.13 Transmit clock configuration and signals overview ......................................................... 35

6.6 10/5 MHZ REFERENCE CLOCK (SLOWCLK) ............................................................................. 36

6.7 RECEIVE BUFFER CLOCK............................................................................................................ 36

6.8 PIPELINING ............................................................................................................................... 36

6.9 DISCARDING EMPTY PACKETS ................................................................................................... 37

6.10 MAXIMUM OUTSTANDING CREDIT ............................................................................................ 37

6.11 TRANSMIT TIME-CODE HANDLING ........................................................................................... 37

6.12 INTENAL RECEIVER DISCONNECT AND INIT FSM TIMEOUT COUNTERS ....................................... 38

6.13 TIMING CYCLE SETTINGS ........................................................................................................ 39

6.14 DISCONNECT TIMEOUT UNCERTAINTY .................................................................................... 40

6.15 CONFIGURATION SIGNALS OVERVIEW ..................................................................................... 40

7 INTERNAL INTERFACE ............................................................................................................... 42

7.1 LINK STATE OPERATION ............................................................................................................ 42

7.1.1 Link Start-up .................................................................................................................... 42

7.1.2 Link Disable ..................................................................................................................... 43

7.2 DATA INTERFACE ...................................................................................................................... 43

7.2.1 Transmit ........................................................................................................................... 43

7.2.2 Transmit FIFO

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