a spacewire implementation of chainless boundary scan...
TRANSCRIPT
International SpaceWire Conference. 17th – 19th September 2007, Dundee, Scotland. 25/09/2007 p1
International SpaceWire Conference
17th – 19th September 2007
International SpaceWire Conference
17th – 19th September 2007
A SpaceWire Implementation of
Chainless Boundary Scan Architecture for
Embedded Testing
A SpaceWire Implementation of
Chainless Boundary Scan Architecture for
Embedded Testing
Mohammed Ali*
Dr. Omar Emam
Mohammed Ali*
Dr. Omar Emam
* Work carried out as part of PhD – Leicester Univeristy
International SpaceWire Conference. 17th – 19th September 2007, Dundee, Scotland. 25/09/2007 p2
IntroductionIntroduction
• Currently Astrium Ltd uses JTAG boundary scan to perform embedded testing.
• This has been successful on missions such as Inmarsat 4 and Skynet 5.
• This presentation proposes a novel boundary scan architecture “Chainless Boundary Scan” (Patent filed) which is well suited to SpaceWire based systems.
• What is JTAG boundary Scan and how does it work?
International SpaceWire Conference. 17th – 19th September 2007, Dundee, Scotland. 25/09/2007 p3
JTAG Boundary Scan- BackgroundJTAG Boundary Scan- Background
• JTAG Stands for:“Joint Test Action Group”
• The Group was setup in 1985 in Europe (Known as JETAG)
• In 1986, It expanded to include members outside of Europe and hence dropped the „E‟ from JETAG to become JTAG)
• The IEEE1149.1 std. was approved on the 15th
September 1990 and is known as:
• “IEEE Standard Test Access Port and Boundary Scan Architecture”
• How does boundary scan work?
International SpaceWire Conference. 17th – 19th September 2007, Dundee, Scotland. 25/09/2007 p4
Boundary Scan CellBoundary Scan Cell
Boundary-scan register
formed from „silicon
nails‟ cells.
Boundary-scan register
formed from „silicon
nails‟ cells.
Memory element
called scan-cell
P-INP-OUT
S-IN
S-OUT
TDI
TCK
TMS
TDO
Internal
core logic
TAP
controller
BPBP
Instruction register
TRST*
* = OPTIONAL within IEEE Std. 1149.1
Identity register *Data registers
Instruction register
International SpaceWire Conference. 17th – 19th September 2007, Dundee, Scotland. 25/09/2007 p5
Example: Performing interconnect
Testing
Example: Performing interconnect
Testing
Core
Logic
TDO
INST REG
Internal
ID REG*
00 10
1
0
1
X
X
X
X
TRST*
TDI
Core
Logic
TDO
INST REG
00 X0
X
X
X
1
0
1
1
TDI
TMS
TCK
TRST*
Test Access
Port
Test Access
Port
Boundary-scan register
formed from „silicon
nails‟ cells.
Boundary-scan register
formed from „silicon
nails‟ cells.
BP BP
ID REG*
Internal
IC1 IC2
External Interconnects
Between two ICs
External Interconnects
Between two ICs
International SpaceWire Conference. 17th – 19th September 2007, Dundee, Scotland. 25/09/2007 p6
Daisy-chaining Boundary Scan
Components & Issues
Daisy-chaining Boundary Scan
Components & Issues
TDI
C1 C2
TDO TDI
C3
TDO TDI
C4
TDO TDI TDO
TMS
TCK
• Connecting many components into small number of
chains (conventional test equipment provides 4 Chains).
• Throughput, management of different logic and different supply
levels, redundancy.
Issues:
• Breaks in the chain
X
International SpaceWire Conference. 17th – 19th September 2007, Dundee, Scotland. 25/09/2007 p7
Time for a changeTime for a change
International SpaceWire Conference. 17th – 19th September 2007, Dundee, Scotland. 25/09/2007 p8
Typical SpW based ArchitectureTypical SpW based Architecture
Memory 1
1
Router 1
Memory 2
Router 2
P1 P2
P3 P4
Sensor 1
Sensor 2 1
2
2
3 4
8 7Processor Array
5
6
7
8
3
4
5
6
International SpaceWire Conference. 17th – 19th September 2007, Dundee, Scotland. 25/09/2007 p9
“Chainless Boundary Scan”“Chainless Boundary Scan”
Test
Equipment
or
Ground
Station
BIST
Controller
Memory
SpW
Router
C1
C3
C2
C4
Any
comms
link
Target Hardware
SpW
SpW
SpW SpW
SpW
SpW
SpWSpW
Cn = Component n
Key
International SpaceWire Conference. 17th – 19th September 2007, Dundee, Scotland. 25/09/2007 p10
SpW Router to Boundary Scan
Adapter
SpW Router to Boundary Scan
Adapter
SpW Packet RouterSpW Packet Router
C
O
D
E
C
C
O
D
E
C
C
O
D
E
C
C
O
D
E
C
Boundary Scan
TAP Controller
and registers
Block B
Packet Interpreter
Packet Assembler –
Block A
Packet Interpreter
Packet Assembler –
Block A
CTRLs
Command
BusData
Bus
SpW I/Fs Physical Layer
SpW Router - Boundary Scan Adapter
Host device internal logic (e.g.
DSP ASIC) if adapter is not
stand-alone.
External
TAP I/F
SpWSpWSpWSpW
TAP Macro
command
Interpreter &
I/F adapter
Block C
TAP I/F
Block C can either be
standalone or form part of
either Block A or Block B.
Core
Logic
TDO
INST REG
Internal
ID REG*
00 10
1
0
1
X
X
X
X
TRST*TDI
TMSTCKTAP
Controller
BP
Micro-cmd
Test data
Ctrl signals
Internal
TAP Ctrl I/F
External
TAP I/F
Component external I/OsComponent external I/Os
International SpaceWire Conference. 17th – 19th September 2007, Dundee, Scotland. 25/09/2007 p11
Hybrid SolutionHybrid Solution
D2
D3
Stand-alone SpW Router - Boundary Scan Adapter
IP with Boundary Scan Gateable Router (G8R)
Stand-alone SpW Router - Boundary Scan Adapter
IP with Boundary Scan Gateable Router (G8R)
D1
TAP 1 TAP 2 TAP 3 TAP 4
D5
D6
D4
Standard
Boundaryscan
Architecture.
D1 to D6
Chainless
SpW based
Architecture
Hybridised Chainless and Standard
Boundary Scan Architecture
Operator
Command
& Data I/F
SpW
SpW
SpW
SpW
SpWSpW
SpWSpW
SpW
SpW
BIST
Controller
Memory
SpW
Router
C1 C2
C3
SpW Router - Boundary Scan
Adapter IP
D7External
TAP I/F
Component with standard
boundary scan
Components with built-in
SpW Router - Boundary
Scan Adapter IP
Spare
International SpaceWire Conference. 17th – 19th September 2007, Dundee, Scotland. 25/09/2007 p12
ConclusionConclusion
• Chainless Boundary scan using SpW based
architecture provides the following advantages:
– Tests can still be performed even after one or more
components have been configured in functional mode
or if a failure of a component occurs.
– The boundary scan vectors can be transported across
the network in macro-command and data packets
without having to translate them into IEEE1149.1
signal compatible format.
– Allows in-orbit testing possible as no additional test
infrastructure is required.