a pwm method for single-phase cascade multilevel inverters

A PWM method for single-phase cascade multilevel inverters toreduce leakage ground current in transformerless PV systems

Gerardo Vazquez1*,†, Panfilo R. Martinez-Rodriguez1, Gerardo Escobar2,Jose M. Sosa1 and Rigoberto Martinez-Mendez3

1Laboratory of Electricity and Power Electronics, ITESI, Km 12.5 Carr. Irapuato-Silao, GTO 36821, Mexico2Graduate School of Engineering-UADY, 97310 Merida, Yucatan, Mexico

3Autonomous University of Mexico State, Department of Engineering, Cerro de Coatepec s/n, Ciudad Universitaria, C.P.50100 Toluca, Estado de México, Mexico

SUMMARY

A single-phase cascade multilevel inverter is able to synthesize AC output voltages with considerablyreduced harmonic distortion, which results in reduced size output filters. In addition, the amplitude of theoutput voltage in the cascade multilevel inverter topology is usually higher than in a single H-Bridgeinverter, which makes possible the power injection into the grid without a voltage boost stage. These ben-efits make cascade multilevel inverter a suitable topology for PV applications. However, cascade multilevelinverters may exhibit large leakage ground current in a grid-connected PV transformerless system, which iscaused by a variable voltage across the stray capacitances formed between the PV panel and ground. In thispaper, a modulation strategy for the cascade multilevel inverter is proposed to deal with leakage groundcurrents arising in transformerless PV applications. Numerical and experimental results are performed toassess the effectiveness of the proposed modulation strategy in the reduction of leakage ground currentsand improving the topology efficiency. Copyright © 2016 John Wiley & Sons, Ltd.

key words: PV system; transformerless inverter; leakage ground current; multilevel power inverters.

1. INTRODUCTION

Transformerless grid-connected inverters have shown several advantages as compared to transformerbased isolated inverters, namely, small size and weight, low cost and high efficiency [1–7]. However,in large-scale PV systems, a step-up transformer is anyhow included to isolate the PV system becauseof the high voltage imposed by the electrical grid. Therefore, a transformerless solution might be lim-ited to relatively low power systems, including residential and commercial applications. In these cases,where the voltage at the Point of Common Coupling (PCC) is relatively low, transformerless invertersare the preferred solution as they exhibit an excellent performance [8].Nevertheless, the lack of galvanic isolation may cause considerable leakage ground current (LGC)

throughout the ground path, which is the result of a variable voltage established across the stray capac-itances formed between the PV array and ground [9]. This voltage is directly related with the common-mode voltage (CMV) generated in the inverter, which depends on the inverter topology, its modulationstrategy and the control law [9,10]. All these factors clearly affect the magnitude and frequency of theLGC generated in a PV system. For instance, in the basic single-phase H-bridge (HB) converter usedas a transformerless PV inverter, it is well known that a unipolar pulse width modulation (PWM) pre-sents LGC, while the bipolar PWM scheme avoids voltage oscillations across the stray capacitances,and thus no LGC.

*Correspondence to: Gerardo Vazquez, Laboratory of Electricity and Power Electronics, ITESI, Km 12.5 Carr. Irapuato-Silao, GTO 36821, Mexico.†E-mail: [email protected]

Copyright © 2016 John Wiley & Sons, Ltd.

INTERNATIONAL TRANSACTIONS ON ELECTRICAL ENERGY SYSTEMSInt. Trans. Electr. Energ. Syst. 2016; 26:2353–2369Published online 22 March 2016 in Wiley Online Library (wileyonlinelibrary.com). DOI: 10.1002/etep.2208

The LGC not only affects the system efficiency and reliability and causes electromagnetic interfer-ence (EMI) issues, but also represents a potential electrical hazard to humans, which may get in contactwith the PV array [11,12]. Therefore, efforts are conducted during the design of transformerless grid-connected converters to try to alleviate or fully eliminate the LGC issue.Several solutions have emerged to address the LGC issue, which include the design of modulation

schemes and control strategies [12–14], as well as the proposal of new transformerless grid-connectedconverter topologies [11,15–17]. For instance, the neutral point clamped (NPC) topology, frequentlyappealed in transformerless PV applications, intrinsically exhibits low LGC. The neutral connection inNPC reduces the voltage fluctuations across the stray capacitances, which considerably reduces theLGC. This makes NPC based systems able to comply withmost international regulations. Themain issuesin this topology are the need of a boost stage and an additional control loop to balance the capacitors.In [12], a space vector modulation (SVM) technique is applied to a three-phase transformerless NPC

inverter guaranteeing low LGC. In [14], a high-reliability single-phase transformerless inverter ispresented. This topology is implemented with superjunction MOSFETs to achieve high efficiency.The modulation scheme, based on a single-carrier sinusoidal strategy, is designed to keep the CMVconstant, and thus, reducing the magnitude of the LGC.Proposals of transformerless topologies based on the full-bridge configuration (and their modulation

schemes aimed to reduce the LGC) have been presented in [15,16,18,19]. For instance, [16] presents amodified H6 inverter topology aimed to reduce LGC. This inverter consists of a single-phase HB in-verter plus a DC-decoupling stage. The latter is implemented by the interconnection of two switchesand two diodes, where the diodes are used to keep a constant CMV. In [20], a modulation strategyfor a new topology of a three-phase NPC converter is proposed. Its implementation involves twoadditional switches, two diodes and split capacitors on the DC-side, with limited blocking voltageon the switches. In [21], a modified full-bridge topology is presented, which includes two moreswitches and diodes. In this topology, the LGC is minimized by means of a unipolar PWM scheme.The single-phase topology proposed in [22] involves two split AC-coupled inductors, which operateseparately for positive and negative grid semi-cycles. Additionally, two AC-side switches allowdecoupling of the PV array from the grid, thus reducing the high-frequency LGC.Cascade multilevel inverters (CMI) represent an attractive solution for grid-connected PV systems.

The CMI offers several advantages over two or three level inverter topologies. For instance, CMItopologies do not need an additional boost stage to generate an AC signal of the required voltage levelto guarantee proper active power injection. Notice that this fact represents an improvement of the over-all efficiency of the PV system. Additionally, the harmonic content of the AC voltage is low, whichtranslates into output filters of smaller size with guaranteed low harmonic distortion. All these benefitsmake the CMI very attractive for transformerless PV applications.Research on these inverters has been focused on the analysis of topologies [10], the proposal of

modulation schemes [6,23] and modifications to the basic CMI topology [24]. In [23], a modulationscheme is proposed to deal with different capacitor voltages in the DC-link to obtain increased outputvoltage level number. In particular, there have been modulation schemes and modifications to the basictopology aimed to reduce the LGC. For instance, in [6], a HB based topology is proposed, which includestwo additional switches and a split capacitor, and uses a unipolar SPWM scheme. In [25], a single-phasethree-level six-switch topology is proposed. The authors in [24] present a modified H6 inverter topologywithout input split capacitors, while using a hybrid modulation scheme.The use of the CMI topology in transformerless PV systems has been reported in [26–28]. In these

works, the authors address two main issues, namely, the control strategy to balance the DC input volt-ages, and alternatives for the sinusoidal modulation strategy. In [8], a solution is proposed to reduceLGC in the CMI topology in a PV application. This solution consists in the addition of two passivefilters built with inductors and capacitors. The design of these filters is based on simplified leakagecurrent analytical models. However, this solution introduces additional costs, size and losses.This paper presents a modulation strategy1 for a CMI that significantly reduces the LGC throughout

the ground path, without the need of additional semiconductors or passive components. As a

1This paper is based on the conference paper [29]. This updated version includes experimental results which allow to compare theperformance of the proposed modulation strategy with two commonly used modulation strategies for the same inverter topology.

G. VAZQUEZ ET AL.2354

Copyright © 2016 John Wiley & Sons, Ltd. Int. Trans. Electr. Energ. Syst. 2016; 26:2353–2369DOI: 10.1002/etep

consequence, the converter achieves high efficiency as well. The idea behind the proposed modulationstrategy consists in selecting switching states that reduce both the transitions on the voltage across thestray capacitances and the number of switching transitions in semiconductors. The performance of theproposed modulation strategy is assessed by means of numerical and experimental results.

2. THE SWITCHING STATE ANALISYS OF THE CMI

Figure 1 shows the CMI topology configured as a transformerless PV inverter. The topology consists of twoHBs (CELL1 and CELL2) connected in cascade, where each one of these has an independent DC source.Notice that a simple resistive–inductive (RL) load has been considered in this study. On the one

hand, inductor L represents the usual filter to allow the grid connection. And, on the other hand, thevoltage drop in R represents the grid voltage. For this, it is assumed that there is a suitable controllerthat guarantees a unitary power factor operation. This simplification allows to focus only on themodulation strategy and its effects on the LGC, disregarding the effect of the controller. As mentionedin [15] the grid voltage generally does not influence the leakage current behavior.The analysis of the CMI topology in the PV transformerless applications takes into consideration the

stray capacitances, which appear between the PV cells and the grounded frame that covers the edge ofthe PV panel [30]. As shown in Figure 1, the stray capacitances are modeled as relatively small capac-itors connected from both terminals of the PV panels to ground. The value of these capacitancesdepends on several operation conditions, namely, moisture, panel size, power converter structure,modulation strategy, among others. In [31], some experiments have been performed to estimate thevalue of such parasitic capacitances, which may be around 200nF and 1μF per kW.The CMI topology shown in Figure 1 adopts 16 different switching combinations to generate the

five voltage levels at the output. The possible combinations are listed in Table I.Assuming that voltages on the DC-side are balanced at a desired DC constant voltage level,2 i.e.

VDC1=VDC2=VDC, then there are several (redundant) states generating the same output voltage.

Figure 1. Cascade multilevel inverter topology.

2Notice that this condition happens only in the case of panels having the same operating point in voltage and current. This con-sideration allows to focus only on the modulation strategy and its effects on the LGC. Surely, unbalance in the DC-side voltagesaffect the LGC; however, the study of this effect in combination with the effect of the modulation strategy in the LGC is left forfuture research.

PWM METHOD FOR TRANSFORMERLESS PV SYSTEMS 2355


For instance, states E2, E21, E22 and E23 generate an output voltage VDC, as it can be deduced fromTable I. Hence, different modulation schemes can be proposed based on the use of redundant states togenerate a given output voltage level. The idea behind the proposed modulation scheme is that theproper selection of the redundant states in a modulation strategy may provide additional improvementsin the topology performance. For instance, reduction of the switching and conduction losses can beachieved. In particular, these redundant states can be properly selected to reduce the LGC, which isthe main objective of this work.

2.1. Conventional modulation strategies

In what follows, the performance of the grid tied transformerless CMI under two conventional modulationstrategies is studied by means of simulations. The conventional strategies considered are the SinusoidalPhase-Shifted PulseWidthModulation (SPSPWM) strategy used in [26], and the multiple carrier Sinusoi-dal Level-Shifted Pulse Width Modulation (SLSPWM) strategy. In both cases, the five-level CMI to-pology shown in Figure 1 is considered using the parameters summarized in Table II.Figure 2 shows the performance of the CMI under the SPSPWM strategy. In Figures 2(a) and 2(b) the

output current (Iout) and the output voltage (Vout) are depicted, respectively. Notice that Vout shows thecharacteristic five output voltage levels, namely, 2VDC, VDC, 0,�VDC and�2VDC. Therefore, its har-monic content is lower than in the conventional HB single-phase based PV transformerless converter,which provides only three different levels in the output voltage. Notice also that the maximum voltageavailable at the output is twice the individual DC input voltage. However, as depicted in Figure 2(c), large

Table I. Switching states for the CMI.

Vout State

State of the semiconductors

S1 S2 S3 S4 S1′ S2′ S3′ S4′

VDC1+VDC2 E1 1 0 1 0 0 1 0 1VDC1 E2 1 0 1 1 0 1 0 0VDC2 E21 1 1 1 0 0 0 0 1VDC1 E22 1 0 0 0 0 1 1 1VDC2 E23 0 0 1 0 1 1 0 10 E3 1 1 1 1 0 0 0 00 E31 0 0 0 0 1 1 1 1VDC1�VDC2 E32 1 0 0 1 0 1 1 0�VDC1+VDC2 E33 0 1 1 0 1 0 0 10 E34 0 0 1 1 1 1 0 00 E35 1 1 0 0 0 0 1 1�VDC1 E4 0 1 0 0 1 0 1 1�VDC2 E41 0 0 0 1 1 1 1 0�VDC1 E42 0 1 1 1 1 0 0 0�VDC2 E43 1 1 0 1 0 0 1 0�VDC1�VDC2 E5 0 1 0 1 1 0 1 0

Table II. System parameters of the CMI-VSI topology.

Parameter Value

VDC1=VDC2 150VCp1=Cp2=Cp3=Cp4 160 nFR 16ΩL 3mHC 1000μFFsw 5kHzFgrid 60HzModulation Index 0.85



voltage variations occur between the PV terminals and ground.3 As a consequence, the LGC flowingthroughout the ground path reaches a considerably high level, as observed in Figure 2(d).Figure 3 shows the performance of the CMI under the SLSPWM strategy. Notice that, the charac-

teristic five voltage levels are also present at the converter output, as it is shown in Figure 3(b). How-ever, the LGC level is still high because of a large dv/dt across the stray capacitances. From Figures 2(d) and 3(d), the RMS values of leakage current are 1.69A and 838mA, respectively. Therefore, noneof the above two cases complies with the German standard VDE 0126-1-1 [32], which establishes amaximum leakage current4 of 300mA.Alternative modulation strategies for the CMI include the SVM [27,34], and multicarrier based mod-

ulation strategies, such as the Alternate Phase Disposition (APOD), the Phase Opposition/Disposition(POD) and the Phase Disposition (PD) [35]. However, none of these strategies addressed the leakagecurrent issue.In this paper, a multiple carrier based modulation strategy is proposed. The modulation strategy is

implemented based on the level shifted technique explained in the following section. The ideabehind the proposed modulation strategy is to keep, as constant as possible, the voltage across thestray capacitances. The latter are represented by small capacitances attached to each DC terminalin the CMI topology under study and referred to ground.

3. PROPOSED MODULATION STRATEGY

The proposed modulation strategy is based on the aforementioned SLSPWM strategy. Moreover, theproposed strategy exploits the redundancy of the different permissible states shown in Table I. Recallthat each permissible state produces a given output voltage level. For the CMI under study, five differ-ent levels can be generated. Hence, four different sectors can be defined as follows.

Figure 2. Simulation results of the grid tied five-level CMI using SPSPWM. (From top to bottom) Outputcurrent (Iout), output voltage (Vout), voltage across the stray capacitance (Vcp1) and leakage current

(Ileak).

3Due to space limitations, only the voltage of Cp1 is shown here. However, in both modulation strategies the voltages across allother stray capacitances Cp2, Cp3 and Cp4 exhibit large dv/dt along the sinusoidal period.4Recall that, beyond this limit, the residual current monitoring device has to be triggered, as it is stated in the standard EN/IEC62109-2 [33].



• Sector 1: The output voltage changes from 0 to VDC and vice-versa.• Sector 2: The output voltage varies from VDC to 2VDC and vice-versa.• Sector 3: The output voltage varies from 0 to �VDC and vice-versa.• Sector 4: The output voltage changes its value from �VDC to �2VDC and vice-versa.

The methodology to select the switching states used in the proposed modulation strategy5 consists inanalyzing all equivalent circuits of the 16 available switching states described in Table I, and selectingthose switching states minimizing the dv/dt over the stray capacitances, i.e. those states minimizing theCMV variations. The proposed strategy is referred as CMCR-SLSPWM, where CMCR stands forcommon-mode current reduction. In addition, the selection methodology also considers the reductionof the number of switching transitions in semiconductors, which translates in the reduction of powerlosses. Therefore, two main objectives are covered in the proposed CMCR-SLSPWM modulationstrategy, namely, reduction of LGC and power losses.As part of the proposed CMCR-SLSPWM modulation strategy, the permissible switching states are

classified into four groups depending on the sector of the generated voltage level. Notice that, on eachsector, there are only two possible voltage levels. Moreover, each of these levels on a given sector maybe produced by more than one switching state belonging to that group (according to Table I). TheCMCR-SLSPWM modulation strategy proposes the selection of the two most convenient states oneach sector to produce the associated levels. The criterion for this selection is to keep the voltage acrossthe stray capacitances as constant as possible and to produce the two states with minimum switchingtransitions.The proposed CMCR-SLSPWM modulation strategy can be better visualized by using the equivalent

circuits of each selected switching state as follows.

Sector 1, State E33 (Vout = 0). During this state, switches S2 and S1′ of CELL1, and S3 and S4′ ofCELL2 are on. Hence, the output voltage is equal to zero as CELL1 generates VDC1, while CELL2generates �VDC2. This condition is only valid whenever VDC1=VDC2. This state is depicted inFigure 4(a).

5The proposed modulation strategy is only valid for the topology depicted in Figure 1, i.e. for the CMI involving two cells. Theextension of this modulation strategy to a more general n-level CMI topology is left for future investigations.

Figure 3. Simulation results of the grid tied five-level CMI using the SLSPWM strategy. (From top tobottom) Output current (Iout), output voltage (Vout), voltage across the stray capacitance (Vcp1) and

leakage current (Ileak).



Sector 1, State E21 (Vout =VDC). Figure 4(b) shows the second state in sector 1. In this case theconfiguration of CELL2 is the same as in the previous state. However, the CELL1 is configured togenerate zero voltage by turning on switches S1 and S2 (upper switches of CELL1). Out of this, theoutput voltage becomes VDC.Sector 2, State E23 (Vout =VDC). During this state, shown in Figure 5(a), the CELL2 remains asin the previous configuration, while the CELL1 is configured to generate zero voltage at its output.In this case, zero voltage is generated by using the lower switches of the CELL2, namely, S1′ andS2′, which decouples the positive terminal of CELL1.Sector 2, State E1 (Vout = 2VDC). An output amplitude of twice the input voltage is obtained bythe sum of both DC sources. This can be achieved by means of the configuration shown in Figure 5(b), where switches S1, S2′, S3 and S4′ are all turned on. This generates a voltage of VDC on eachcell.Sector 3, State E32 (Vout = 0). In this case zero voltage is generated by means of the configurationshown in Figure 6(a). A positive voltage is generated by using CELL1, while a negative voltage isgenerated by using CELL2. Notice that this is the opposite situation to the Sector 1, State E33 aboveexplained.

Figure 4. CMI states for Sector 1.




Sector 3, State E41 (Vout =�VDC). A�VDC voltage is obtained by turning on switches S1′, S2′,S4 and S3′ as shown in Figure 6(b), where the CELL1 provides zero voltage at its output, whileCELL2 provides a negative voltage.Sector 4, State E43 (Vout =�VDC). As observed in Figure 7(a), to obtain a negative voltage dur-ing this part of the negative semi-cycle, switches S1 and S2 generate zero voltage at the CELL1 out-put, while CELL2 keeps the same configuration during the entire negative semi-cycle.Sector 4, State E5 (Vout =�2VDC). Finally, the configuration shown in Figure 7(b) produces anegative output voltage of twice the input voltage. In this case, both cells are configured to provide�VDC at their outputs. As a result �2VDC is obtained at the output.

The voltages across the stray capacitances can now be obtained by analyzing each equivalent circuitin both levels of each sector as above described in the proposed CMCR-SLSPWM modulationstrategy. These voltages, for each case, are summarized in Table III.As observed in Table III, Vcp1 and Vcp2 have only one voltage transition during each semi-cycle

and on each zero-crossing of the output voltage, that is, at every transition between sectors. During thepositive semi-cycle of the output voltage, the voltage across Cp1 changes from VDC to 2VDC, whilethe voltage in the terminals of Cp2 changes from 0 to VDC. In the case of Vcp3 and Vcp4, there is one





voltage transition at every zero-crossing of the output voltage, i.e. at every change of polarity of theoutput voltage. For instance, in the case of Cp3, the voltage changes from VDC to 0, while in Cp4,the voltage changes from 0 to �VDC. These voltages variations across the stray capacitances causenegligible LGC spikes throughout the ground path, which are described in the next section.

4. SIMULATION RESULTS

Simulation results have been carried out to evaluate the performance of the CMCR-SLSPWM mod-ulation strategy presented in Section 3. The simulations are implemented using the same simulationparameters as in Section 2. Only the operation in open loop is evaluated.6 Figures 8(a) and 8(b) showthe output current and the output voltage, respectively. Notice that the output voltage exhibits thecharacteristic five voltage levels. This has the benefit of a lower harmonic distortion as comparedto classical solutions in single-phase transformerless proposals. In addition, the load current has aquasi-sinusoidal waveform plus the switching ripple. The latter has a frequency of double the carrierfrequency. Therefore, the filter requirements are the same as in a HB inverter with unipolar modula-tion strategy. Figure 8(c) shows the voltage across the stray capacitance Cp1. Notice that the wave-form includes the voltage transitions described in Section 3. These voltage transitions generate theLGC depicted in Figure 8(d).Voltages across Cp1 and Cp3 have been depicted in Figure 9 to better understand the effect of the

voltage across the stray capacitances causing the LGC. Notice that, voltages across Cp2 and Cp4 areequal to those across Cp1 and Cp3, respectively. As it can be observed, the voltage measured in theterminals of Cp1 exhibits six voltage changes along an entire output voltage period. However, thevoltage of Cp3 changes only twice over a whole period. Hence, the simulation results match the resultsobtained by analysis above summarized in Table III.As above discussed, the voltage transitions shown in Figures 9(a) and 9(b) produce leakage currents

in the associated stray capacitances. The total effect of all voltage transitions on the LGC is depicted inFigure 9(c). As observed in Figure 9(c), spikes in the LGC appear whenever a non zero dv/dt over thestray capacitances occurs. Notice that the proposed CMCR-SLSPWM strategy significantly reducesthe LGC level. In fact, the RMS value of the LGC is about 219mA, which complies with the Germanstandard. This qualifies the CMI as a good candidate for transformerless PV applications. To calculatethe switching losses on each modulation strategy considered in this paper, and to provide an approx-imate of their efficiency, the waveforms of each strategy have been also obtained and analyzed.Figures 10–12 give a rough idea of the amount of switching transitions occurring on each modulationstrategy. Notice that the proposed CMCR-SLSPWM strategy considerably reduces the switching

Table III. Voltages across the stray capacitances on both levels of each sector.

Sector State

Stray capacitance voltage

Vcp1 Vcp2 Vcp3 Vcp4

1 E33 VDC 0 VDC 0E21 VDC 0 VDC 0

2 E23 2VDC VDC VDC 0E1 2VDC VDC VDC 0

3 E32 0 �VDC 0 �VDCE41 0 �VDC 0 �VDC

4 E43 �VDC �2VDC 0 �VDCE5 �VDC �2VDC 0 �VDC

6Feedback control of this system is out of the scope of the present paper. As previously mentioned, the use of a resistor as a loadcan be seen as a simplification of a grid connected system where a suitable controller guarantees operation at a PF = 1. Researchactivities on the control design are being carried out at this moment and the results will be reported in the near future.



losses because only two switches are controlled at the switching frequency. In contrast, the SPSPWMstrategy has the most switching transitions, and thus, the switching losses are expected to be the worst.To corroborate this, simulations using the thermal module of PSIM software have been also per-formed. For this, the model of the IGBT PM75DSA120 (1200V y 75A) has been used. It is consideredthat the system injects around 8 kW of active power in all three modulation strategies, namely,SPSPWM, SLSPWM and CMCR-SLSPWM. Moreover, notice that only the power losses of the semi-conductors are considered. The results reveal an efficiency of 94.56% for the SPSPWM, 97.9% for theSLSPWM and, 98.47% for CMCR-SLSPWM strategy. This confirms that the efficiency improvement

Figure 8. Time responses of the proposed CMCR-SLSPWM modulation strategy: (a) Output current (Iout),(b) Output Voltage (Vout), (c) Vcp1 and (d) Leakage current (Ileak).

Figure 9. Voltages across the stray capacitances and LGC in the CMI under the proposed CMCR-SLSPWMmodulation strategy: (a) Vcp1, (b) Vcp3 and (c) Ileak.



is yet another important contribution of the proposed modulation strategy. Table IV summarizes thesimulation results in a quantitative form for a better comparison.

5. EXPERIMENTAL RESULTS

The proper operation of CMCR-SLSPWM strategy has been verified by experimental results per-formed in the laboratory prototype shown in Figure 13. As in the simulation test, the experiments

Figure 10. Switching pattern of the SPSPWM strategy for switches (from top to bottom) S1, S2, S3 and S4.

Figure 11. Switching pattern of the SLSPWM strategy for switches (from top to bottom) S1, S2, S3 and S4.

Figure 12. Switching pattern of the CMCR-SLSPWM strategy for switches (from top to bottom) S1, S2, S3and S4.

Table IV. Performance of modulation strategies under study.

Modulation strategy LGC (IleakRMS) Efficiency (%)

SPSPWM 1.69A 94.56%SLSPWM 838mA 97.9%CMCR-SLSPWM 219mA 98.47%Norm VDE 0126-1-13 300mA —



consider only open loop operation, with the same parameters listed in Table II. The modulation strat-egies SLSPWM and SPSPWM have been also implemented and tested for comparison purposes. Theprototype was implemented with SKM100-GB124D IGBT modules controlled by SKHI-22A drivers.A dSPACE ACE1103 control board is used to generate the switching patterns. The DC voltage of bothpower cells is provided by two independent constant DC power supplies as in the simulations. Parasiticcapacitances Cp1, Cp2, Cp3 and Cp4 have been emulated using MKP (Metallized PolypropyleneFilm) capacitors, connected in both positive and negative terminals of each DC source and referred

Figure 13. Modular experimental setup for the CMI.

Figure 14. Time responses under SPSPWM method: (From top to bottom) output current (Iout), outputvoltage (Vout), voltage across Cp1 (Vcp1) and LGC.



to ground. Finally, the dead time to avoid short circuit in the legs of each inverter module is fixed to3μs.Time responses of the SPSPWM, SLSPWM and CMCR-SLSPWM strategies are depicted in

Figures 14–16, respectively. Each of these figures shows (from top to bottom) output voltage (Vout),output current (Iout), Vcp1 voltage and LGC. Notice that, in all three cases, the output current has asinusoidal waveform plus the associated switching ripple. The latter exhibits a switching frequencyof four times the carrier frequency in the SPSPWM method, while it is only double the carrierfrequency in the other two cases. Moreover, in all three cases, the output voltage exhibits the charac-teristic five levels. Notice that, the voltage across the stray capacitance Cp1 and the LGC matches thesimulations results presented in the previous section.The experimental results show that the LGC level in the CMCR-SLSPWM strategy is very low, as

predicted by simulations. In contrast, the LGC in SLSPWM and SPSPWM is relatively high,overpassing the maximum allowed levels. Finally, the switching sequences for all three modulation

Figure 15. Time responses under SLSPWM method: (From top to bottom) output current (Iout), outputvoltage (Vout), voltage across Cp1 (Vcp1) and LGC.

Figure 16. Time responses under the proposed modulation strategy: (From top to bottom) output current(Iout), output voltage (Vout), voltage across Cp1 (Vcp1) and LGC.



Figure 18. Switching signals for the SLSPWM method.

Figure 17. Switching signals for the SPSPWM method.

Figure 19. Switching signals for the proposed CMCR-SLSPWM modulation strategy.



methods studied in this paper are also obtained from the prototype. The results are depicted inFigures 17–19 for the SPSPWM, SLSPWM and CMCR-SLSPWM strategy, respectively. Notice thatthese experimental curves match those obtained numerically. Therefore, the comparison results shownin Table IV are very close the experimental ones.

6. CONCLUSIONS

A novel modulation strategy for the CMI, referred as CMCR-SLSPWM, was proposed to alleviate theLGC issue. The proposed strategy for the CMI consisted in a modification of the carrier based modu-lation strategy SLSPWM widely used to control power inverters. On the one hand, the CMI topologyrepresented a good candidate for PV applications as it presented higher output voltage levels than othertopologies based on the traditional HB topology, it exhibited low THD because of multiple voltagelevels at the output, and it relaxed the voltage stress across the semiconductors. On the other hand,it was shown that the proposed CMCR-SLSPWM strategy, applied to the CMI, achieved much lowerLGC and higher efficiency than conventional carrier-based modulation strategies used to control theCMI such as SLSPWM and SPSPWM. This was demonstrated by both simulation and experimentalresults. The efficiency studies involved the calculation of switching losses, where a particular IGBTmodel was used. In fact, the proposed CMCR-SLSPWM strategy was able to fulfill the requirementsof the German standard VDE 0126-1-1 [32]. These benefits showed that, the conjunction of the CMItopology and the proposed CMCR-SLSPWM strategy represents a promising solution fortransformerless PV applications.

7. LIST OF SYMBOLS AND ABREVIATIONS

PWM Pulse Width ModulationPV PhotovoltaicAC Altern CurrentPCC Point of Common CouplingLGC Leakage Ground CurrentCMV Common Mode VoltageEMI Electromagnetic InterferenceNPC Neutral Point ClampledSVM Space Vector ModulationDC Direct CurrentCMI Cascaded Multilevel InverterSPWM Sinusoidal Pulse Width ModulationSPSPWM Sinusoidal Phase-Shifted Pulse Width ModulationSLSPWM Sinusoidal Level-Shifted PulseWidth ModulationAPOD Alternate Phase DispositionPOD Phase Opposition/DispositionPD Phase DispositionCMCR-SLSPWM Common-Mode CUrrent ReductionHB H-Bridge

REFERENCES

1. Calais M, Myrzik J, Spooner T, Agelidis V. Inverters for single-phase grid connected photovoltaic systems—anoverview. Proc. of the IEEE Power Electronics Specialists Conference, 2002, vol. 4, Queensland, Australia, June2002; 1995–2000.



2. Xue Y, Chang L, Kjaer SB, Bordonau J, Shimizu T. Topologies of single-phase inverters for small distributed powergenerators: an overview. IEEE Transaction on Power Electronics 2004; 19(5):1305–1314.

3. Kjaer S, Pedersen J, Blaabjerg F. A review of single-phase grid-connected inverters for photovoltaic modules. IEEETransaction on Industrial Electronics 2005; 41(5):1292–1306.

4. Gonzalez R, Gubia E, Lopez J, Marroyo L. Transformerless single-phase multilevel-based photovoltaic inverter.IEEE Transaction on Industrial Electronics 2008; 55(7):2694–2702.

5. Yang B, Li W, Zhao Y, He X. Design and analysis of a grid-connected photovoltaic power system. IEEE Transac-tion on Power Electronics 2010; 25(4):992–1000.

6. Xiao H, Xie S, Chen Y, Huang R. An optimized transformerless photovoltaic grid-connected inverter. IEEETransaction on Industrial Electronics 2011; 58(8):1887–1895.

7. Xiao H. Transformerless split-inductor neutral point clamped three-level PV grid-connected inverter. IEEETransaction on Power Electronics 2012; 27(4):1799–1808.

8. Zhou Y, Li H. Analysis and suppression of leakage current in cascaded-multilevel-inverter-based PV systems. IEEETransaction on Power Electronics 2014; 29(10):5265–5277.

9. Su X, Sun Y, Lin Y. Analysis on leakage current in transformerless single-phase PV inverters connected to the grid. Pro-ceedings of the Asia-Pacific Power and Energy Engineering Conference (APPEEC), March 2011; 1–5.

10. Lopez O, Teodorescu R, Doval-Gandoy J. Multilevel transformerless topologies for single-phase grid-connectedconverters. Proceedings of the 32nd Annual Conference on IEEE Industrial Electronics, IECON 2006, Nov.2006; 5191–5196.

11. Lopez O, Freijedo F, Yepes A, et al. Eliminating ground current in a transformerless photovoltaic application. IEEETransaction on Energy Conversion 2010; 25(1):140–147.

12. Cavalcanti M, Farias A, Oliveira K, Neves F, Afonso J. Eliminating leakage currents in neutral point clampedinverters for photovoltaic systems. IEEE Transaction on Industrial Electronics 2012; 59(1):435–443.

13. Cavalcanti M, Oliveira K, de Farias A, Neves F, Azevedo G, Camboim F. Modulation techniques to eliminateleakage currents in transformerless three-phase photovoltaic systems. IEEE Transaction on Industrial Electronics2012; 57(4):1360–1368.

14. Guo X, Cavalcanti M, Farias A, Guerrero J. Single-carrier modulation for neutral-point-clamped inverters in three-phase transformerless photovoltaic systems. IEEE Transaction on Power Electronics 2013; 28(6):2635–2637.

15. Kerekes T, Teodorescu R, Rodriguez P, Vazquez G, Aldabas E. A new high-efficiency single-phase transformerlessPV inverter topology. IEEE Transaction on Industrial Electronics 2011; 58(1):184–191.

16. Gonzalez R, Lopez J, Sanchis P, Marroyo L. Transformerless inverter for single-phase photovoltaic systems. IEEETransaction on Power Electronics 2007; 22(2):693–697.

17. Xiao H, Xie S. Leakage current analytical model and application in single-phase transformerless photovoltaic grid-connected inverter. IEEE Transaction on Electromagnetic Compatibility 2010; 52(4):902–913.

18. Burger B, Kranzer D. Extreme high efficiency PV-power converters. Proceedings of the 13th European Conferenceon Power Electronics and Applications, EPE 2009, Sept. 2009; 1–13.

19. Araujo S, Zacharias P, Mallwitz R. Highly efficient single-phase transformerless inverters for grid-connectedphotovoltaic systems. IEEE Transaction on Industrial Electronics 2010; 57(9):3118–3128.

20. Wang Y, Li R, Cai X. Novel high efficiency 3 level stacked neutral point clamped grid tied inverter. IEEETransaction on Industrial Electronics 2013; 60(9):3766–3774.

21. Barater D, Buticchi G, Crinto AS, Franceschini G, Lorenzani E. Unipolar PWM strategy for transformerless PVgrid-connected converters. IEEE Transaction on Energy Conversion 2012; 27(4):835–843.

22. Gu B, Dominic J, Lai J, Chen C, Chen B. High reliability and efficiency single-phase transformerless inverter forgrid-connected photovoltaic systems. IEEE Transaction on Power Electronics 2013; 28(5):2235–2245.

23. Sang Z, Mao C, Wang D. Staircase control of hybrid cascaded multi-level inverter. Electric Power Components andSystems 2014; 42(1):23–34.

24. Ji B, Wang J, Zhao J. High efficiency single phase transformerless pv H6 inverter with hybrid modulation method.IEEE Transaction on Industrial Electronics 2013; 60(5):2104–2115.

25. San G, Qi H, Wu J, Guo X. A new three-level six-switch topology for transformerless photovoltaic systems.Proceedings of the 7nd International Power Electronics and Motion Control Conference, IPEMC 2012, vol. 1, June2012; 163–166.

26. Ali S, Jain P, Bakhshai A. Cascaded multilevel converters and their applications in photovoltaic systems. 2ndCanadian Solar Building Conference, 2007, June 2007.

27. Tamilvani P, Valluvan K. Hybrid modulation technique for cascaded multilevel inverter for high power and highquality applications in renewable energy systems. International Journal of Electronic and Electrical Engineering2012; 5(1):59–68.

28. Chavarria J, Biel D, Guinjoan F, Meza C, Negroni JJ. Energy-balance control of PV cascaded multilevel grid-connected inverters under level-shifted and phase-shifted PWMs. IEEE Transaction on Industrial Electronics2013; 60(1):98–111.

29. Vazquez G, Martinez-Rodriguez PR, Sosa JM, Escobar G, Arau J. A modulation strategy for single-phase HB-CMIto reduce leakage ground current in transformer-less PV applications. Proceedings of the 39nd Annual Conferenceon IEEE Industrial Electronics, IECON 2013, Nov. 2013; 210–215.



30. Gubía E, Sanchis P, Ursúa A, López J, Marroyo L. Ground currents in single-phase transformerless photovoltaic sys-tems. Progress in Photovoltaics: Research and Applications 2007; 15(15):629–650.

31. Lopez O, Teodorescu R, Freijedo F, Dovalgandoy J. Leakage current of a single-phase transformerless pv inverterconnected to the grid. Proceedings of the 20nd Annual IEEE Applied Power Electronics Conference and Exposition,(APPEEC), March 2007; 907–912.

32. DKE deustche kommission elektrotechnik elektronik informationstechnik im din und vde 0126-1-1, 2005, 2005.33. Kumar KA, Eichner J. Guidance on proper residual current device selection for solar inverters. Schneider Electric

White Paper 2010; 1:1–5.34. Gupta A, Khambadkone AM. A general space vector PWM algorithm for multilevel inverters, including operation

in overmodulation range. IEEE Transaction on Power Electronics 2007; 22(2):517–526.35. Ganesh J, Ramesh K. Design and simulation of cascaded H-bridge multilevel inverter based DSTATCOM.

International Journal of Engineering Trends and Technology 2012; 3(1):2231–5381.



a pwm method for single-phase cascade multilevel inverters

Documents