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EC 2257 ELECTRONICS CIRCUITS II AND SIMULATION LAB

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KONGUNADU COLLEGE OF ENGINEERING AND TECHNOLOGY

Department of ECE

Vision of the Collee!

TO be a home of utmost excellence in technical education and build full

fledged engineers with good caliber,discipline,right skills and providing

plentiful career opportunities to make them assests for the community and to

the country.

"ission of the Collee!

o To inculcate high moral and professional excellence among our

students with careful phychological approach to make thememerge as successful academic personalities and face global

changes.

o To become a preferred destination for learners by the attraction

of developing resources, infrastructure and feel good

atmosphere, in addition to necessary requirements.

o To impart transformative education, providing intensive training

by intellectuals, skill full leaders and global citizens effective and

efficient in various fields of life.

o To uphold industry institute interaction by way of collaboration

with industries, research and development centers with an aim toserve the nation.

Vision of ECE Department!

o To develop the department into a full fledged center of learning and

to enhance the Professional Technologist for a ealistic !nvironment

"ission of ECE Department!

o To prepare graduates for professional careers and lifelong learning, to

promote the creation and dissemination of knowledge, to serve

society through professional practice and community outreach, and

to act as a catalyst for economic and technological development of

the "ation.

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LI#T OF E$%ERI"ENT#

Design of following circuits1. Series and Shunt feedback amplifiers:

Frequency response, Input and output impedance calculation

2. RC hase shift oscillator, !ien "rid#e $scillator

%. &artley $scillator, Colpitts $scillator

'. (uned Class C )mplifier

*. Inte#rators, +ifferentiators, Clippers and Clampers

. )stable, -onostable and "istable multiibrators

SIMULATION USIN !S!ICE"

/. +ifferential amplifier

0. )ctie filters : "utterorth 2ndorder F, &F 3-a#nitude 4 hase Response5

6. )stable, -onostable and "istable multiibrator 7 (ransistor bias

18. +9) and )9+ conerters 3Successie approimation5

11. )nalo# multiplier

12. C-$S Inerter, ;);+ and ;$R

LAB SYLLABUS

EC 2257 -ELECTRONICS CIRCUITS II AND SIMULATION LAB

YEARE" ! II& IV 'RANCH! ECE

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EC2257-ELECTRONICS CIRCUITS II AND SIMULATION LAB

YEAR& #E" ! II& IV 'RANCH ! ECE

List of Experiments:

#. "o Title Page "o$arks

obtained

#ignature

I CYCLE

%.Design of current Series amplifiers

&. Design of voltage shunt Series amplifiers:'.

( Phase shift oscillator

). *ien +ridge Oscillator

.-artley Oscillator

.(olpitts Oscillator

/. Tuned (lass ( 0mplifier

II CYCLE

1.2ntegrators, 3ifferentiators, (lippers and(lampers

4.0stable, $onostable and +istablemultivibrators

%5.

#2$670T2O" 6#2"8 P#P2(!93ifferential amplifier,0ctive filters 9+utterworth &ndorder 7P:, -P: ;$agnitude

< Phase esponse=

%%.0stable, $onostable and +istablemultivibrator > Transistor bias

%&.3?0 and 0?3 converters ;#uccessiveapproximation=

%'.0nalog multiplier, ($O# 2nverter, "0"3and "O

Expt No: 1 CURRENT-SERIES FEEDBACK AMPLIFIER

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Aim:

To design and test the current-series feedback amplifier and to calculate thefollowing parameters with and without feedback.

. !id band gain.

". #andwidth and cut-off fre$uencies.

%. &nput and output impedance.

Compo!t" # E$%ipm!t &!$%i&!':

S() No) Compo!t" * E$%ipm!tR+,! *

-%+tit.Sp!/i0i/+tio"

'ower suppl( )*-%*+,

" unction generator )*-"*!+/

% 012

3 Transistor #0*4

5 1esistors

6 0apacitors4 0onnecting wires 7ccordingl(

Ci&/%it 'i+,&+m:

i 3it4o%t 0!!'+/6:

Vcc = +12V

R1

RC

Cout

CCin

" "C18/R

CRO

)hie

? 1E+ ;

Desensitivit( factor8 D ; ? Cm;

Transconductance with feedback8 Cmf; Cm> D ;

&nput impedance with feedback8 Bif; BiD

2utput impedance with feedback8 B*f; B*D

P&o/!'%&!:

. 0onnect the circuit as per the circuit diagram.

". =eeping the input voltage constant8 var( the fre$uenc( from 5*/ to %!/ inregular steps and note down the corresponding output voltage.

%. 'lot the graph: Cain )d#+ ,s re$uenc(3. 0alculate the bandwidth from the graph.

5. 0alculate the input and output impedance.

6. 1emove Emitter 0apacitance8 and follow the same procedures ) to 5+.

3

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T+%(+& /o(%m:

i 3it4o%t 0!!'+/6:

,i ;

Sl. o re$uenc( 2utput ,oltage Cain ; ,*>,iCain ; "* log),*>,i+

)/+ ),*+ )volts+ )d#+

ii 3it4 0!!'+/6:

,i ;

Sl. o re$uenc( 2utput ,oltage Cain ; ,*>,iCain ; "* log),*>,i+

)/+ ),*+ )volts+ )d#+

Mo'!( ,&+p4: 0&!$%!/. &!"po"!

9+i i 'B

ithout feedback

ith feedback

re$uenc( in /

R!"%(t:

Thus the current series feedback amplifier is designed and constructed and thefollowing parameters are calculated.

Theoretical 'ractical

ith feedback ithout feedback ith feedback ithout feedback

&nputimpedance

2utputimpedance

Cain)midband+#andwidth

5

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Expt) No) 2 OLTA9E S;UNT FEEDBACK AMPLIFIER

Aim:

To design and test the voltage-shunt feedback amplifier and to calculate thefollowing parameters with and without feedback.

. !id band gain.

". #andwidth and cut-off fre$uencies.%. &nput and output impedance.






% 012

3 Transistor #0*4 5 1esistors

6 0apacitors

4 0onnecting wires

Ci&/%it Di+,&+m:

i 3it4o%t F!!'+/6:

Vcc = +12V

R1 RC

Cout

CCin

" "C18/

< CRO

Vin=50mV

f=(1-3M)Hz R2 R &0; "6" )transistor 7ctive+

; ,E; &E1E; ,cc>* ;

4

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7ppl(ing =,L to output loop8 we get ,00; &010? ,0E? &E1E

10;

Since is ver( small when compare with &08 &0&E

1E; ,E> &E;

S ; ? 1#> 1E

1#;

,#; ,001"> )1? 1"+

1#; 1@@ 1"

1; 1";

ii 3it4 0!!'+/6:

12; 10@@ 1f;

1i; )1#@@ hie+ 1f;

1m; -)hfe)1#@@ 1f+ )10@@ 1f++ > ))1#@@ 1f+ ? hie+ ;

Desensitivit( factor8 D ; ? 1m

1if; 1i> D ;

1of; 1o> D ;

1mf; 1m> D ;

A0i; 1if>* ;

0i; > )"f A0i+ ;

Aco; 1of>* ;

0o; > )"f A0o+ ;

1E; 1E@@ ))1#? hie+ > )?hfe++

A0E; 1E>* ;

0E; > )"f A0E+ ;

A0f; 1f>*

0f; > )"f A0f+ ;P&o/!'%&!:


". =eeping the input voltage constant8 var( the fre$uenc( from 5*/ to %!/ inregular steps and note down the corresponding output voltage.

%. 'lot the graph: Cain )d#+ ,s re$uenc(

F

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3. 0alculate the bandwidth from the graph.

5. 0alculate the input and output impedance.

6. 1emove Emitter 0apacitance8 and follow the same procedures ) to 5+.

T+%(+& Co(%m:

i 3it4o%t F!!'+/6:

,i ; * m,

F&!$%!/. < 9+i =

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Expt) No) > RC P;ASE S;IFT OSCILLATOR

Aim:

To design and construct a 10 phase shift oscillator for the given fre$uenc( )f*+.






% 012

3 Transistor #0*4

5 1esistors

6 0apacitors

4 0onnecting wires 7ccordingl(

Ci&/%it Di+,&+m:

Vcc = +12V

R1 RC

Cout

CCin

" "C18/

< RCRO

R2 R &0; "6" )transistor 7ctive+

; ,E; &E1E; ,cc>*

7ppl(ing =,L to output loop8 we get

,00; &010? ,0E? &E1E

10;

Since is ver( small when compare with &08

&0&E

1E; ,E> &E;

S ; ? 1#> 1E; "

1#;

,#; ,#E? ,E;

,#; ,001"> )1? 1"+

1#; 1@@ 1"

1; 1";

Cain formula is given b(8

7,;

h fe

1 Leff )7v; -"G8 design given+

hie

Effective load resistance is given b(8 1leff ; 1c @@ 1L

1L;

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A0i; MNhie?)?hfe+1EO @@ 1#P>* ;

0i; > )"f A0i+ ;

Aco; 1leff>* ;

0o; > )"f A0o+ ;

A0E; 1E>* ;

0E; > )"f A0E+ ;

F!!'+/6 N!t?o&6:

f*; < 0 ; *.*f<

fo;

"610 1 ;

P&o/!'%&!:

. 0onnections are made as per the circuit diagram.". Switch on the power suppl( and observe the output on the 012 )sine wave+.

%. ote down the practical fre$uenc( and compare with its theoretical fre$uenc(.

Mo'!( 9&+p4:

,out ),oltage+

Time)ms+

R!"%(t:

Thus 10 phase shift oscillator is designed and constructed and the output sinewave fre$uenc( is calculated as

T4!o&!ti/+( P&+/ti/+(

F&!$%!/.

"

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Expt) No)@ ;ARTELY OSCILLATOR

Aim:

To design and construct the given oscillator for the given fre$uenc( )f2+)

Compo!t" # E$%ipm!t &!$%i&!':S() No) Compo!t" * E$%ipm!t

R+,! *-%+tit.

Sp!/i0i/+tio"



% 012

3 Transistor #0*4

5 1esistors

6 0apacitors

4 D

F D0#

G 0onnecting wires 7ccordingl(

Ci&/%it Di+,&+m:

Vcc = +12V

R1 RC

Cout

CCin

"

"C18/CRO

&0; "6" )transistor 7ctive+

; ,E; &E1E; ,cc>*


,00; &010? ,0E? &E1E

10;

Since is ver( small when compare with &08 &0&E

1E; ,E> &E;

S ; ? 1#> 1E; "

1#;

,#; ,#E? ,E;

,#; ,001"> )1? 1"+

1#; 1@@ 1"

1; 1";

Cain formula is given b(8

7,;

h fe

1 Leff )7v; -"G8 design given+

hie

Effective load resistance is given b(8 1leff ; 1c @@ 1L

1L;


0i; > )"f A0i+ ;

Aco; 1leff>* ;

3

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0o; > )"f A0o+ ;

A0E; 1E>* ;

0E; > )"f A0E+ ;

F!!'+/6 N!t?o&6:

f*; < L; m< L"; *m

7 ; ; L

L "

f ;

" (L+L")0

0 ;

P&o/!'%&!:

. 0onnections are made as per the circuit diagram.". Switch on the power suppl( and observe the output on the 012 )sine wave+.

%. ote down the practical fre$uenc( and compare with its theoretical fre$uenc(.

Mo'!( 9&+p4:

,out ),oltage+

Time)ms+

R!"%(t:Thus artle( oscillator is designed and constructed and the output sine wave

fre$uenc( is calculated as

Theoretical 'ractical

re$uenc(

5

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Expt) No)5 COLPITTS OSCILLATOR

Aim: To design and construct the given oscillator at the given operating fre$uenc( )

E$%ipm!t" &!$%i&!':





% 012

3 Transistor #0*4

5 1esistors

6 0apacitors

4 D

F D0#

G 0onnecting wires

Ci&/%it Di+,&+m:

Vcc =

R1 RC

Cout

Cin

C

"

"C18/CRO

%

Vin1=

1 SR ? 188@

+

>'

%=

Vin2 S

iii NOR

VDD = +5V

%

Vin1 1 = S

>1 +

2 = SVin2 >2

+' Vout

+ +>% >'

= = R ? 188@S S

"*

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T4!o&.:

i I!&t!&

0!2S is widel( used in digital &0s because of their high speed8 low powerdissipation and it can be operated at high voltages resulting in improved noise immunit(.

The inverter consists of two !2SETs. The source of p-channel device is connected to?,DD and that of n-channel device is connected to ground. The gates of two devices areconnected as common input.

ii NAND

&t consists of two p-channel !2SETs connected in parallel and two n-channel!2SETs connected in series. '-channel !2SET is 2 when gate is negative and -channel !2SET is 2 when gate is positive. Thus when both input is low and wheneither of input is low8 the output is high.

iii NOR

&t consists of two p-channel !2SETs connected in series and two n-channel!2SETs connected in parallel. '-channel !2SET is 2 when gate is negative and-channel !2SET is 2 when gate is positive. Thus when both inputs are high andwhen either of input is high8 the output is low. hen both the inputs are low8 the outputis high.

T&%t4 T+(!:

i I!&t!&

&nput 2utput

*

*

ii NAND

, ," 2utput

* *

*

*

*

iii NOR

, ," 2utput

* *

* *

* *

*

"

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Mo'!( 9&+p4:

i I!&t!&

,oltage

&nput aveform5,

time )s+* * "* %* 3* 5* 6* 4* F*

2utput aveform

5,

time )s+* * "* %* 3*

ii NAND

,oltage

&nput aveform

* * "* %* 3*

2utput aveform

5* 6* 4* F*

time )s+5* 6* 4* F*

time )s+ * * "* %* 3* 5* 6* 4* F*

time )s+* * "* %* 3* 5* 6* 4* F*

&&

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1iii2 NOR

,oltage

&nput aveform

time )s+

* * "* %* 3* 5* 6* 4*

2utput aveform

* * "* %* 3* 5* 6* 4* F* time )s+

time )s+

* * "* %* 3* 5* 6* 4* F*

O%tp%t:

i I!&t!&

Cain ; ,)"+>,in ;

&nput 1esistance at ,in ;2utput 1esistance at ,)"+ ;

ii NAND

Cain ; ,)3+>,in ; ,)3+>,in" ;&nput 1esistance at ,in ;

&nput 1esistance at ,in" ;

2utput 1esistance at ,)3+ ;

iii NOR

Cain ; ,)3+>,in ; ,)3+>,in" ;

&nput 1esistance at ,in ;&nput 1esistance at ,in" ;

2utput 1esistance at ,)3+ ;

R!"%(t:

Thus the transient characteristics of output voltage for the given 0!2S inverter87D and 21 is plotted and the voltage gain8 input impedance and outputimpedance are calculated.

"%

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Expt) No)7 SECOND ORDER BUTTER3ORT; - LO3 PASS FILTER

Aim:

To design and implement the second order butterworth Low pass filterusing 'S'&0E.

Ci&/%it Di+,&+m:

RI; 1@ RF *0, ohm2

8 V+

2

/

R1 R2

-

A$B(

* %

% +

1 -/'1

'

1.*6@ 1.*6@

R

V-

AI; C2 8.1u 18@C1 8.1u

1V

3188 7 18@5&

8

T4!o&.:

7 Low pass filter has a constant gain from * to f. ence the bandwidth of thefilter is f. The range of fre$uenc( from * to f is called pass band. The range offre$uencies be(ond fis completel( attenuated and it is called as stop band.

D!"i,:

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f; ***B 0; 0" ;*. 1&;***

f; > "10

1 ; > "0f

1 ; 1; 1"; 5G"

"3

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Cain ; .5F6

.5F6 ; ? )1> 1&+

1; 5F6

Mo'!( 9&+p4:

Cain )d#+

%d#

re$uenc( )B+

f

R!"%(t:

Thus Low pass filter is designed and implemented using 'S'&0E.

"5

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Expt) No) DIFFERENTIAL AMPLIFIER

Aim:

To implement the differential amplifier using 'S'&0E.

Ci&/%it Di+,&+m:

RF 18@

V+

1RI; 18@

2 /VIN 2- ,-/'1% Vout+

VIN * R2 18@ % '

RC$- V-18@

T4!o&.:

7 differential amplifier amplifies the difference between two voltages ,and

,". The output of the differential amplifier is dependent on the difference between twosignals and the common mode signal since it finds the difference between two inputs itcan be used as a subtractor. The output of differential amplifier is

1

,2; ),"Q ,+

1

"6

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Mo'!( 9&+p4:

,oltage

, time

,"

time

,%

time

C+(/%(+tio:

, ; 5, ," ; *,

1 *=

,2; ),"Q ,+ ; )* Q 5+

1 *=

,2

; 5,

O%tp%t:

,2; 5,

R!"%(t:Thus a differential amplifier is implemented using operational amplifier.

"4

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Expt) No) FREUENCY RESPONSE OF SIN9LE TUNED AMPLIFIER

Aim:

To design and construct a single tuned amplifier and to plot the fre$uenc(response.

E$%ipm!t R!$%i&!':





% 012

3 Transistor #0*4

5 1esistors

6 0apacitors

4 DF D0#

G 0onnecting wires

Ci&/%it Di+,&+m:

VCC = +10V

R1 C

Cout

CinC

"

"C18/

< R

R2CR$

A?*8mAR" )transistor 7ctive+

; ,E; &E1E; ,cc>*


,00; &010? ,0E? &E1E

10;

Since is ver( small when compare with &08 &0

&E1E; ,E> &E;S ; ? 1#> 1E;

" 1#;

,#; ,#E? ,E;

,#; ,001"> )1? 1"+

1#; 1@@ 1"

1; 1";

1L;


0i; > )"f A0i+ ;

Aco; )10@@1L+ >* ;

0o; > )"f A0o+ ;

A0E; 1E>* ;

0E; > )"f A0E+ ;

R ; 1L> L

1L;

f*;

" LC

0 ;

"G

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P&o/!'%&!:

. 0onnect the circuit as per the circuit diagram.". Set ,i ; 5* m, )sa(+8 using the signal generator.

%. =eeping the input voltage constant8 var( the fre$uenc( from */ to%!/ inregular steps and note down the corresponding output voltage.

3. 'lot the graph: Cain )d#+ ,s re$uenc(

T+%(+& Co(%m:

i = 5< m

F&!$%!/.

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Expt) No)1< ASTABLE MULTIIBRATOR

Aim:

To design and construct an astable multivibrator using transistor and to plot theoutput waveform.

Compo!t" * E$%ipm!t" R!$%i&!':

Sl. o. &tem name1ange >

Ruantit(Specification

Transistor #0*4 "

" 1esistors 3.G=8 .6! " each% 0apacitors *.35n "

3 012 )*-"*!+/

5 'ower Suppl( )*-%*+, 6 0onnecting ires 7ccordingl(

Ci&/%it Di+,&+m:

Vcc = +12V

RC R R RC5.! 1.5M 1.5M 5.!

Vo1C

CVo20."#n$

C0."#n$

"C18/ "C

"C18/

).%F1+ ; ) *-%

+ > ).%F .5 *6+; *.3Fn

P&o/!'%&!:

. 0onnections are made as per the circuit diagram.

". Switch on the power suppl(.

%. ote down the output T28 T2and output voltage from 012.3. 'lot the output waveform in the graph.

T+%(+& Co(%m:

7mplitude T2 T2 re$uenc()in volts+ )ms+ )ms+ )in /+

,o

,o"

%"

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Mo'!( 9&+p4:

,o ),olts+

Time )ms+

,o" ),olts+

Time )ms+

RESULT:

Thus the astable multivibrator is designed and constructed using transistor and itsoutput waveform is plotted.

%%

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Expt) No)11 MONOSTABLE MULTIIBRATOR

Aim:

To design and construct monostable multivibrator using transistor and to plotthe output waveform.


Sl. Do. &tem name 1ange > Specification Ruantit(

Transistor #0*4 "


3 012 )*-"*!+/

5 'ower Suppl( )*-%*+,

6 0onnecting ires 7ccordingl(

Ci&/%it Di+,&+m:VCC = +12V

RC*.6@

RC R

*.6@ 1.1%- 18@ R1

+1Ao1 C

C1

1;'88/ 1.20nF Ao22*nF

CC

"

" "C18/"C18/

hfe;

Select " ")min+

";

,00Q ,#E)sat+

1 ; ;

& #"

T ; *.6G10

0 ; T > *.6G1 ;

-,##1 ,0E)sat+ 1"

,#; ?1? 1" 1? 1"

,##1 ,0E)sat+ 1"

; )since8 , #is ver( less+

1? 1" 1? 1"

,##1 ; ,0E)sat+ 1"

1";*1

)since8 ,

##; ", and ,

0E)sat+ ; *.",+

Let 1; *=8 then 1"; **=

0hoose 0; "5p.

P&o/!'%&!:

. 0onnections are made as per the circuit diagram.". Switch on the power suppl(.

%5

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%. 2bserve the output at collector terminals.

3. Trigger !onostable with pulse and note down the output T28 T2 andvoltage from 012.

5. 'lot the waveform in the graph.

T+%(+& Co(%m:

idth &nput 2utput

)ms+ T2 T2 ,oltage T2 T2 ,oltage)ms+ )ms+ ),olts+ )ms+ )ms+ ),olts+

Mo'!( 9&+p4:

,o ),olts+

Time )ms+

,o" ),olts+

Time )ms+

R!"%(t:

Thus the monostable multivibrator is designed and constructed usingtransistor and its output waveform is plotted.

%6

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Expt) No)12 BISTABLE MULTIIBRATOR

Aim:

To design a bistable multivibrator and to plot its output waveform.


Sl. Do. &tem name 1ange > Specification Ruantit(

Transistor #0*4 "


3 012 )*-"*!+/

5 'ower Suppl( )*-%*+,

6 0onnecting ires 7ccordingl(

Ci&/%it Di+,&+m:

VCC = +10V

RC&u' *i,,

RC

5.! (V* VCC) 5.!

+1 1;'88/ 1;'88/ +2

C 50$ C 50$

Vo1R1 10! R1 10!

Vo2

CC "

"C18/"C18/

"

**= 3 0apacitor *. 5 0onnecting wires 7ccordingl(

Ci&/%it Di+,&+m:

i Di00!&!ti+to&:

C

8.1uF

Vin=5V R

f= 1!Hz 1@9 CRO188@

ii It!,&+to&:

8

R 1@9 188@

Vin=5V

f= 1!Hz C8.1uF CRO

8

3*

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)iii+ 0lipper:

)a+ Series 'ositive 0lipper:

D

1;'88/Ain?*A Rf=1!Hz 10!

CRO

S4%t Po"iti! C(ipp!&:

R 10!

Ain?*A D

f=1!Hz

)c+ Series egative 0lipper:

8

1;'88/

8

CRO

D

1;'88/

Ain?*A Rf=1!Hz 10!

8

' S4%t N!,+ti! C(ipp!&:

R 10!

Ain?*A D

f=1!Hz

1;'88/

8

3

CRO

CRO

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! Po"iti! Bi+"!' S!&i!" Po"iti! C(ipp!&:

D

1;'88/R

10!CRO

Ain?*A

f=1!Hz V%

2A

8

)f+ 'ositive #iased Shunt 'ositive 0lipper:

R 10!

D1;'88/

Ain?*Af=1!Hz V%

2A

8

, Po"iti! Bi+"!' S!&i!" N!,+ti! C(ipp!&:

D

1;'88/R

10!

Ain?*Af=1!Hz V%

2A

8

3"

CRO

CRO

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)h+ 'ositive #iased Shunt egative 0lipper:

R 10!

1;'88/ D

Ain?*A

f=1!Hz V%

2A

8

)i+ egative #iased Series 'ositive 0lipper:

D

1;'88/

R

10!

Ain?*A

V%f=1!Hz

2A

8

)+ egative #iased Shunt 'ositive 0lipper:

R 10!

D

1;'88/

Ain?*Af=1!Hz V%

2A

8

3%

CRO

CRO

CRO

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)k+ egative #iased Series egative 0lipper:

D

1;'88/

R

Ain?*A10! CRO

f=1!Hz

V%

2A

8)l+ egative #iased Shunt egative 0lipper:

R 10!

D

1;'88/

Ain?*ACRO

f=1!Hz V%

2A

8

m Comi+tio+( C(ipp!&

R 10!

D D

1;'88/ 1;'88/

Ain?*A CRO

f=1!HzV%

V%

2A2A

8

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33

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)iv+ 0lamper:

+ Po"iti! C(+mp!&:

C

8.1uF

Ain?*A DR

1;'88/ 10!f=1!Hz

8 N!,+ti! C(+mp!&:

C

8.1uF

Ain?*AD R

1;'88/ 10!f=1!Hz

8

T4!o&.:

i Di00!&!ti+to&:

CRO

CRO

The high pass 10 network acts as a differentiator whose output voltagedepends upon the differential of input voltage. &ts output voltage of the differentiatorcan be expressed as8

d

,out ; ,in dt

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ii It!,&+to&:

The low pass 10 network acts as an integrator whose output voltagedepends upon the integration of input voltage. &ts output voltage of the integratorcan be expressed as8

,out ; ,in dt

iii C(ipp!&:

This circuit is basicall( a rectifier circuit8 which clips the input waveformaccording to the re$uired specification. The diode acts as a clipper. There are severalclippers like positive clipper8 negative clipper8 etc. Depending upon the connection ofdiode it can be classified as series and shunt.

i C(+mp!&:

The clamper circuit is a t(pe of wave shaping circuit in which the D0 level ofthe input signal is altered. The D0 voltage is varied accordingl( and it is classified aspositive clamper or negative clamper accordingl(.

D!"i,:

i Di00!&!ti+to&:

f ; =/

; 10 ; ms &f0 ; *. Then

1 ; *=

or T UU 8 0hoose 1 ; =andor T 8 0hoose 1 ; **=

ii It!,&+to&:

f ; =/

; 10 ; ms &f0 ; *. Then1 ; *=

or T UU 8 0hoose 1 ; =andor T 8 0hoose 1 ; **=

P&o/!'%&!:


". Set ,in ; 5, and f ; =/.%. 2bserve the 2utput waveform and plot the graph.

36

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Mo'!( 9&+p4:

i Di00!&!ti+to&

,in ),olts+

Time )ms+

,out ),olts+

Time )ms+

Time )ms+

ii It!,&+to&

,in ),olts+

Time )ms+

,out ),olts+

Time )ms+

Time )ms+

34

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iii C(ipp!&:

,in ),olts+

Time )ms+

,out ),olts+

Series 'ositive 0lipper

Time )ms+

Shunt 'ositive 0lipper

Time )ms+

Series egative 0lipper

Time )ms+

Shunt egative 0lipper

Time )ms+

'ositive #iased Series 'ositive 0lipper

",Time )ms+

3F

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'ositive #iased Shunt 'ositive 0lipper

",Time )ms+

'ositive #iased Series egative 0lipper

",

Time )ms+

'ositive #iased Shunt egative 0lipper

",

Time )ms+

egative #iased Series 'ositive 0lipper

Time

)ms+ -",

egative #iased Shunt 'ositive 0lipper

Time

)ms+ -",

egative #iased Series egative 0lipper

Time )ms+

-",

3G

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egative #iased Shunt egative 0lipper

Time )ms+

-",

0ombinational 0lipper

",

Time )ms+

-",

i C(+mp!&:

'ositive 0lamper:

Time )ms+

egative 0lamper:

Time )ms+

R!"%(t:

Thus different wave shaping circuits are studied and their output waveformsare plotted.

5*

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EPT NO)1@ DI9ITAL TO ANALO9 CONERTER

R 2R LADDER TYPE

Aim:

To construct a F Q bit digital to analog converter using 1 Q "1 ladder t(pe.

Ci&/%it Di+,&+m:

28@

V+

18@ 18@ 18@ /' -

1 2 % VO/*-/'1*

+28@

28@ 28@ 28@ 0

V-

88

8 8 8

6-10V

T4!o&.:

7 D70 accepts an n Q bit input word b8 b"8 VV8 bn in binar( and produces ananalog signal that is proportional to the input. &n this t(pe of D708 reference voltage isapplied to one switch and the other switches are grounded. &t is easier to build andnumber of bits can be expanded b( adding more 1 Q "1 sections. The circuit slow downdue to stra( capacitance.

O"!&+tio:

d )!S#+ d" d% )LS#+2utput ,oltage

,2),olts+

* * * *

* * ."5* * ".5

* %.45

* * 5

* 6."5

* 4.5

F.45

5

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C+(/%(+tio:

2utput ,oltage8 ,2; ,1)d"-

? d""-"

? d%"-%

+

or **8 ,2; 5,

2utput:

,2; 5,

Mo'!( 9&+p4:

,oltage

5,

time

R!"%(t:

Thus 1 Q "1 ladder t(pe digital to analog converter is implemented.

5"

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EPT NO)15 ASTABLE MULTIIBRATOR

Aim:

To plot the transient response of voltages at collector terminals of the twotransistors R and R". &nitial node voltages at collector and base are /ero.

Ci&/%it Di+,&+m:

VCC = +10V

*

R2 R1 R% R''.6@ 0*8@ 0*8@ '.6@

C1 C2

2

% 1

'

Ao1 Ao2

8.6nF 8.6nF

C

C" >2

">1 "C18/

"C18/

80524554 ec ii lab manual

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