2006 - reliability of interface under accelerated temperature cycling (1)

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Reliability study of underll/chip interface underaccelerated temperature cycling (ATC) loading

Y.L. Zhang a , D.X.Q. Shi b, *, W. Zhou a

a School of Mechanical and Production Engineering, Nanyang Technological University, 50 Nanyang Avenue,Singapore 639798, Singapore

b Singapore Institute of Manufacturing Technology, 71 Nanyang Drive, Singapore 638075, Singapore

Received 22 August 2004; received in revised form 28 January 2005

Available online 17 June 2005

Abstract

Interface reliability issue has become a major concern in developing ip chip assembly. The CTE mismatch betweendifferent material layers may induce severe interface delamination reliability problem. In this study, multifunctionalmicro-moire interferometry (M 3I) system was utilized to study the interfacial response of ip chip assembly under accel-erated thermal cycling (ATC) in the temperature range of 40 C to 125 C. This in-situ measurement provided goodinterpretation of interfacial behavior of delaminated ip chip assembly. Finite element analysis (FEA) was carried outby introducing viscoelastic properties of underll material. The simulation results were found to be in good agreementwith the experimental results. Interfacial fracture mechanics was used to quantify interfacial fracture toughness and

mode mixity of the underll/chip interface under the ATC loading. It was found that the interfacial toughness is notonly relative to CTE mismatch but also a function of stiffness mismatch between chip/underll. 2005 Elsevier Ltd. All rights reserved.

1. Introduction

Flip chip technology is one of the major assemblytechnologies, with which the smaller packaging can beachieved for a desired functionality. Therefore, ip chiptechnology is expected to have a rapid growth in theindustry applications in the next decade. However, largecoefficient of thermal expansion (CTE) mismatch be-tween the chip and the substrate may lead to cata-strophic thermal stresses in solder interconnects, andhence reduce life of the package. Epoxy-based underllmaterials are, therefore, introduced into ip chip assem-blies in order to reinforce the strength of increasingly

miniaturized solder interconnects [1,2]. However, duringthe manufacturing process, low adhesion due to incom-patible interfaces or under-cured underll, and void de-fects caused by trapped moisture can lead to anotherserious reliability problem, i.e., interface delamination,in the ip chip assembly [3]. It has been reported thatthe solder joint fatigue failure appeared shortly afterthe delamination happens at the interface when the ipchip assembly is subjected to thermal shock testing[4,5]. It is most likely that the crack may initiate at theunderll/chip interface and propagate into the solder joint. The propagation of interface crack will cause thefunction loss of electronic devices.

Due to the complex nature of ip chip assembly andcomplicated environmental loading, considerable limita-tions and difficulties exist in studying the interface

0026-2714/$ - see front matter 2005 Elsevier Ltd. All rights reserved.

doi:10.1016/j.microrel.2005.04.012

* Corresponding author.E-mail address: [email protected] (D.X.Q. Shi).

Microelectronics Reliability 46 (2006) 409420

www.elsevier.com/locate/microrel
mailto:[email protected]:[email protected]


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delamination problem in ip chip packages using tradi-tional strength theory. The most common method usedin industry is accelerated temperature cycling (ATC)test, which not only takes a long time and considerableresources, but also gives little insight into the failuremechanism and thus less help in the package design.Accordingly, the research emphasis has shifted stronglyto damage and fracture mechanics, which offers a funda-mental approach to the delamination problems. Briey,two categories of research work have been carried out.On the one hand, different numerical and experimentalmethodologies have been developed to characterize thefracture toughness of polymer/inorganic interface [6,7].The fracture toughness is employed as a criterion forthe interface design. On the other hand, numerical sim-ulations [4,8] and in-situ measurement [912] have beenperformed to investigate the reliability of ip chipassembly subject to different mechanical and environ-

mental loadings. However, less experimental investiga-tion has been conducted on the delamination reliabilityof polymer/inorganic interface, especially under the realATC loading due to lack of in-situ/real-time opticalmeasurement system.

In this study, an integrated multifunctional micro-moire interferometry (M 3I) system was developed tomeasure the deformation of ip chip assembly underthe ATC loading. Interfacial fracture mechanics tech-nique was employed to analyze the crack-tip displace-ment eld and further study the interfacial behavior of the delaminated chip/underll interface. Furthermore,

in order to examine the nding of M 3I system, an inter-face fracture mechanics based FEA model was devel-oped to determine the effective interfacial toughness of the assembly under the same temperature loading proleused in the moire interferometry. The simulation resultswere found to be in good agreement with the experimen-tal results. Both results showed that the interfacialtoughness is not only relative to CTE mismatch but alsoa function of stiffness mismatch between chip/underll.

2. Experimental and numerical methodologies

2.1. Moire interferometry

In this study, an integrated multifunctional micro-moire interferometry (M 3I) system was developed bycombining moire interferometry (MI) technique withphase shifting, micro-force application and measure-ment, thermoelectric heating and cooling, ultrasonichumidity excitation, and microscopic imaging tech-niques. The schematic diagram of M 3I system is shownin Fig. 1 . The system was used to investigate the inter-face reliability of ip chip assembly. With this system,displacement elds can be determined from moire fringepatterns

U x; y N x x; y

2 f ;

V x; y N y x; y

2 f ;

1

Fig. 1. Schematic diagram of M 3I system: (1) computer; (2) driver of phase shifter; (3) microscopic imaging device; (4) phase shifter; (5)moire interferometer; (6) micro-force controller; (7) micro-force amplier; (8) cooling chiller; (9) micro-force actuator; (10) six-axisadjustment xture; (11) miniature thermal cycling chamber (or miniature humidity chamber); (12) chamber support; (13) xing frame;

(14) temperature controller; (15) optical table.

410 Y.L. Zhang et al. / Microelectronics Reliability 46 (2006) 409420


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where f is the frequency of specimen grating, andN x (x, y) and N y(x, y) are the fringe orders in theU (x, y) and V (x, y) eld moire patterns, respectively. Inpractice, a specimen grating with a frequency of 1200lines/mm was used. The corresponding contour intervalin the moire fringe patterns was 417 nm/fringe.

2.2. Interface fracture mechanics

For a sandwiched system, as shown schematically inFig. 2 , its solution to plane problems of elasticity de-pends on two non-dimensional combinations of the elas-tic moduli.

With Dundurs parameters a and b dened by [13],the displacement relationships of an interface crack ata distance r behind the crack-tip are given by [14]

d y id x 8

1 2iecosh p e

K 01 i K

02

E r

2p 12 r

l ie; 2

where dx and d y are the crack-tip opening displacements(CTODs) in x and y directions, respectively; K 01 and K

02

are the nominal interface stress intensity factors (SIFs)related to the modes I and II loading congurations,respectively; r is a distance from the crack-tip; l is a char-acteristic length parameter; e is a material constant de-ned as

e 1

2pln

1 b1 b

; 3

and E * is the effective Young s modulus given by

2 E

1

E 1

1 E 2

; 4

with E i E i=1 vi for plane strain and E i E i forplane stress. By solving Eq. (2), the individual K 01 and K 02 can be obtained, the details were presented in previ-ous work [7]. Note that extrapolation method is required

to obtain K 1 and K 2 at the crack-tip based on nominalSIFs K 01 and K

02, whose details are to be illustrated in

Section 5.3. The effective interface fracture toughnessK and mode mixity w is therefore determined by [15]

K eff

ffiffiffiffiffiffiffiffiffi K 21 K

22

q ; 5

w tan 1Im Kl ieRe Kl ie b60. 6

3. Experimental details

3.1. Flip chip assembly

Flip chip assembly studied was shown in Fig. 3 (a). Inorder to simplify the study, the solder joints were re-moved since a pre-crack was of difficulty to be prepared

at the chip/underll interface with solder joints existing.The attention was drawn on the interfacial delaminationbehavior between chip/underll. Since the assembly wassymmetric, only half of the assembly was studied, asshown in Fig. 3 (b). It consisted of three materials,namely, silicon chip with Si 3N 4 passivation, underlland FR-4 with solder mask on top. A commercializedepoxy based underll material supplied by Loctite

was used in this study. The composition of the materialwas 60% epoxy with 40% silica lling sizing from 1 l mto 4 l m. The glass transition temperature ( T g) of under-ll was determined to be 105 C using differential scan-ning calorimeter (DSC) [16].

A specially designed mould was employed to preparethe assembly with desired dimension, i.e., 8 mm (L) 5 mm (W) 1.8 mm (H). The thickness of underllwas determined to be 0.5 mm. In addition, the choiceof the underll thickness optimized for critical adhesionwill not result in enhanced resistance to progressive deb-onding under the temperature cycling load used in thisstudy [17]. In order to measure the interface toughness,a pre-crack was prepared on the chip passivation byusing a piece of silicone rubber lm with the thicknessof 20 l m. After the curing of underll, the pre-crackwas made at the chip/underll interface with length

a = 2.7 mm, and the ligament ahead of the crack-tipw = 5.3 mm, satisfying, a, w > H + h + t, where H , h,and t are the thickness of FR-4, silicon wafer and under-ll respectively. The selection of these dimensions was toneglect edge effects on loading. Under these situations, asteady state solution was valid and the dependence of the SIFs on the crack length can be eliminated [15].

A dispenser and a curing oven were employed to pre-pare the sandwich specimen. By following ip chip pack-aging process, an optimized curing condition wasdened to be 165 C for 8 min. Due to capillary action,underll was dispensed into the gap between chip and

FR-4. When the specimen was partially cured, theFig. 2. Interface crack problem.

Y.L. Zhang et al. / Microelectronics Reliability 46 (2006) 409420 411


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rubber was quickly removed from the specimen and asharp crack was fabricated. After molding, each speci-men was carefully polished with a ne SiC paper to re-move excessive underll and to obtain the desireddimensions.

3.2. Moire test

Moire tests were conducted on the pre-cracked ipchip assembly with the M 3I system. The assembly wasloaded into the miniaturized thermal cycling chamber.A typical ATC loading was applied onto the assembly.

The ATC loading prole is shown in Fig. 4 . It had a

temperature range of 40 C to 125 C, a dwell timeof 12 min at the two extreme temperatures and a cycletime of less than 65 min. In the experiment, moire fringepatterns were recorded at different temperature steps,e.g., 40 C, 25 C, 0 C, 25 C, 50 C, 75 C, 100 Cand 125 C, as depicted in Fig. 4 . The platform plottedin the gure showed time for recording fringe patternimages. Based on the moire fringe patterns, the CTODsaround the crack-tip of the assembly can be determinedwith Eq. (1) and the facture toughness and mode mixitycan be calculated with Eqs. (5) and (6) .

4. Numerical simulation

In order to examine the ndings of M 3I system, aFEA model was established to determine the deforma-tion of the assembly with the same specimen structure,

dimensions and temperature loading prole used in themoire experiment.

4.1. Materials properties

Since the epoxy-based underll exhibits viscous nat-ure, especially when the temperature is around or aboveT g, timetemperature-dependent material properties cangreatly affect the response of ip chip assembly structure[11]. The viscoelastic material model, which was estab-lished in our previous works [18,19], was employed todescribe the deformation behavior of the underll

material

Fig. 4. Schematic illustration of temperature prole used in theATC test.

Fig. 3. Schematic diagram of the assembly to be studied: (a) ip chip assembly and (b) simplied ip chip assembly.



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E t E 0 X I

i1 E iet =sR i E T t ; 7

where E (t) is the relaxation modulus, I is the number of the Maxwell elements, sR i is the relaxation time relatedto the i th Maxwell element, E T (t) is the tangent modu-lus, dened as E T (t) = d r (t)/d e(t), which is non-strain-rate related.

The input data were obtained according to algorithmprovided by ANSYS, as listed in Table 1 , where H is theactivation energy and R is the ideal gas constant. Mean-while, silicon chip and FR-4 were modeled as tempera-ture-dependent elastic materials. The details are listedin Table 2 .

4.2. Modeling

A commercial FE software, ANSYS version 6.1, was

employed and a 3D nite element model was built to

simulate the package under the ATC test. The assemblywithout llet was modeled with the same dimensions de-picted in Fig. 3 (b). Visco89 elements were used to simu-late the assembly with imperfect underll, as shown inFig. 5 (a). A zoomed-in area around the crack-tip wasshown in Fig. 5 (b). The smallest mesh size around the

crack-tip was 2.5 l m. FR-4 and silicon chip were

Table 1Viscoelastic parameters for underll material

Parameters Value Parameters Value

H/R 15644 C 1 0.264CTE (ppm/ C) Below T g T -dependent C 2 0.2

Above T g 110 C 3 0.536G xy (0) (MPa) 1691.7 k1 0.198G xy (1 ) (MPa) 23.3 k2 451K (0) (MPa) 4500 k3 30435K (1 ) (MPa) 62

Table 2Material properties for chip and FR-4

Young s modulus (GPa) CTE (ppm/ C) Poisson s ratio

Silicon chip 132.46 0.00954 T 2.113 + 0.00235 T 0.28FR-4 In-plane 24.422 0.0226 T 17.6 0.11

Out-of-plane 10.562 0.00957 T 24 0.39

Fig. 5. Finite element model: (a) 3D mesh of sandwich specimen ( z = 0.5 mm) and (b) Mesh zoomed-in at crack front.



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modelled as 20-node hexahedron solid95 elements withtemperature-dependent properties. Totally, the 3D mod-el had 22,335 elements and 96,800 nodes.

5. Results and discussion

5.1. Moire fringe patterns under ATC test

Fig. 6 showed typical U and V eld moire fringe pat-terns around the crack-tip obtained from different tem-peratures. From the fringe patterns, the thermaldeformations at the different temperatures were calcu-lated with Eq. (1). Accordingly, the schematic deforma-tion throughout the whole temperature cycling is shownin Fig. 7 . Because of low CTE and high Young s modu-lus, silicon chip deformed the least compared to theother two materials. It can be observed that, during

the heating process, the adherent FR-4/underll struc-ture behind the crack-tip bent down. The slight loss of warpage was observed in case of dwelling at extremelyhigh 125 C. It was because of the rubbery or leatherynature of underll when the temperature was aboveT g. The coupling between silicon and FR-4 throughunderll material tended to diminish and the assemblywas in the stress-release state. However, the underllexperienced large inelastic deformation at this statedue to large CTE (110 ppm/ C), the large strain wouldalso consequently affect the interfacial reliability.

When the assembly was cooled down to room tem-perature, the structure lost warpage, but the residualwarpage remained in the assembly due to viscoelasticitynature of underll at high temperature, especially at thetemperature loading higher than T g of underll (e.g.,125 C). When the assembly was cooled down to minustemperature, due to the CTE mismatch as well as stiff-ness mismatch between underll and FR-4, the warpageof the structure became signicant again for the part of coupled underll and FR-4 component and the magni-tude of warpage increased continuously throughoutthe entire cooling process.

5.2. FEA examination

Figs. 810 showed the deformation patterns aroundthe crack-tip of the assembly under the three tempera-tures of 75 C under heating process, 50 C under cool-ing process and 40 C under cooling process. It wasnoted that the displacements attained from FEA werein agreement with those obtained from the moire test.In addition, the results proved the tendency of defor-mation described before. It was also an evidence thatthe viscoelastic properties of underll and the tempera-ture-dependent properties of FR-4 and silicon wafermodeled in FEA could more realistically describe the

thermal deformation of the sandwich ip chip speci-

men. It is therefore proved that, in case the materialmodel of underll is accurately modeled, the more real-istic results could be obtained through numerical

simulation.

Fig. 6. Moire fringe pattern under accelerated temperaturecycling test: (a) U eld at 75 C during heating up (stage B inFig. 4 ); (b) V eld at 75 C during heating up (stage B in Fig. 4 );(c) U eld at 100 C during cooling down (stage F in Fig. 4 ); (d)V eld at 100 C during cooling down (stage F in Fig. 4 ); (e) Ueld at 0 C during heating up (stage O in Fig. 4 ); (f) V eld at0 C during heating up (stage O in Fig. 4 ).



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5.3. Fracture behavior investigation

Note that the Dundur

s parameters change as a func-tion of elastic mismatch between chip/underll. In casethe elastic moduli of the underll varied signicantlywhen the temperature went up around and even abovethe T g, the corresponding interfacial toughness waschanged obviously. In the experiment, the CTODs werederived from the moire fringe patterns representing dis-placement along the two crack anks. Typical CTODsof the whole temperature cycling are displayed inFig. 11 . As seen, when the temperature cooled downto the room temperature, the excessive CTODs werefound along the crack. The residual deformation wascaused by the viscoelastic behavior of the underll atthe high temperature. When the assembly loaded inthe minus temperature, the viscoelasticity of the underllwas not signicant since the underll material exhibitelastic characteristic at the low temperature.

In this study, a characteristic length l = hunderllvalued 0.5 mm was selected as reference length. Theselection of l was within the zone of dominance of theK -eld, i.e., elastic zone of bimaterial, where the varia-tion of l is negligible even for changes of l of several or-ders of magnitude since e is small in the case of Si/underll interface [15]. With the length l , the nominalSIFs were calculated as function of r1/2 [7]. As shown

in Fig. 12 , the nominal K 01 increased when the r1/2 de-creased, while the nominal K 02 almost remain as a con-stant when the r1/2 decreased. The two nominal SIFsshowed an approximate linear relationship with ther1/2 . It is reasonable to assume that the deformation eldaround the crack-tip was dominated by the K -eld, andthe linear extrapolation method [20] could be employedto determine the fracture toughness at the crack-tip. Bycurve tting, the experimental and FEM results wereextrapolated to the y-axis using straight line, which rep-resented the interfacial toughness K 1 and K 2 at the crack-tip. The values of K eff and w were then calculated with

Eqs. (5) and (6) and the results are plotted in Fig. 13 .

During the heating process, it was observed in Fig.13(a) that the highest value of K eff happened at the tem-

perature between 75 C and 100 C rather than 125 C.From Eqs. (2)(6) , it can be seen that changes of E * willaffect the value of K eff [7]. The possible explanationmight be that both CTE and stiffness mismatch insidelayered structure could signicantly inuence the defor-mation and corresponding fracture behaviors. Particu-larly, in case the temperature went up to the T g of theunderll, the underll is malleable because of the contin-uing rearrangement of molecular segments, which isinuenced by the secondary bonds in the crystalline re-gion. The rearrangement results in the dramatic deceasein Young s modulus of underll, and therefore alters themechanical relationship in the sandwich structure.Mathematically, it is expressed as rapid decrease in E *as dened in Eq. (4). Accordingly, SIFs are prone to de-crease signicantly as the temperature is close to or high-er than the T g of the underll. It could be expressed as

CTE mismatch factor :

F 1 f 1 jCTE underfill T CTE FR -4T j ;Stiffness mismatch factor :

F 2 f 2 j E underfill T E FR -4T j ;Warpage : W g F 1 F 2.

8

Similarly, the increase of underll modulus at theminus temperatures was helpful to increase the K eff .When the temperature cooled down, there was residualK eff generated with the comparison of the K eff at thesame temperature during the heating up process. Thisresidual value was aroused by viscoelastic deformationespecially when the temperature exceeded the T g. Theshifted sign of the phase angle during cooling process,as presented in Fig. 13 (b), showed alteration of thedirection of shear stress inside the specimen.

As aforementioned, K eff decreased as stress relaxationhappened in the glass transition state of underll. How-ever, one cannot determine that the most dangerous

stage in the thermal cycling was located at the point with

Fig. 7. Schematic diagram of deformed shape within whole temperature cycling.



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highest K eff , since the interfacial toughness varies withthe mode mixity at the same time [15]. According tothe denition of interfacial fracture extension, theexpression can be K eff K eff w;

w tan 1 Im KLie

Re KLie

h i;) 9

where w is the mode mixity. From Eq. (9), it can be seenthat the value of K eff becomes a curve with the functionof mode mixity w rather than an independent point.Thus, referring to the work done by Suo [21], it is knownthat the smaller phase angle has corresponding smallerK eff since mode I failure is more fatal than mode II.

Apart from mode mixity, it was anticipated that change

Fig. 8. U and V contour map at 75 C during heating up (stage B in Fig. 4 ).



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of material stiffness (modulus) induced by temperaturevariation would also decrease the interfacial fracturetoughness when the phase angle is xed [22]. In orderto examine the possibility of assembly failure, the ratio

of effective interfacial toughness K eff and critical interfa-

cial toughness K Ceff was introduced to describe the frac-ture behavior of underll/chip interface under ATCloading. The data of critical interfacial toughness forthe same interface were obtained from our previous

study as shown in Table 3 [12]. As a result, the ratio

Fig. 9. U and V contour map at 50 C during cooling-down (stage H in Fig. 4 ).



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of K eff and K Ceff at 75 C was found to be smaller than

that at 125 C, i.e., K eff K Ceff 75 C 0.185 < K eff K Ceff 125 C 0.2. This showed that 125 C was supposed to be themost catastrophic point during the high temperatureloading. Similarly, the ratio of K eff and K Ceff at 40 C

was determined to be 0.4, which is even greater thanthe ratio at 125 C. It implied that it is also possible toinduce the crack propagation at 40 C. Therefore, itis expected that the interface delamination is prone topropagate at the both extreme temperatures, i.e.,125 C and 40 C, during the thermal cycling.

Fig. 10. U and V contour map at 40 C during cooling-down (stage L in Fig. 4 ).



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6. Conclusions

In-situ moire measurement was carried out to inves-tigate the thermal deformation and interfacial toughnessof delaminated ip chip package under the 40 C to125 C thermal loading condition using the M 3I system.FEA numerical simulation was applied to verify theexperimental results with the consideration of viscoelas-tic properties of underll. The results showed goodagreement between experiment and numerical simula-tion results, which indicated that in-situ measurementcan well reect the structure response of ip chip assem-bly under thermal cycling.

Both moire and simulation results showed that notonly CTE mismatch was a main cause for interfacialdelamination, but also stiffness mismatch played impor-

tant role on structure deformation and consequentlyfracture behaviors. The coupling effect between CTEmismatch and stiffness mismatch was of importance tobe considered in the design and material choices of ipchip manufacturing. Since the interfacial toughnesshad different mode mixities at different temperatures, itmight not be a suitable parameter for assessment of the most dangerous situation for the package. The ratioof effective interfacial toughness and critical interfacial

Fig. 11. CTODs at the distance of r /l = 0.3 obtained frommoire experiment for the whole temperature cycle ( l = 0.5 mm;referring to Fig. 4 ).

Fig. 12. SIFs obtained at 25 C as functions of r1/2 .

Fig. 13. Representative interfacial toughness and phase angleobtained from FEA and moire : (a) comparison of FEA andmoire with respect to K eff and (b) comparison of FEA andmoire with respect to ^w.

Table 3Fracture toughness evaluation

Temperature( C)

Modemixity( )

K eff (MPa m 1/2 )

K Ceff (MPa m 1/2 ) [20]

K eff /K Ceff

75 72.4 0.105 0.568 0.185

125 46.8 0.042 0.210 0.240 57.3 0.271 0.671 0.4



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toughness needs to be introduced to determine the mostdangerous ATC testing condition.

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2006 - reliability of interface under accelerated temperature cycling (1)

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