1

•Dielectrics:

- Epitaxial growth. Single crystal. Batch to single

wafer.

- Silicon Dioxide (Oxide). Alternative to batch

furnace.

- SACVD Oxides: BPSG (PMD), FSG, USG

(IMD), TEOS/03

- Silicon Nitride

• Conductors:

- mainly Tungsten. High aspect ratio plugs.

• Single wafer processing.

Chemical Vapor Deposition

2

•The most critical process in IC

manufacturing

•Patter transfer process

•Leading edge (sub-wavelength

lithography):

248nm light to pattern 130nm features

- phase shifting masks/reticles

- optical proximity correction

•Next generation: 193nm, 57nm, 13nm

Lithography

3

Direct Step on Wafer (DSW) AlignerOptical Configuration

4

Comparison of Step and Repeat vs. Step and ScanLithography tool types

5

Lithography: Alignment and Exposure(Stepper/Scanner)

6

Characteristics of Negative and Positive Resists

7

Photoresist DevelopPositive Resist

8

•Wet (chemical bath) for > 3 microns or

Dry (plasma reactor) < 3 microns

•Conductors (31%), polysilicon (25%),

oxide etch (44%)

•Metal etch 35 - 40 wph.

Etch (material removal)

9

Applied Materials 5000 Etch Process Chamber

Source: Applied Materials (AMAT)

10

The Plasma

The plasma supplies etchants which must remove the film selectively; Ideally the mask and substrate are not

attacked.

Source: D.L. Flamm, 1996

11

Etch Chemistries

Source: D.L. Flamm, 1996

12

Etch

Metal Etch

typically dry (Plasma Reactor) etch

* Al to resist etch selectivity: 3:1

13

Photolithography Process Flow Chart

14

Oxide and Copper

CMP Processing

Why CMP for copper?- because no-one can figure out how to etch copper at low temperature.

3 Steps for Deposition1. CU barrier (Ta, TaN) using PVD2. CU seed using PVD3. CU bulk using ECD

CMP (oxide) - used with AL today

1. Deposit blanket metal

AL DEP

SL

SLAL AL AL

2. Litho (expose and develop) and etch

SL

3. Oxide Deposition (CVD)

Oxide

SLAL AL AL

4. CMP (grind down, flat)

OXOxide

AL AL AL

CMP (for Copper)

1. Deposit blanket oxide

Oxide

SL

SLOX OX OX

2. Litho and etch oxide

SL

3. Blanket Copper Deposition

CU

SLOX OX OX

4. CMP (grind down and flatten)

CU CU

OX OX OX

15

•Doping process (changes the electrical

characteristics of the material)

•Creates the elements of the transistors

•Fires ions of dopant material into the

wafer

•P (positive) dopants OR N (negative)

dopants

•Older doping process: diffusion

•Need to repair damages from

bombardment: anneal or Rapid Thermal

Processing (RTP)

Ion Implant

16

Periodic Table of the Elements

17

Typical Ion Implantation Equipment

Source: SJSU

Section C

Future Trends

19

•300 nm wafer processing. Ramp

occurring slowly.

•New materials:

- Cu is here. High-end Logic (3.06GHz P4).

- low-k dielectrics. Next major material

change.

- dielectric substrate engineering: SOI,

Strained Silicon.

- high-k dielectric materials for gates

•Economics may limit Moore’s Law, not

physics !

Future Trends

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