1

APV25 I2C parameters

Brief reminder of what the I2C registers do (from User Manual)

Check on integration centre currently used parameters: TIB/TOB/TEC(thanks to Mariarosaria D’Alfonso, Andrea Rizzi, Katja Klein, Gaelle Boudoul)

VPSP scan considerations

Some information from APV wafer test database on production uniformitye.g. how well will chips match without individual tuning

Pointers to reference information

m.raymond@imperial.ac.uk - July '06

2

APV25 analog chain

IPREIPCASC

IPSF

ISHA

ISSFIPSP

IMUXIN

VFPVFS VPSP

MUXGAIN

IPRE, IPCASC, IPSF, ISSF, IPSP, IMUXIN, ISHAcurrents provided by bias generator to set operating points of analogue stages8 bit values 0 -> 255 (read/write register access)

VFP, VFS, VPSPvoltages generated by dumping programmable currents into on-chip resistors8 bit values 0 -> 255 (read/write register access)

ISHA and VFS are “free” parameters for tuning pulse shape, but can specify default values

VPSP is “free” parameter for analogue baseline adjust – but watch power consumption (see later)

3

APV mode register (R/W)

8 bit register – only 6 bits used

bit no. 5 preamp polarity 0 = non-inverting 1 = inverting 4 readout frequency 0 = 20 MHz 1= 40 MHz 3 readout mode 0 = decon. 1 = peak 2 calibration inhibit 0 = OFF 1 = ON 1 trigger mode 0 = 3 sample 1 = 1 sample 0 analogue bias 0 = OFF 1 = ON

examples:

binary dec.

100101 37 inverting, 20 MHz, decon., cal inhibit ON, 3 sample, bias ON

101111 47 inverting, 20 MHz, peak, cal inhibit ON, 1 sample, bias ON

100001 33 inverting, 20 MHz, decon., cal inhibit OFF, 3 sample, bias ON

101011 43 inverting, 20 MHz, peak, cal inhibit OFF, 1 sample, bias ON

normaloperationno CAL

normaloperationwith CAL

4

MUX gain (R/W)

8 bit register – only 5 bits usedfeature included to accommodate extreme process variations in on-chip resistor values

bit no. 4 highest 3 higher 2 nominal 0 = OFF 1 = ON 1 lower 0 lowest

binary dec.

10000 16 +20%01000 8 +10%00100 4 nominal00010 2 -10%00001 1 -20%

5

Calibration and Latency (R/W)

Calibration - 8 bit registers

CDRV mask (all ones except one you want to drive)e.g. 11101111

CSEL mask (all ones except delay you want to select – 8 steps of 3.125 nsec)there is a mistake in the user manual here!

ICAL calibration pulse amplitudenot well controlled – relies on small overlap region between two metal tracksso can use to “calibrate” (tune) pulse shape, but not gain

Latency - 8 bit register sets separation between write and trigger pointers to the pipeline

can take any value up to 191

if changed then must issue Reset101 to relaunch pipeline pointersotherwise chip will malfunction and latency error generated

6

Error Register (Read only)

8 bit register – only 2 bits used

bit 1 FIFO error (overflow – should not happen (APVE protects))bit 0 Latency error (distance between write and trigger pointers to pipeline

not equal to programmed latency)

can (should) only return: bin. dec.

00 0 no errors01 1 latency error10 2 FIFO error11 3 latency and FIFO error

SEU effects may well cause these errorsif chip detects either error then error bit also set in output data header

7

TIB TOB TEC+ TEC-

IPRE 98 98 98 98IPCASC 52 52 52 52IPSF 34 34 34 34ISHA 46 80 80 80ISSF 34 34 34 34IPSP 55 55 55 55IMUXIN 34 34 34 34ISPARE 0 0 0 0ICAL 40 40 40 40

VFP 30 30 30 30VFS 70 50 30 50VPSP 37 34 37 33

CDRV 0 0 0 0CSEL 8 8 8 8

MODE 47 37 47 37LATENCY 100 100 100 100MUXGAIN 4 4 4 4

ERROR 0 1 1 1

Integration centre parameters currently in use

all subdetectors agree

pulse shape and baselineadjustment “free” parameters

needs to be set correctly for“calibration” (see p.5)

preamp polarity / RO freq. / (decon/peak) / CAL inhibit /(3/1)sample / bias (ON/OFF)

should be read only

WARM (room temp. ~ +30)

discrepancy may account for small differencesobserved in TEC+/TEC- performance?

8

TIB TOB TEC

IPRE 85 85 85IPCASC 45 45 45IPSF 30 30 30ISHA 30 50 50ISSF 30 30 30IPSP 48 48 48IMUXIN 30 30 30ISPARE 0 0 0ICAL 40 40 40

VFP 30 30 30VFS 70 50 60VPSP 37 - -

CDRV 0 - -CSEL 8 - -

MODE 47 - -LATENCY 100 100 100MUXGAIN 4 4 4

ERROR 0 0 0

Parameters currently in use and proposed

all subdetectors agree

pulse shape and baselineadjustment “free” parameters

needs to be set correctly for“calibration” (see p.5)

preamp polarity / RO freq. / (decon/peak) / CAL inhibit /(3/1)sample / bias (ON/OFF)

should be read only

COLD (-10 -> -20)

values used by TIB provided by Andrea Rizzi in agreement with:http://www.hep.ph.ic.ac.uk/~dmray/pdffiles/cold_APV_params.pdf

values for TOB/TEC are what I propose here in agreement with:http://www.hep.ph.ic.ac.uk/~dmray/pdffiles/TOB_cold_APV_params.pdfhttp://www.hep.ph.ic.ac.uk/~dmray/pdffiles/TEC_cold_APV_params.pdf

9

Parameters currently in use and proposed

WARM (room temp.)

TIB TOB TEC+ TEC- TIB TOB TEC

IPRE 98 98 98 98 85 85 85IPCASC 52 52 52 52 45 45 45IPSF 34 34 34 34 30 30 30ISHA 46 80 80 80 30 50 50ISSF 34 34 34 34 30 30 30IPSP 55 55 55 55 48 48 48IMUXIN 34 34 34 34 30 30 30ISPARE 0 0 0 0 0 0 0ICAL 40 40 40 40 40 40 40

VFP 30 30 30 30 30 30 30VFS 70 50 30(50) 50 70 50 60VPSP 37 34 37 33 37 - -

CDRV 0 0 0 0 0 - -CSEL 8 8 8 8 8 - -

MODE 47 37 47 37 47 - -LATENCY 100 100 100 100 100 100 100MUXGAIN 4 4 4 4 4 4 4

ERROR 0 1 1 1 0 0 0

all subdetectors agree

pulse shape and baselineadjustment “free” parameters

needs to be set correctly for“calibration” (see p.5)

preamp polarity / RO freq. / (decon/peak) / CAL inhibit /(3/1)sample / bias (ON/OFF)

should be read only

COLD (-10 -> -20)

suggest default VFS (prior to tuning) -> 50 for TEC+unless this causes problemsfor comparisons with previouslymeasured data

10

be careful with VPSP scans

analogue baseline

VPSP setting adjusts analogue baseline position

works by introducing DC voltage offset at APSP O/P which in turn produces DC offset current flowing in the MUXstages

baseline setting has strong effect on overall power

e.g. assume baseline tuned to ~ 25% relative to dig. head amp.

get ~7% power increase if move from 25% to 50%level

much more (~ 28%) if scan through full range

for setting up, better to start with high value (lowbaseline) and scan down (baseline rises) until targetvalue reached (then stop)

see:http://www.hep.ph.ic.ac.uk/~dmray/pdffiles/cold_APV_params.pdfhttp://www.hep.ph.ic.ac.uk/~dmray/pdffiles/Detailed%20APV25%20Power%20Consumption.pdf

0

100%

50%

module powerbaseline pos’n

TIB modulemeasurement

11

Some info from APV production test data

~ 600 wafers (~ 216,000 chips) tested over ~ 4 yearsincluding early production wafers with yield problems which were not usedproduction lots from lot 9 onwards

individual chips subjected to detailed testing of analogue/digital functionality -> Known Good Die (KGD)

individual chip results stored => analysis of database -> insight into overall uniformity

note: I2C parameters used in production test kept constant throughout (including ISHA and VFS) exceptfor VPSP

100

90

80

70

60

50

40

30

20

10

0

yie

ld [%

]

29282726252423222120191817161514131211109876543210

production lot number

individual wafers lot averages

Production wafer yields (360 chips / wafer)

12

ampl

itude

nor

m.

to m

ax.

puls

e ht

.

12.5 nsec./division

ampl

itude

nor

mal

ised

to

max

. pu

lse

heig

ht

12.5 nsec./division

simulation parameters - 2 - 1 nominal + 1 + 2

intensity plots show pulse shapes from all 131,734 KGD from 414 production wafers (lots 9 – 29) overlaid

SPICE simulated peak mode pulse shapes show almost all chips lie within 1 of nominal

Normalised Pulse Shapes

peak mode

deconvolution

=> pulse shapes match quite well even without tuning

13

120

100

80

60

40

20

0

AD

C u

nits

100806040200

3.125 ns steps

ISHA=30

ISHA=100

ISHA=80,VFS=60

120

100

80

60

40

20

0

AD

C u

nits

VFS=0

VFS=120

ideal CR-RC ISHA=80,VFS=60

100

80

60

40

20

0

-20

AD

C u

nits

100806040200

3.125 ns steps

VFS=0

VFS=120

ISHA=80,VFS=60

120

100

80

60

40

20

0

AD

C u

nits

ISHA=30

ISHA=100 ideal CR-RC ISHA=80,VFS=60

VFS fixed, vary ISHA ISHA fixed, vary VFS

Pulse shape tuning

strong effect on decon pulse shape

weak effect

weak effect

strong effect on peak pulsefall time

14

Output Frame Parameters

APV output frame consistsof digital header followedby 128 analogue samples

digital header amplitude set by on-chip current reference

mean header amplitude andspread for all KGD/lot shows minimal lot dependence

average analogue pedestal (baseline) set by VPSP– the only parameter varied during wafer test (tunedto position baseline at 25% of digital header range)

mean value and spread of distributions of VPSP values required to set 25% level show some lot dependence, but well within available adjustmentrange

error bars show 1 std. dev.

80

60

40

20

0head

er a

mp.

[A

DC

uni

ts]

292725232119171513119production lot number

O/P

am

plitu

de

1 sec./division

digital header

128 analog samples

signal

45

40

35

3045

40

35

30292725232119171513119

VP

SP

va

lue

production lot number

peak mode

deconvolution

15

lots of info and links at:http://www.hep.ph.ic.ac.uk/~dmray/Tracker.html

I2C parameter recommendations for different temperatures:http://www.hep.ph.ic.ac.uk/~dmray/pdffiles/cold_APV_params.pdfhttp://www.hep.ph.ic.ac.uk/~dmray/pdffiles/TOB_cold_APV_params.pdfhttp://www.hep.ph.ic.ac.uk/~dmray/pdffiles/TEC_cold_APV_params.pdf

APV production data analysis LECC paper:http://indico.cern.ch/getFile.py/access?contribId=108&resId=0&materialId=paper&confId=0510

Reference information

16

Transistor level – for info (1)

IPRE IPCASC IPSF ISHA ISSF

VFP VFS

PREAMPSF

SFINV

preamppolarityselect

SHAPERpipeline

17

Transistor level (2)

IPSP

IMUXIN

VPSP

MUXGAIN

APSP