work in progress --- not for publication draft – work in progress - not for publication 13 july...

Work in Progress --- Not for PublicationDRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005

Interconnect Working GroupInterconnect Working Group

ITRS 2005

13 July 2005

San Francisco


Agenda• Membership• Scope and cross section• Key issues• MPU Half Pitch• Cu resistivity effects• Crosstalk• Low k comments• DRAM• Summary


JapanTomoji NakamuraHideki Shibata

TaiwanDouglas CH Yu

USRobert GeffkenChristopher Case

Europe

Hans-Joachim Barth

Alexis Farcy

Korea

Hyeon-Deok Lee

Hyun Chul Sohn

ITWG Regional Chairs


Participants• Robert Geffken• Hans-Joachim Barth• Alexis Farcy• Harold Hosack• Paul Feeney• Ken Monnig• Rick Reidy• Hideki Shibata• Kazuyoshi Ueno• Michele Stucchi• Douglas Yu• Ming-Shih Yeh

• Osamu Yamazaki• Lucile Arnaud• JD Luttmer• Brongersma Sywert• Ivan Berry• Manfred Engelhardt• Dirk Gravesteijn• NS Nagaraj• Mike Mills• Gunther Schindler• Chung-Liang Chang• Tomoji Nakamura• Christopher Case


Interconnect scope• Conductors and dielectrics

– Metal 1 through global levels– Starts at pre-metal dielectric (PMD)

• Associated planarization • Necessary etch and surface preparation• Embedded passives• Reliability and system and performance issues• Ends at the top wiring bond pads• Predominantly “needs” based, with some

important exceptions ( and resistivity)


Global

Semi-Global

Intermediate

Metal 1

Passivation

Dielectric

Etch Stop Layer

Dielectric Capping Layer

Copper Conductor with Barrier/Nucleation Layer

Pre Metal Dielectric

Metal 1 Pitch

Tungsten Contact Plug

Typical ASIC Chip Cross Section

Via

Wire


Global (up to 5)

Intermediate

Metal 1

Passivation

Dielectric

Etch Stop Layer

Dielectric Capping Layer

Copper Conductor with Barrier/Nucleation Layer

Pre Metal Dielectric

Metal 1 Pitch

Tungsten Contact Plug

Typical MPU Chip Cross Section

Via

Wire


Technology Requirements • Wiring levels including “optional levels” • Reliability metrics• Minimum wiring/via pitches by level• Performance metric• Planarization requirements• Conductor resistivity• Barrier thickness • Dielectric metrics including effective • Crosstalk figure of merit


• Recent publications by logic device manufacturers suggest that M1 pitch and intermediate wire minimum pitch are scaling at a rate faster than the 2004 ITRS

• “Non-contacted” or “staggered contacted” M1 pitch is widely used by most logic manufacturers. To avoid ambiguity - we will use staggered contacted M1 half pitch.

• Changes:– 90 nm M1 half pitch in 2005 – scaling at x 0.75 / 2 years from 2005 to 2009– reverting to 3 years cycle in 2010 and beyond

• Metal 1 pitches converging between DRAM, logic, flash

Whose linewidth is it anyway? The pitch for M1


Source: 2003 ITRS - Exec. Summary Fig 4

Fig 4

Metal Pitch

Typical DRAM Metal Bit Line

DRAM ½ Pitch = DRAM Metal Pitch/2

Poly Pitch

Typical MPU/ASIC Un-contacted Poly

MPU/ASIC Poly Silicon ½ Pitch = MPU/ASIC Poly Pitch/2

Typical MPU/ASICContacted Metal 1

MPU/ASIC M1 ½ Pitch = MPU/ASIC M1 Pitch/2

Metal 1 (M1) Pitch

- Staggered contacted M1 pitch same as DRAM - Staggered contacted M1 pitch same as DRAM

Half Pitch Definition


Year DRAM h.p(nm)MPU/ ASIC M1

h.p(nm)2004 updated

MPU/ ASIC M1h.p(nm)

2005 proposed(U.S)

MPU/ ASIC M1h.p(nm)

Commercial

MPU/ ASIC M1h.p(nm)

2005 proposed(J apan)2001 160 2002 2003 100 120 120 2004 90 107 2005 80 95 85 90 902006 70 85 76 782007 65 76 67 65 672008 57 67 60 582009 50 60 54 50 502010 45 54 48 452011 40 48 42 402012 35 42 38 352013 32 38 34 322014 28 34 30 282015 25 30 27 252016 22 27 24 222017 20 24 21 202018 18 21 19 182019 16 19 17 162020 14 17 15 14

70%/ 3years 70%/ 3years 70%/ 3years 75%/ 2years 75%/ 2years( 2009)～70%/ 3years(2010 )～

10

100

2000

2002

2004

2006

2008

2010

2012

2014

2016

2018

2020

- 90nm half pitch in 2005 and 75% shrink/2years- Scaling rate relaxed to 70%/3years same as DRAM after 2010

M1 half pitch


Size matters• 2003 – the impending impact of Cu resistivity increases at

reduced feature sizes (due to scattering) - noted• 2004 – metrics introduced to highlight the impact of width

dependent scattering on the effective resistivity and impact on RC delay

• For 2005-– Models have been refined using data to more accurately

predict the resistivity due to changes in aspect ratio, shape metal thickness, and grain boundary scattering

– Metrics have been recalculated• Adapt the same methodology for DRAM when Cu is

introduced (2007)


Size matters

Courtesy: Infineon Technologies

Copper resistivity o = constant 1.8 -cm at 300 KA mean free path of charge carriers =3.4×10-6 cmA wire width W (cm)A probability for reflection of electrons at the grain boundaries of 0.19The portion, p=0.33 of electrons specularly reflected from the walls (surface or interface).


Impact of scattering on line resistivity

Year of Production 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020

IsMPU/ASIC Metal 1 (M1) ½ Pitch (nm)(contacted) 90 78 67 58 50 45 40 35 32 28 25 22 20 18 16 14

Is

Conductor effective resistivity ( -cm) Cu Metal 1 wiring, including effect of width dependent scattering and a conformal barrier of thickness specified below, calculated from data available in 2005

3.15 3.29 3.47 3.67 3.9 4.08 4.3 4.63 4.83 5.2 5.58 6.01 6.33 6.7 7.34 8.19

Is

Conductor effective resistivity ( -cm) Cu wiring, assumes no scattering

2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2

From discussion with Design TWG•Resisitivity rise ‘not a problem’ for M1•May be ‘yellow’ issue for intermediate levels at/after 45nm


10 100 10002

3

4

Height 50 nm Height 155 nm Height 190 nm

Re

sist

ivity

[ c

m]

Line width [nm]

Aspect Ratio Dependence

Courtesy: Infineon Technologies


Interconnect performance: crosstalk• Crosstalk among neighbouring interconnects

– Capacitive crosstalk roughly proportional to c = CIMD / CILD

Mainly fixed by the aspect ratio of lines and vias Crosstalk level increases at each new generation

– Induces delay uncertainty (delay increased by crosstalk up to 3x delay)

Crosstalk is becoming a major issue Special attention should be paid on these parasitic effects

20%

25%

30%

35%

130 nm 90 nm 65 nm 45 nm 32 nm 22 nmTechnology node

Cro

ssta

lk r

atio

1.5

1.6

1.7

1.8

1.9

2

2.1

Lin

e as

pec

t ra

tio

Crosstalk ratioAspect ratio

0

0.2

0.4

0.6

0 0.1 0.2 0.3 0.4 0.5 0.6Time (ps)

Volta

ge (V

)

Crosstalk level

Input signal Metal 1


Crosstalk• Raise awareness of crosstalk issues

– Introducing a crosstalk metric to raise visibility of this issue

– Potential solutions

• Introduction of ULK materials Only a slight impact on crosstalk as both CIMD and CILD decrease

• Development of hybrid architectures Strong reduction of crosstalk level Ultimate hybrid architecture is air gap

• Reduction of the k-value of additional capping layers Low-k dielectric barriers Self-aligned barriers


65 nm example of effective calculation for Realistic and Aggressive Structures

Structure Homogeneous Homo w/HM Hybrid

(Cu D.B) 4.0 4.0 4.0

(Hardmask) NA 3.0 3.0

(via) 2.7 2.5 2.4

(trench) 2.7 2.5 2.5

eff 2.96 2.87 2.83


Cu D.B height[nm] 35 35 35

Hardmask height [nm] NA 40 40

Via height [nm] 112 112 112

Trench height [nm] 126 126 126

Minimum L/S [nm] 70 70 70

Aggressive case in 2007Aggressive case in 2007Realistic case in 2007Realistic case in 2007


(Cu D.B) 4.0 4.0 4.0

(Hardmask) NA 3.0 3.0

(via) 2.5 2.3 2.3

(trench) 2.5 2.3 2.3

eff 2.78 2.72 2.72

Same thickness at same generation but different materials with various structures value range


Low again! Near Term

Table 81a and b MPU Interconnect Technology Requirements

Year of Production 2005 2006 2007 2008 2009 2010 2011 2012 2013

DRAM ½ Pitch (nm) (contacted) 80 70 65 57 50 45 40 35 32

MPU/ASIC Metal 1 (M1) ½ Pitch (nm)(contacted)

90 78 67 58 50 45 40 35 32

Interlevel metal insulator – effective die lectric constant ()[4]

3.1–3.6 3.1–3.6 2.7–3.0 2.7–3.0 2.7–3.0 2.3-2.6 2.3-2.6 2.3-2.6 2.0-2.4

3.1 - 3.4 3.1 - 3.4 2.7 - 3.0 2.7 - 3.0 2.5 - 2.8 2.5 - 2.8 2.5 - 2.8 2.1 - 2.4 2.1 - 2.4Interlevel metal insulator (minimum expected) – bulk dielectric constant ()

<2.7 <2.7 <2.4 <2.4 <2.4 <2.1 <2.1 <2.1 <1.9

≤ 2.7 ≤ 2.7 ≤ 2.4 ≤ 2.4 ≤ 2.2 ≤ 2.2 ≤ 2.2 ≤ 2.0 ≤ 2.0

Near-term

This is the first dielectric acceleration in 4 years

Recognizes renewed interest in ULK and potential solution to integration challenges


Low again! Long TermTable 81a and b MPU Interconnect Technology Requirements

Year of Production 2014 2015 2016 2017 2018 2019 2020

DRAM ½ Pitch (nm) (contacted) 28 25 22 20 18 16 14

MPU/ASIC Metal 1 (M1) ½ Pitch (nm)(contacted)

28 25 22 20 18 16 14

Interlevel metal insulator – effective dielectric constant ()[4]

2.0-2.4 2.0-2.4 <2.0 <2.0 <2.0

2.1 - 2.4 1.9 - 2.2 1.9 - 2.2 1.9 - 2.2 1.6-1.9 1.6-1.9 1.6-1.9Interlevel metal insulator (minimum expected) – bulk dielectric constant ()

<1.9 <1.9 <1.7 <1.7 <1.7

≤ 2.0 ≤ 1.8 ≤ 1.8 ≤ 1.8 ≤ 1.6 ≤ 1.6 ≤ 1.6

Long-term

No known solutions for the long term bulk dielectric materials


From low to no - air gaps• Introduction of air gap architectures

– Creation of air gaps with non-conformal deposition– Removal of sacrificial materials after multi-level interconnects

Values of effective k-value down to 1.7 with low crosstalk levels Localized air gaps to maintain good thermal and mechanical properties

Ultra-low and Air gap (<2.0) (CVD & Spin-on)

Non-conformal deposition Sacrificial material


DRAM• Small changes in specific via and contact

resistivity

• Contact A/R rises to >20 in 2020 - a red challenge - associated with 16 nm DRAM half pitch

• Low in 2003 - Cu delayed to 2007

• Identified need to distinguish embedded, flash, and traditional DRAM


• Metal 1 design rule concerns– Staggered pitch used for definition - agreed– New

• 90 nm half pitch for 2005 - agreed• High performance MPU pitches scaling at

~0.75/2 years until 2009• Returning to 0.7/3 years

• Local wiring pitches for logic, DRAM and SRAM will converge ~ 2010 and follow a common 3 year trend

• Intermediate and local wiring pitches will also merge similarly ~ 2010

2005 last words


Last words• Continued changes in materials• Must manage 3D CD • System level solutions must be accelerated to

address the global wiring grand challenge – materials solutions alone cannot deliver performance -

end of traditional scaling – integrated approach with design and packaging

• For 2006 – preparing 3D IC interconnect roadmap– Quantifying emerging interconnect potential solutions

work in progress --- not for publication draft – work in progress - not for publication 13 july...

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