with articles by dennard, itoh, koyanagi, sunami, foss...

SSCSSSCSSSCSSSCSIEEE SOLID-STATE CIRCUITS SOCIETY NEWSWinter 2008 Vol. 13, No. 1 www.ieee.org/sscs-news

The DRAM Story with articles by Dennard, Itoh, Koyanagi,

Sunami, Foss and Isaac

sscs_NLwinter08 1/8/08 10:37 AM

Welcome tothe Winter,2008, issue

of the Solid-State Cir-cuits Society News-letter! We appreciateall of your feedbackon our first year of

issues presenting The TechnicalImpact of Moore's Law, The Impactof Dennard’s Scaling Theory, The40th Anniversary of Amdahl's Law,and Barrie Gilbert: The Gears ofGenius. Thank you for supportingour efforts!

The goal of each issue is to be aself-contained resource with back-ground articles (that is, the 'originalsources') and new articles byexperts who describe the currentstate of affairs in technology in viewof the impact of the original papersand/or patents.

This issue contains one EducationHighlights article:

"Turning Students On to Circuits,"by Yannis Tsividis of Columbia Uni-versity in New York City, NY.

The theme of the issue is "TheDRAM Story with new articles by

Dennard, Itoh, Sunami, Koyanagi,Isaac and Foss," discussing the evo-lution and current status of DRAM:(1) "Revisting ‘Evolution of the

MOSFET Dynamic RAM-A Per-sonal View’" by Robert Dennard(IBM);

(2) "The History of DRAM CircuitDesigns - At the Forefront ofDRAM Development" by KiyooItoh (Hitachi Ltd);

(3) "Stacked Capacitor DRAM Celland Three-Dimensional Memo-ry" by Mitsumasa Koyanagi(Tohoku University);

(4) "The Role of the Trench Capaci-tor in DRAM Innovation" byHideo Sunami (Hiroshima Uni-versity);

(5) "The Remarkable Story of theDRAM Industry" by Randy Isaac,retired Vice President (IBM);

(6) "DRAM - A Personal View" by R.C. Foss, retired Chairman of theBoard and Founder (MOSAIDTechnologies Incorporated).

In addition, the issue includesreprints of two original papers andan original patent: (1) R. H. Dennard, "Evolution of the

MOSFET Dynamic RAM - A Per-sonal View," IEEE Transactionson Electron Devices, vol. ED-31,No. 11, November, 1984, pp.1549-1555.

(2) R. H. Dennard, "Field-EffectTransistor Memory," Patent3,387,286, June 4, 1968.

(3) K. Itoh, "In Quest of the Joy ofCreation," in "Innovate theFuture," 2005 Hitachi HyoronSpecial Edition, pp. 34-39,Hitachi Hyoronsha, Tokyo,Japan.

Thank you for taking the time toread the SSCS News. We appreciateall of your comments and feedback!Please send comments [email protected].

2 IEEE SSCS NEWS Winter 2008

President:Willy SansenK. U. LeuvenLeuven, [email protected]: +32 16 321975

Vice President:Bernhard BoserUniversity of CaliforniaBerkeley, CA

Secretary:David A. JohnsUniversity of TorontoToronto, Ontario, Canada

Treasurer:Rakesh KumarTechnology Connexions Poway, CA

Past President:Richard C. JaegerAlabama Microelectronics CenterAuburn University, AL

Other Representatives:Representative to Sensors Council

Darrin YoungRepresentative from CAS to SSCS

Domine LeenaertsRepresentative to CAS from SSCS

Un-Ku Moon

Newsletter Editor:Mary Y. LanzerottiIBM T.J. Watson Research [email protected]: +1 914 945 1358

Associate Editor for Europe/Africa:Tony HarkerISLI Alba Centre Alba CampusLivingston Scotland EH54 [email protected]

Elected AdCom Members at LargeTerms to 31 Dec. 08:

Wanda K. GassAli HajimiriPaul J. HurstAkira MatsuzawaIan Young

Terms to 31 Dec. 09:John J. CorcoranKevin KornegayHae-Seung (Harry) LeeThomas H. LeeJan Van der Spiegel

Terms to 31 Dec. 10:Terri S. FiezTadahiro KurodaBram NautaJan SevenhansMehmet Soyuer

Region 8 Representative:Jan Sevenhans

Region 10 Representative:C.K. Wang

Chairs of Standing Committees:Awards John J. CorcoranChapters Jan Van der SpiegelEducation C.K. Ken YangMeetings Bill BidermannMembership Bruce HechtNominations Stephen H. LewisPublications Bernhard Boser

For detailed contact information, see the Soci-ety e-News: www.ieee.org/portal/site/sscs

For questions regarding Society business, contact the SSCS Executive Office.

Contributions for the Spring 2008 issue of the Newsletter must be received by 8 February 2008 at the SSCS Executive Office. A complete media kit for advertisersis available at www.spectrum.ieee.org/mc_print. Scroll down to find SSCS.

Anne O’Neill, Executive Director IEEE SSCSSSCS-West: 1500 SW 11th Ave. #1801Portland, OR 97201Tel: +1 732 981 3400Fax: +1 732 981 3401Email: [email protected]

IEEE Solid-State Circuits Society AdCom

Editor’s Column

Katherine Olstein, SSCS Administrator IEEE SSCS445 Hoes Lane, Piscataway, NJ 08854 Tel: +1 732 981 3410 Fax: +1 732 981 3401Email: [email protected]


Winter 2008 IEEE SSCS NEWS 3

Photo by Michiko Sunami. From left, Kiyoo Itoh,

Hideo Sunami, Robert H.Dennard, Mitsumasa

Koyanagi.

Winter 2008 Volume 13, Number 1

Editor’s Column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2President’s Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Introducing Tony Harker, Associate Editor for Europe/Africa . . . . . . . . . . . . . . . . . . .4Letters to the Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81Corrections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

40

62

75

EDUCATION HIGHLIGHTSTurning Students On to Circuits, Yannis Tsividis . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

TECHNICAL LITERATURERevisiting “Evolution of the MOSFET Dynamic RAM – A Personal View,”Robert H. Dennard, reprinted from IEEE Transactions on Electron Devices, 31(11):1549-1555, November 1984 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Field-Effect Transistor Memory (U.S. Patent No. 3,387,286) R. H. Dennard, 1968 . . . . . . 17The History of DRAM Circuit Designs – At the Forefront of DRAM Development, Kiyoo Itoh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27In Quest of the Joy of Creation, Kiyoo Itoh, reprinted from “Innovate the Future,”2005 Hitachi Hyoron Special Edition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31The Stacked-Capacitor DRAM Cell and Three-Dimensional Memory, Mitsumasa Koyanagi, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37The Role of the Trench Capacitor in DRAM Innovation, Hideo Sunami . . . . . . .42The Remarkable Story of the DRAM Industry, Randy Isaac . . . . . . . . . . . . . . . . .45DRAM - A Personal View, R. C. Foss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

PEOPLEAsad Abidi Recognized for Work in RF-CMOS, Anne O’Neill . . . . . . . . . . . . . . . . . . . . . .57R. Jacob Baker Honored at FIE Conference in October . . . . . . . . . . . . . . . . . . . . . . . . .59Van der Spiegel Acclaimed for Educational Innovation at IEEE EAB Meeting,Katherine Olstein . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60Lanzerotti Applauded for Editorship of LEOS Newsletter . . . . . . . . . . . . . . . . . . . . . . . . .62SSCS Distinguished Lecturers Visit Athens and Varna . . . . . . . . . . . . . . . . . . . . . . . . . . . .62Betty Prince Talks in Brazil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64New Senior Members . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64Call for Fellow Nominations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64Tools: How to Write Readable Reports and Winning Proposals: Part 5, Peter and Cheryl Reimold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

CONFERENCESISSCC 2008 to Focus on System Integration for Life and Style, Bill Bowhill . . . . . . . . . . .66Invitation from the ISSCC 2008 Technical Program Chair, Yoshiaki Hagihara . . . . . . . .68VLSI-TSA and VLSI-DAT to Convene on 21-25 April in Hsinchu, Taiwan, Clara Wu . . . . .69Mm-Wave CMOS Applications: A Report from a CSICS Panel, Anne O’Neill . . . . . . .70

CHAPTER NEWSSSCS-Germany Cosponsors SAMOS 2007, Holger Blume . . . . . . . . . . . . . . . . . . . . . . . .71Sakurai and Razavi Visit SSCS-Seoul . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7218th VLSI Design/CAD Symposium Cosponsored by IEEE Taipei & Tainan, C. C. Wang .72Murmann and Razavi Visit SSCS-Taipei . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74230 Papers Represent Intennational Community at ASICON 2007 . . . . . . . . . . . . . . .75Ian Galton Speaks on Fractional-N PPLS at SSCS-CAS/Atlanta, Gabriel Rincon-Mora . .76Academia and Industry Interact in Ireland, Peter Kennedy . . . . . . . . . . . . . . . . . . . . .78Eight Technical Meetings in Fort Collins, Alvin Loke . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80SSCS Far East Chapters Meet in Jeju, Korea . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

NEWSFiez, Kuroda, Nauta, Sevenhans & Soyuer Elected to AdCom . . . . . . . . . . . . . . . . . . .82CEDA Celebrates Second Anniversary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85Keep Your Professional Edge with Innovative Courses from IEEE . . . . . . . . . . . . . . . . .8881

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President’s MessageRichard C. Jaeger, Auburn University, [email protected]

My two-year term as Presidentof the IEEE Solid-State Cir-cuits Society is nearly at an

end. Thanks to the efforts of ourmembership, staff, and volunteers,the Society continues to strengthenand expand its international activities.Our conferences are attracting recordnumbers of paper submissions andattendees. The Journal of Solid-StateCircuits sees strong submissions, andthe Journal’s papers continue to havesome of the highest download ratesfrom IEEE Xplore. The number ofSSCS chapters and their activities areat a record level. By the end of 2007,SSCS financial reserves are also pro-jected to be at a record level.

We all should be thankful for the

exceptional efforts of Anne O’Neill,Executive Director of the Society,and Katherine Olstein, SSCS Admin-istrator, who ensure smooth day-to-day operation of the society and sup-port the President in ways that aretoo many to enumerate. I thank PastPresident Steve Lewis for his alwaysconsidered advice and insight, and Ialso want to acknowledge the manycontributions of the members of ourAdministrative Committee and Sub-committees. Finally, the past twoyears have seen outstanding devel-opment of the content of theNewsletter through the hard work ofAnne, Katherine and technical Editor,Mary Lanzerotti.

As of January 1, 2008, Willy

Sansen, Professor at KU Leuven,Belgium, and Director of ESAT-MICAS, becomes SSCS President.Professor Sansen is well knowninternationally for his work in ana-log circuits and has been involvedwith a wide range of SSCS activitiesincluding Society Vice President andChair of the 2002 ISSCC.

Our Society will be in good handsunder Willy’s leadership.

Richard C. Jaeger

Outgoing President

New Recruit to the SSCS Editorial TeamTony Harker, ISLI Alba Centre, [email protected]

Hello Everyone

As the newest recruit to the SSCSNews Editorial team, I’d like tointroduce myself and give you someideas about the subject areas I willbe addressing in future issues.

I am Tony Harker, Chief Execu-tive of the Institute for System LevelIntegration (ISLI) in Livingston, atown situated between Scotland’scapital city, Edinburgh, and itslargest city, Glasgow. Livingston hasbeen home to a number of elec-tronics companies since the 1970sand is commonly known as SiliconGlen.

ISLI positions itself as a bridgebetween academic and commercialworlds, promoting and encouragingtechnology transfer and collabora-tive research. One of our main char-ters is the provision of postgraduateeducation with our partners – theinformatics, computing science andelectronic engineering departmentsof the Scottish universities of Edin-burgh, Glasgow, Strathclyde andHeriot Watt. Academic staff fromeach institution work together to

support, supervise and deliver Mas-ter’s and PhD--level programmes atour campus in Livingston.

ISLI also has its own researchgroup specialising in integrated sili-con MEMS, and a design group,which hold widely ranging engi-neering skills and whose primaryaim is to help promote technologytransfer between academia andindustry. This is a considerable chal-lenge in itself bearing in mind thefrequently diverse driving factorswithin each sphere.

The massive changes to the semi-conductor industry witnessed overthe past decade have left fewunscathed. The UK’s electronicsindustry, including ISLI, has beenrequired to respond and adapt,faced with reduced inward invest-ment from multinationals. Indeedthe apparent new world order offabless suppliers, linked to themega-foundries, plus the rise ofsmall and medium-sized enterprises(SMEs) are filling gaps and provid-ing a new level of challenges tothose tasked with supporting theirendeavours.

Such phenomena are not simplyUK or Europe-wide. The constantdrive for cost-effective develop-ment, the quest for competitivemargins, the need to maintain inno-vation, and the availability of a high-ly educated workforce will continueto drive the commercial world at anaggressive pace. The challenge to usall is how we maintain an adaptableand scaleable response to thesemarket needs.

The trend towards globalisationof resource, the high cost ofembarking on advanced design onthe crest of the silicon wave, time-to-market pressures, and the inher-ent need to mitigate the large anddiverse risks (more than anythingdue to the cost of failure), present aplethora of challenges requiringengineers to think more laterallythan ever before. Gone are the daysof compartmentalised, isolateddesigners; nowadays design engi-neers working with Silicon need towear many different hats, as well asembrace ideas from mechanical orchemical engineering environmentsand the world of business.



The pervasive nature of electron-ics, and its clear underpinning ofalmost all of our leisure and busi-ness lives, accelerates the need tocross-pollinate with other engineer-ing disciplines. Recent examples ofthis include the integration of MEMStechnologies with CMOS control cir-cuits and the addition of RF to sens-ing platforms in the medical world.Huge leaps in available computingpower, offered by ever greater inte-gration in faster and smaller tech-nologies, continues to openavenues for product consolidationand innovative development. Mas-sive digital processing capabilitycoupled with advanced analogueblocks for human interfacing withininnovative encapsulation is the verybasis for many of the devices wenow take for granted. (If anyoneneeds evidence of this just look atthe cell phone in your pocket!)

Perhaps most importantly, wemust not forget the urgent need toharness new energy sourcesthrough innovative scavenging tech-niques. These, coupled with smartand efficient energy managementsystems, will help form the back-bone of new development inportable products in the comingdecade.

Topics such as these, plus associ-ated challenges in supportingdiverse markets, geographical dis-persion of development resources,new and emerging players, and keydriving technologies, will form thebackbone of my plans for articlesthroughout the coming year as Iexplore the vital areas for a success-ful symbiotic relationship betweenacademia and industry.

I sincerely hope you enjoy mymusings and welcome any feedbackyou may have.

Best regards

Tony HarkerAssociate Editor of

Europe/Africawww.sli-institute.ac.ukTel: +(44) 1506 469 300

Fax + (44) 1506 469 301

Tony Harker graduated fromNorthumbria University (formerlyknown as Newcastle Upon TynePolytechnic) with a degree in Phys-ical Electronics in 1983. After gradu-ation, he moved to Scotland andtook up a product engineering rolewith National Semiconductor atGreenock. During his time withNational, Tony moved into IC

design, working in a small group ofengineers in full custom and stan-dard cell telecom development forthe Ethernet market.

After a move to Fujitsu’s ASICdesign group in Manchester, Eng-land in 1989 Tony spearheadedadvanced layout techniques in lead-ing edge silicon processes with histeam, and introduced the concept ofIP-based design and development.This culminated in a hugely suc-cessful 25+ ASIC-based system proj-ect for a major European telecomcustomer.

Tony joined Cypress Semiconduc-tor in 2000 to run the UK full customdesign centre. Specialising in globaltechnology, project and productmanagement, he rose to becomeProgramme Director before leavingin 2005 to run the Institute for Sys-tem Level Integration, In his time atISLI, Tony has enhanced the com-mercial face of the organisation,increasing its international profileand its interaction with the UKdesign community.

In his spare time, Tony enjoysspending time with his family, dogsand horse and also the outdoor lifebeing a keen angler and field sportsparticipant.


EDUCATION HIGHLIGHTS


When one compares today’s students to thoseof earlier generations, the differences arestriking. Yet the way most of us teach has

essentially remained unchanged since the middle of thepast century. No wonder, then, that our students are notattracted to electrical engineering or, among those whoare, many are disappointed and just drag along, or evendrop out. In this article we discuss what can be done toturn things around. Parts of this article draw on an ear-lier one on an introductory EE class [1].

Today’s studentsToday’s students differ from those of older genera-tions in several respects [2]:

1. They have not tinkered. Thus, if they get startedin EE through the conventional circuit analysisclass, they have no idea where, in practice, all thetheory fits and why it is needed. In the past,many students had tinkered and could see whythe theory they were being taught was useful.This provided motivation, which is missing today.

2. They are impatient. Today’s students are used toimmediate gratification (exemplified by theirobsessive playing of computer games, wherethey push a button and see “major results” rightaway). Telling these students that they “will seelater in the curriculum” why circuit analysis isuseful, does not work; two semesters down theroad, or even one, is too far into the future forthem. Thus they lose motivation, develop frus-tration and many become passive learners.

3. They think that software is everything. Beingmembers of the computer games generation,today’s students relate to the computer screenextremely well. This is good, but also has a neg-ative side: Students tend to develop the impres-sion that all that needs to be done is press keys,and somebody else, somewhere, will take careof designing and building the hardware.

In view of the above generational differences, itdoes not make sense to keep teaching studentsusing techniques that were appropriate half a cen-tury ago. Doing so risks losing some of the bestminds, or at least turning them off as far as circuitsare concerned.

Efforts to turn things aroundSeveral attempts to turn things around have beenmade in recent years at several universities, all involv-ing a laboratory. Many universities have tried a soft-ware-oriented first lab; this can be about multimedia,or it can use software packages as aids to teach sig-

nal processing or control systems. This approach canprovide immediate gratification, but it fails to addressproblems #1 and #3 above; in fact, it reinforces #3. Ifthe first engineering courses students see are soft-ware-oriented, by the time they get to hardware it istoo late to make them relate to it well. What is need-ed is a course with real contact to the real world,using a real (not a virtual) laboratory. Our chance todo something, before the students get turned off withcircuits, is the first circuits lab.

Approaches to the first circuits labAbout ten years ago, we noticed a worrying down-ward trend in our enrollment; more and more engi-neering students were opting for different depart-ments. We looked into this problem, and found thatits cause was the fact that we were not addressing theneeds of today’s students, as outlined above. A keyproblem was our first circuits lab, which was run theclassical way: it involved dry instructions whichserved to teach measurement techniques and to veri-fy the theory. This reinforced the general impressionout there that engineering is not fun, and failed tomotivate students. It also did not allow them to becreative. In other words, our first circuits lab waswasting a unique opportunity to excite today’s stu-dents about electrical engineering in general, and cir-cuits in particular. We decided to turn things around;we begun by looking at approaches elsewhere thatdeparted from the classical approach.

One approach we saw was to run the lab concur-rently with a theory class, and have students gradu-ally build a large system, usually based on a kit, withthe end result achieved at the end of the term. Thisapproach is certainly better than the classical one asfar as motivation is concerned. Unfortunately, we didnot find it easy to make such a lab compatible withthe order in which we wanted to present the theoryin class; this would have required tight coordinationbetween different instructors, who in fact changedfrom year to year, and was not practicable. Even ifwe offered this lab in the semester following the the-ory class, the need to tie all individual experiments toone specific application was over-constraining forour purposes; we did not find this the best vehicle forillustrating the many different concepts in our firstcircuits class.

In another approach elsewhere students assembledsimple circuits using kits, before they had a theoryclass or, in some cases, with accompanying short lec-tures1. However, we could not afford to introduce anextra term of circuits in order to accommodate thisapproach, since in our curriculum, as in those else-where, circuits classes had already been squeezedinto a small number of terms. And, such a class couldnot replace a classical circuits class; although the“light lab” approach can be fun and can serve a use-

Turning Students On to CircuitsBy Yannis Tsividis, Department of Electrical Engineering, Columbia University New York, NY, [email protected]

© 2008 IEEE




ful purpose, for us it did not adequately relate prac-tice to theory, and was not a substitute for a realteaching lab.

A teaching lab that excites and motivatesFollowing our study of the alternatives, we set out tocreate a lab that would retain their advantages with-out their drawbacks. From the beginning, our goalwas to do this in a most general way, so that hope-fully our approach would stand a chance of beingadopted elsewhere as well. It soon became evidentthat the best solution was a mix of the modern andthe classical. Our goal was to get the students to tin-ker while understanding the links of practice to theo-ry, and to provide them with rewarding lab experi-ences that would excite and motivate them. The labwe ended up with has the following features:

Experiment independence: We found that it is best atthis level to keep the experiments largely independent(as opposed to their being part of a larger construc-tion project culminating at the end of the term). In thisway we had great flexibility in designing the experi-ments, in order to reinforce certain important con-cepts. This makes the lab compatible with a variety ofcurricular formats used at various institutions. Theexperiments are as follows:

1. Measuring DC voltages and currents2. Simple DC circuits; resistors and resistive sensors3. Generating, observing and hearing time-varying

signals4. Basic characteristics of op amps and comparators

D1. Mini design project5. Amplifier design using op amps; a sound system6. RC circuit transients; more on measurement

techniques7. Filters, frequency response, and tone control8. LC circuits, resonance, and transformers9. Diodes and their applications10. Modulation and radio reception - Final design

projectD2. Final design project

The above experiments can be done based onknowledge provided in any “Circuits 101” class,except for the diodes, which are fully covered in thelab manual. Diodes are introduced for two reasons:They drive the point home that not everything in cir-cuits is linear; and they make for interesting experi-ments, such as radio reception, that help reinforceother topics. The experiments involving diodes can beskipped if desired.

The following experiments are included in the man-ual, and can be used, along with some of the above,in electronics classes or in classes that mix circuitswith electronics:

11. MOSFET characteristics and applications12. Principles of amplification using MOSFETs13. Bipolar transistors and amplifiers14. Digital logic circuits; gates and latches15. D flip-flops and shift registers16. JK flip-flops and ripple counters

Extra equipment: In addition to the usual oscillo-scope, signal generators, multimeters, and power sup-plies, a few more pieces of equipment are an integralpart of the lab stations: a microphone, a CD/MP3 play-er, a small power amplifier, and a loudspeaker. SeeFig. 1.

Fig. 1. Audio in the first circuits lab. A microphone, aCD/MP3 player, a small power amplifier, and a loudspeak-er are standard equipment in each station.

Emphasis on reality: The lab reinforces the point thateverything the students do in it is real and useful, byhelping them relate what they measure to their sens-es. Thus for example, they do not just observe wave-forms on the oscilloscope screen, but also hear themthrough a power amplifier. They do not obtain thesewaveforms only from a signal generator; instead,using a microphone, they observe the waveforms oftheir voice, whistling, and clapping. They are evenasked to remove the loudspeaker’s panel, feel thevibrations of the speaker’s cone for various frequen-cies and amplitudes, and finally lay the speaker flat,remove its front panel, and observe how a small par-ticle bounces when placed on the vibrating cone. Thismay sound overdone, but those of us who where hob-byists at a young age know that such experiences stayin memory, and help make things click; they help stu-dents relate to their experiments, increase intuition,and motivate further study.

Emphasis on applications: Because the experimentsare largely independent, many different types of appli-cations could be woven into them. For example, inExperiment 2 on resistors, we take the opportunity tointroduce resistors that are sensitive to temperature(thermistors) and light (photoresistors). Thus, sensorsare introduced very early on. Students see more trans-ducers (microphones and loudspeakers) in Experi-ment 3. In Experiment 4 they see yet another trans-ducer (an LED), and they learn how to turn it on fromthe output of a comparator. Similarly in other experi-

1 Recently, in some schools this approach has even been taken up

by the students themselves [3,4]. If that does not give us the mes-

sage that students are crying for a change in the way they are

taught, I don’t know what will!




ments; they do not just measure the gain of an opamp/resistor amplifier, but they use it to amplify theirown voice signal and listen to it. They do not justmeasure the frequency response of RC circuits, butapply these circuits to tone control, using them toprocess music from their favorite recordings stored ontheir iPods or CDs, and listen to the result. After hav-ing studied diodes, LC circuits, amplifiers, and theirapplications, they are asked to put these together tomake a simple radio receiver, shown in Fig. 2. This,for them, is obviously a large system, and they canspend a couple of frustrating hours in making it work;but in the end, when they receive their first station,the effect on them is palpable. The coupling to appli-cations also serves to motivate students to take class-es in other subjects; for example, the radio receiverexperiment points to classes in communications.

Design projects: Thanks to the experiment independ-ence mentioned above, mini design projects can beintroduced very early. For example, in the 5th weekstudents are asked to come up with a specified sys-tem that does something useful, e.g. a “night lamp”that turns on when the light intensity in the room islow. We don’t tell them how to do this. After strug-gling for a couple of hours, and with discreet helpfrom the TAs if needed, a spark goes on in theirheads, and they realize that they can combine theknowledge they have already acquired on resistors,photoresistors, comparators and LEDs to make thistask possible. This is a unique moment in their edu-cation, and it has a lasting effect on their motivationfor further study in this and other classes. A muchmore extensive, final project completes the class. Stu-dents can choose from a list of suggested projects, orcan propose their own design project.

Balance between freedom and guidance: A complete-ly regimented approach stifles creativity and does notensure learning; it is entirely possible for a student toblindly follow instructions and leave the lab withouthaving really understood much. To avoid this, a cer-tain amount of freedom must be allowed. On theother hand, complete freedom is not appropriate, asmany students do not know how to begin andbecome stuck very often. Thus we opted for a com-promise, which works best for the large majority of

students. There are steps to be followed in eachexperiment, but parts of the story are withheld, andthe students are required to search for these partsthemselves. “What if” questions are used often for thispurpose. For example, in Experiment 5 the studentshave verified that the loudspeaker converts electricityto sound. They are then asked, could the loudspeak-er perhaps be used to do the opposite, i.e. convertsound to electricity? They thus have to set up anexperiment to find out. This brings up in their mindthe issue of energy conversion reversibility in trans-ducers, and encourages them to experiment.

Throughout the lab, we have avoided large circuitsand complicated equations, which at this stage wouldonly serve to cloud things. There is room for those infollow-up classes and labs. In the first lab, it is best toconcentrate on exciting students, giving them intu-ition, and making them look forward to such classes!In the end, students who have gone through this firstlab tend to relate to both practice and theory better.Motivation is the key.

The experiments described above have been fine-tuned over repeated trials, and the lab now practical-ly runs itself. The resulting manual has been pub-lished [5]. An effort has been made to make this man-ual appropriate for a variety of situations, and tomake it easy for colleagues elsewhere to reproducethis lab. A companion Web site [6] contains detailedinformation on how to set up the lab, how to run it,where to get the parts, how to fool-proof the equip-ment, ideas for design projects, etc.

As already mentioned, before this class was intro-duced at Columbia, we were losing students to otherdepartments at an alarming rate. Three years later,thanks to the introduction of this lab, our enrollmenthad doubled. We found that students who took thislab did better in follow-up classes, and not only onesin circuits; we attribute this to the motivational aspectof the class. Some quantitative results are given else-where [1]. The students’ comments, collected anony-mously by the Dean’s Office and communicated to theEE department over the years, have been very positiveand include “Thank you for this great experience” ,“Lab very useful’’, “Every department should have aclass like this”, “I learned a lot and feel prepared forthe rest of my major”, “Labs were great - very helpfulin understanding the material”, “Labs are very helpful

Fig. 2. RF in the first circuits lab. Before building this radio receiver, students have studied each of the three blocksshown in broken lines in separate experiments on resonant circuits, diode applications, and op amp circuits.



EDUCATION HIGHLIGHTSin familiarizing students with …the concepts from thelecture”, “The lab was excellent”, “The lab manual isexcellent”, “The lab session is great - helps you gethands on knowledge of the topics you learn”, “For thefirst time I felt that the lab actually reinforced the sub-jects taught in class”, and “I even...dare I say it...enjoyed... the lab portion of the class”.

A variety of settings for this labThe lab described above has been adopted in a vari-ety of settings at several universities. For example,at Princeton it is offered concurrently with the firstcircuits analysis class in the sophomore year; thesame for the University of Connecticut, which pro-vides a good example of how the lab can be syn-chronized with lectures using a standard circuits text[7]. At San Diego State University the lab accompa-nies the first electronics class in the junior year. AtColumbia, we run this lab as part of a first-year classin circuits and electronics. Caltech is planning tointroduce this lab into their curriculum starting thisfall [8].

ConclusionsToday’s students can be turned on to circuits if thefirst lab they take is exciting and motivating. Thisarticle describes an approach to achieving this. Inaddition to illustrating the many concepts taught intheory classes, this approach couples experimentsto applications, and encourages students to tinkerand explore. We found that a proper mix of themodern and classical approaches gives excellentresults. The most unambiguous indication of suc-cess for us has been seeing the students’ face lightup when their designs work for the first time, andhearing them say that this lab made them realizethat EE is for them. Motivating students in this wayis especially important in view of the recent trendtowards decreasing EE enrollments.

This author would be happy to provide more detailsto instructors who are implementing, or are consider-ing implementing, this lab at their own institution. Hecan be e-mailed at [email protected].

References[1] Y. Tsividis, “Teaching circuits and electronics to

first-year students”, Proc. 1998 IEEE Internation-al Symposium on Circuits and Systems, vol. 1,pp. 424-427, Monterey, May/June 1998.

[2] R. A. Rohrer, “Taking circuits seriously”, IEEE Cir-cuits and Devices, vol. 6, no. 4, pp. 27-31, July1990.

[3] “Students Create Hands-On Electrical Engineer-ing Course”, The Institute Online, http://www.theinstitute.ieee.org, 5 January 2007.

[4] “Student Branches Boost Membership with Hands-On Projects”, The Institute Online, http://www.theinstitute.ieee.org, 5 October 2007.

[5] Y. Tsividis, A First Lab in Circuits and Electron-ics, John Wiley and Sons, New York, 2002.

[6] http://he-cda.wiley.com/WileyCDA/HigherEdTi-tle/productCd-0471386952.html

[7] http://www.engr.uconn.edu/ece/crsdata/210sy01.pdf[8] Prof. A. Emami-Neyestanak, Caltech, private commu-

nication.

About the AuthorYannis Tsividis received the B.S. degreefrom the University of Minnesota, Min-neapolis in 1972, and the M.S. and Ph.D.degrees from the University of California,Berkeley in 1973 and 1976, respectively.He is Charles Batchelor Memorial Profes-sor at Columbia University in New York.His research has been in analog and

mixed-signal MOS integrated circuits at the device, circuit,system, and computer simulation level, starting with thefirst fully-integrated MOS operational amplifier in 1975. AFellow of the IEEE, he has received the 1984 Baker PrizeAward for the best IEEE publication and the 2007 IEEEGustav Robert Kirchhoff Award, and was co-recipient ofthe 2003 ISSCC L. Winner Outstanding Paper Award. Hereceived Columbia’s Presidential Award for OutstandingTeaching in 2003, and the IEEE Undergraduate TeachingAward in 2005.


TECHNICAL LITERATURE


Revisiting “Evolution of the MOSFET Dynamic RAM– A Personal View”I am very pleased to have my 1984 paper reprinted here in this "DRAM" issue of SSCS News. It is a greathonor for it to be included here with original papers from several authors who have made very significantcontributions to the advancement of DRAM.

I want to explain why I wrote this paper in the first place. It was invited for the CENTENNIAL SPECIALISSUE of IEEE Transactions on Electron Devices, commemorating the 100th anniversary of the founding ofIEEE. That was very special to be among a dozen authors chosen to describe the history and future prospectsof some important developments in electronic devices. I remember that I was given very little time to writethis paper, and I was very pleased that I was able to pull it together and let it flow out with very little editing.

On rereading my paper, I feel it is a good history of the early days of semiconductor memory development,and it explains as clearly as I can how my invention of DRAM came about. However, I have done a little morework since then to delineate what the capability of magnetic-core memory was at the time of my invention ofDRAM in 1967. I found that the largest IBM mainframes had 1MB of memory with an access time of 1-2 microsec-onds, and apparently dissipated 40kW of power according to the data in Ref.1 of the reprinted paper. (Hardlywhat one wants to have in their PC.) That is in sharp contrast to the capability of DRAM even in it’s infancy inthe middle 1970s, which certainly led to the rapid growth in personal and portable computers thereafter.

The history of DRAM development up to 1984 is based on what I knew personally and was able to find ref-erences for. It only touches some highlights. There were a lot of technology, circuit and architectural advancesin the very competitive environment of that period, with only a little documentation in the public literature.

My final topic of “FUTURE PROSPECTS” in this reprinted paper is a case study in the hazards of predict-ing the future. It does serve as a good reference to the state of knowledge in 1984. As we all know, opticallithography has progressed to give more than ten times smaller features than we expected at that time. Scal-ing of transistors has also gone a lot further. Here the progress was driven by the unexpected robustness ofgate insulators which allowed them to be scaled thinner and operated at much higher electric fields than weever dreamed possible. Moreover, the emergence of CMOS offset (for a while, at least) the dramatic increasein power density associated with this large increase in electric fields.

At this point in time we are finding it very challenging to continue the pace of progress we have enjoyedin the past 35 years or so. I now know better than to make predictions for the future, but I will repeat thefinal line of my 1984 paper: It should be interesting to look back in 15 more yearsand see what has really happened!

Robert H. Dennard, November 2007




1. IntroductionDynamic random-access memory (DRAM) has beenthe only high-density RAM used for over 30 yearsdespite many attempts to replace it. Still contributingto IT advances, it has achieved an unprecedented six-fold increase in memory capacity in the last threedecades, from the 1-Kbit level in 1970 to the 1- to 4-Gbit level today, as shown in Figure 1 [1]. Such rapidprogress, however, would have been impossible with-out the implementation of many inventions and inno-vative technologies and the efforts of many talentedpeople. The one-transistor one-capacitor cell (the 1-T cell) invented by Robert Dennard [2], and support-ed by his scaling theory [3], has played a key role.Over my career, I have also contributed to thisprogress by being fully involved in developingDRAM technologies.

The first production of semiconductor memoryannounced by Intel and IBM in 1970 had a profoundimpact on my research at Hitachi Ltd. On the side, Ibought the hottest DRAM samples and evaluatedthem to judge how DRAMs would impact Hitachimainframe computers, while still being involved inmagnetic memory device/system design. Eventually,however, I was forced to change my research fieldfrom magnetic thin-film memory to semiconductormemory. This change was so exceptionally suddenand difficult, I felt like a victim of fate. Looking back,however, I realize how fortunate I was to have wit-nessed such an advancement of DRAMs. In any event,I started my career as a DRAM designer at the end of1972 with a 4-Kbit DRAM. Then, as the lead designerof the first prototype for each of eight successive gen-

erations of Hitachi DRAMs ranging from 4- Kbits to 64Mbits, I was constantly faced with the challenge ofbreaking through the limits on each consecutive gen-eration. Fortunately, we eventually overcame the dif-ficulties with our best efforts. It is quite impressivethat such painful and struggling developments cannow be plotted as a smooth line on a graph like thatshown in Figure 1.

This paper describes the history of DRAM circuitdesigns from its advent in 1970 to the present, basedon my career at the forefront of DRAM development.More detail can be seen in references [4, 5].

2. In the Cradle of DRAM (1970s)The 1970s was a decade in which MOS DRAMbecame firmly established as the technology for mainmemory, and also became the MOSFET technologydriver. The dawn of the LSI era using MOSFET tech-nology came in 1970, marked by the launch of the 1-Kbit DRAM, named 1103 by Intel Corporation. At thattime, it was anticipated that magnetic memory, whichhad a large slice of the memory market, would even-tually be replaced by DRAM. In the race to developDRAM, companies enthusiastically aimed at develop-ing products that would bring them wealth and suc-cess. However, it would not be until the mid-1970sthat such products would start appearing on the mar-ket. It was normal in those early years to find a kalei-doscopic variety of product specifications and tech-nologies provided by various manufacturers. Forexample, in the 1-Kbit generation, utilizing the highspeed of n-channel MOSTFETs (nMOSTs) a manufac-turer used a memory cell with four nMOSTs. In con-trast, utilizing the low leakage of p-channel MOSFETs(pMOSTs), despite their slow speed, Intel used amemory cell with three pMOSTs. However, nMOStechnology at that time had not matured, and pro-duction of this memory cell eventually halted due toan uncontrollable leakage problem in the cell. More-over, samples were never released on time, and whenthey finally were released and evaluated, they werefound to have a narrow voltage margin. In 1974,when nMOS 4-Kbit DRAM was starting to be devel-oped, once a manufacturer switched to the 1-T celloffering a higher density, other manufacturers thenimmediately followed. Doubts soon began to ariseabout using this underdeveloped technology as aresult of its problems, even though a method usinga cross-coupled differential sense amplifier forsensing/restoring had been presented at the 1972ISSCC [6].

In fact, sophisticated technology was necessary forthe stable operation of the 1-T cell due to the cell’s

The History of DRAM Circuit Designs —At theForefront of DRAM Development—Kiyoo Itoh, Hitachi Ltd., [email protected]

Figure 1. Trends in the memory cell size and memorycapacity of DRAMs [1].

© 2008 IEEE




inherent features [5]. This is the case even for modern1-T-cell DRAMs using a half-VDD bit-line (BL)precharging scheme and a cross-coupled CMOS senseamplifier, as shown in Figure 2.

After precharging BLs at VDD/2, the word-line (WL)is activated so that a signal voltage (vS) is developedon the floating BL, as a result of charge sharing of thecell node and BL. Unfortunately, it is small (usually100-200 mV) despite a high VDD (1-5 V) because thecell capacitance (CS = 20-50 fF) is much smaller thanthe BL capacitance (CB = 50-600 fF). A small CS and alarge CB result from the need for a small cell size andfor connecting a large number (128-512) of cells to aBL, respectively. In addition, the signal voltage isfloating. Thus, the operation is susceptible to noise. Inany event, the original voltage (VDD or 0 V) at the cellnode collapses to around VDD/2. The destructivereadout characteristics thus necessitate successiveamplification and restoring. The circuit for the opera-tions must be simple enough to be laid out within thesmall pitch of BLs while minimizing noise generationfrom the circuit itself. In fact, for modern DRAMs it isthe CMOS sense amplifier that meets the requirement.Here, the amplification and restoring are simultane-ously performed on many BLs along the WL at a largevoltage swing of VDD/2, thus causing various kinds ofnoise in the memory-cell array via parasitic capaci-tances during the operations. In the early 1970s, cir-cuit and noise-reduction techniques to cope with theproblems were not available.

Just as feared, the resulting samples were not sat-isfactory for users. After many disappointments, itwas not until the 16-Kbit generation, between 1976and 1978, that the first acceptable samples appeared.Also, specifications were standardized (for example,the package pin-count was decreased from 22 to 16)and a considerable number of technologies were dis-carded. Consequently, the 1-T cell using double poly-silicon layers [7], low-power dynamic circuit configu-rations for logic gates and sense amplifiers [8], andthe address-multiplexing scheme (halving the

address package pin-count) [7] became standard.Despite these steps forward, in 1978, the so-called“soft-error problem” (i.e., non-destructive failures ofmemory cells caused by alpha-particle irradiation orcosmic-ray irradiation) was revealed [9]. Even thougha chip coating with polyimide and the purification ofrelevant materials partly resolved the problem, fur-ther technological development was needed. In addi-tion, from the user viewpoint, the use of three exter-nal supply voltages (12, 5, and –5 V) remainedunwieldy.

3. In the Rush of Innovative DRAM Technologies(1980s) The 1980s brought an era in which proposals ofbreakthrough DRAM technologies were rushed, andthe DRAM market was drastically larger than in theprevious decade. During the 64-Kbit generationaround 1980, there were major advancements inproduct specifications and technologies, and theabove-mentioned three power supplies were replacedby a single 5-V power supply [10] by using an on-chipsubstrate bias generator. The folded-bit-line (BL)arrangement invented by K. Itoh [11] in 1974 (the de-facto standard cell nowadays) was introduced inorder to cancel array noise. In the conventional open-BL arrangement, two BLs in a pair connected to a dif-ferential sense amplifier are implemented separatelyon two array conductors (see Fig. 3(a)), causing elec-trical imbalances between the lines. Moreover, if volt-age bounces at the conductors are different, differentvoltages are coupled to the BLs via conductor-BL par-asitic capacitances. Consequently, a differential noisethat cannot be cancelled by the amplifier is generatedbetween the pair of BLs. On the contrary, in the fold-ed-BL arrangement, shown in Fig. 3(b), the two BLsrun close to one another and are parallel on the sameconductor, enabling the same voltage to be coupledto the BLs and thus cancelled by the amplifier.

In the following 256-Kbit generation, “bootstrapping”and the redundancy technique [5] were rapidly accept-

Figure 2. The read, amplification, and restoring of the 1-Tcell. The signal voltage (vS) is discriminated and amplifiedwith another BL as a reference. The amplified signal isthen restored at the cell node (N). vS = (VDD/2)CS/(CS + CB).

Figure 3. Configurations of (a) open BL arrangement and(b) folded-BL arrangement. SA; Sense amplifier, Y; Columnselect-line, I/O; Common data-in- and data-out-lines.



TECHNICAL LITERATUREed throughout the industry. During this generation,around 1985, prices of DRAMs collapsed because offierce competition. Despite this problem, however,technical developments continued apace [5]. In particu-lar, a partial activation of multi-divided BLs for low-power array, a highly reliable pMOST-output word driv-er, and a half-VDD capacitor plate for doubling cellcapacitance were introduced. Another significant intro-duction was a half-VDD BL precharging scheme [5] forreducing power dissipation and array noise and for pro-viding stable sensing without problematic dummy cells.Moreover, a milestone was the on-chip voltage down-converter (VDC) scheme [5, 12], which ensured reliabil-ity in scaled devices while reducing power dissipationand maintaining an external power supply for severalgenerations. The details follow.

Standard power-supply voltage is dictated by systemsupply, which is not scaled down fast enough to equaladvances in device miniaturization. Therefore, a voltage-down converter (see Fig. 4) that can bridge the supplygap between the system and internal core-circuit devicesneeds to be integrated on the chip. The converter canadjust the converted voltage (VDL) in accordance withthe breakdown voltage lowering of the ever-miniatur-ized devices, while maintaining the external power sup-ply voltage (VDD) for several generations. In practice, theaging (or burn-in) stress test, which enables us to quick-ly remove potential defects by applying a high stressvoltage and high temperature, must be made possibleby raising the VDD above the normal operation voltage.The VDC was proposed for a 1-Mbit nMOS DRAM [12]in 1984. However, after taking into consideration theloop stability of the DRAM load that dynamicallychanges at a large voltage swing, the VDC could suc-cessfully be implemented in 16-Mbit DRAM products inthe early 1990s. Nowadays, the VDC has become anindustry standard for DRAMs as well as for microcon-trollers. Another milestone in the 1980s was the use ofCMOS technology, which enables us to use simple andlow power circuits. Although the concept of CMOSDRAM [13] was proposed in 1980, it was not industrial-ized until the late 1980s for 1-Mbit DRAMs. CMOS tech-nology has since been indispensable.

4. Toward High-Speed and Low-Voltage DRAMs(1990s-present)In the early 1990s, a major transition once again tookplace in the 4-Mbit generation with the introductionof vertical trench and stacked capacitors [5]. Bothcapacitors were, and still are, indispensable for pro-viding a large signal voltage with a large cell capaci-tance, although there had been controversial argu-ments about their performance and scalability. Mem-ory capacity continued to grow due to high-densityfabrication process technology guided by Dennard’sscaling theory. After memory capacity at the researchand development level reached the 1-4Gbit level inthe mid-1990s, however, high speed with doubledmemory capacity per generation became the focus forthe development of DRAM, rather than increase inmemory capacity by quadrupling it in each genera-tion. This focus resulted from the need for a smallincrement unit of memory capacity in PC systems,bridging the more prominent DRAM-processor per-formance gap, lower bit cost, and shorter lead-timerequired for advanced process technology. The resultof these changes was the emergence of high-through-put DRAMs [5], as exemplified by a pipe-lined DRAM,block transfer oriented protocol DRAM (the so-called“Rambus DRAM”), and synchronous DRAM (SDRAM).Driven by increasing system clocks and scaleddevices, high-throughput DRAM progress has contin-ued into the 21st century. Pipe-lined/interleaving tech-niques with multi-bank, high-speed low-voltageswing I/O interfaces and wide I/Os combined withhigh-density packaging, a double data rate (DDR)technique that aligns read data at both edges of theexternal clock, a delay-locked loop (DLL) that alignsdata with the external clock, and even on-chip termi-nation have all been widely used in high-speedDRAM products. Consequently, by the end of 2007,DRAM evolved to a 1.5-V 1.6-Gbit/s/pin (800-MHzclock) 1-Gbit DDR SDRAM using an 80-nm triple-metal dual-gate poly CMOS process [17].

Even in the 1990s, DRAM was the technology driv-er of low-voltage CMOS circuits. The early 1990s sawthe advent of low-voltage (≤1.5 V) CMOS circuits. Y.Nakagome et al. [14] pioneered the development oflow-voltage CMOS LSIs with a 1.5-V 50-ns 64-MbitDRAM. This was landmark work because the chipwas not only the first 64-Mbit DRAM but also the first1.5-V DRAM when 5 V was still the standard powerbeing used. The 1.5-V DRAM was a major innovation,driven by a growing interest in portable and battery-operated systems. This DRAM required the use ofmany low-voltage circuits in order to resolve prob-lems pertaining to low-voltage operations. One par-ticular problem (and a major obstacle) was, and stillis, the subthreshold current (leakage). This is becausethe threshold voltage (VT) of MOSTs for low-voltagehigh-speed CMOS LSIs must be lowered by scalingdown the MOSTs and lowering their operating volt-age, causing an exponential increase in the leakage(i.e., the current flowing between the source anddrain even though the gate voltage is lower than VT).The resultant leakage currents flowing even in CMOS

Figure 4. (a) On-chip voltage down-converter scheme, and(b) aging (burn-in) test with a high stress voltage [5].




circuits unacceptably increase the stand-by current ofa chip. Eventually, leakage dominates even the activecurrent, as expected in Figure 5 [15], resulting in a lossof the low-power advantage of CMOS circuits that wetake for granted today. Simple and effective schemes[1, 5] to reduce leakage are to back-bias the MOST invarious ways, such as the offset gate-source drivingand stacking of the switched-source impedance (SSI),and use of the power switch. In particular, the SSI ismost suitable for a memory chip consisting of largenumber of iterative circuit blocks that dominate thetotal active leakage of the chip. As early as 1993,the SSI was expected to reduce the active current ofa hypothetical 1.0-V 16-Gbit DRAM [15] dominatedby leakage to one-tenth (1180 mA to 116 mA).Although these schemes were all proposed byDRAM designers, they have made a strong impacton subsequent developments of SRAMs and logiccircuits in MPUs [16]. Lower-voltage DRAMs, how-ever, are facing a challenge, as in other LSIs. Thisis the variability problem (e.g., speed variationsdue to VT variations in a chip) that will becomemore prominent with device miniaturization, espe-cially for many sense amplifiers consisting of smallflip-flops.

A recent movement can also be seen in develop-ments of high-density DRAM cell structures aiming atthe 4F2 area (F = device feature size) instead of con-ventional 6-8F2 cells. This trend is being driven by theobjective of reducing bit cost as device scalingbecomes more complicated and expensive for deep-sub-100-nm technologies. A good example is thefloating-body silicon-on-insulator (SOI) one-transistorgain cell accepting logic compatible process [18]. TheSOI cell consists of an nMOST built on a partiallydepleted SOI. The floating body is used as an electri-cal charge storage node.

5. ConclusionIn summary, DRAM has enabled us to fabricate com-puters, handheld equipment, and almost everythingwith electrical components with a dramatically lowbit-cost and high performance. But how about thefuture? Can we overcome problems such as the ever-more difficult fabrication process and the variabilityissue in the deep-sub-100-nm era? How and when canwe get the 4F2 DRAM cell? Moreover, how far can wego with the 1-T cell? Nobody knows for sure. But thatis what makes integrated circuit research and devel-opment so exciting [19].

References[1] K. Itoh, M. Horiguchi, and H. Tanaka, Ultra-Low-Voltage Nano-

Scale Memories, Springer, Aug. 2007. [2] R.H. Dennard, USP-3387286, June 4, 1968. [3] R.H. Dennard, F.H. Gaensslen, H.N. Yu, V.L. Rideout, E. Bas-

sous, and A.R. LeBlanc, “Design of Ion Implanted MOSFET’swith Very Small Physical Dimensions”, IEEE J. Solid-State Cir-cuits, Vol. SC-9, pp. 256-268, Oct. 1974.

[4] L.M. Terman, “Memory at ISSCC”, ISSCC Commemorative Sup-plement to the Digest of Technical Papers, pp.91-111, Feb. 1993.

[5] K. Itoh, VLSI Memory Chip Design, Springer-Verlag, NY, 2001.[6] K.U. Stein, A. Sihling, E. Doering, “Storage Array and

Sense/Refresh Circuit for Single-Transistor Memory Cells”, ISSCCDig. Tech. Papers. pp. 56-57, Feb. 1972.

[7] C.N. Ahlquist, J.R. Breivogel, J.T. Koo, J.L. McCollum, W.G. Old-ham, and A.L. Renninger, “A 16K Dynamic RAM”, ISSCC Dig.Tech. PapersÅCpp. 128-129, Feb. 1976.

[8] P.R. Shroeder and R.J. Proebsting, “A 16Kx1 Bit Dynamic RAM”,ISSCC Dig. Tech. Papers, pp. 12-13, Feb. 1977.

[9] T.C. May, M.H. Woods, “A New Physical Mechanism for SoftErrors in Dynamic Memories”, Proc. Reliability Physics Symp.,pp. 33-40, April 1978.

[10] K. Itoh, R. Hori, H. Masuda, Y. Kamigaki, H. Kawamoto, and H.Katto, “A single 5V 64K dynamic RAM”, ISSCC Dig. Tech.Papers, pp. 228-229, Feb. 1980.

[11] K. Itoh, USP-4044340, Dec.29, 1975. [12] K. Itoh, R. Hori, J. Etoh, S. Asai, N. Hashimoto, K. Yagi and H.

Sunami, “An Experimental 1Mb DRAM with On-Chip VoltageLimiter”, ISSCC Dig. Tech. Papers, p. 282-283, Feb. 1984.

[13] K. Shimohigashi, H. Masuda, Y. Kamigaki, K. Itoh, N. Hashimo-to, and E. Arai, “An n-well CMOS Dynamic RAM,” IEDM Dig.Tech. Papers, pp. 835-836, Dec. 1980.

[14] Y. Nakagome, Y. Kawamoto, H. Tanaka, K. Takeuchi, E. Kume,Y. Watanabe, T. Kaga, F. Murai, R. Izawa, D. Hisamoto, T. Kisu,T. Nishida, E. Takeda, and K. Itoh, “A 1.5-V Circuit Technologyfor 64Mb DRAMs”, Symp. VLSI Circuits Dig., Tech. Papers, pp.17-18, June 1990.

[15] T. Sakata, K. Itoh, M. Horiguchi, and M. Aoki, “Two-Dimen-sional Power-Line Selection Scheme for Low Subthreshold-Cur-rent Multi-Gigabit DRAM’s”, IEEE J. Solid-State Circuits, Vol. 29,No. 8, pp. 887-894, August 1994.

[16] G. E. Moore, “No Exponential is Forever: But “Forever” Can BeDelayed!”, ISSCC Dig. Tech. Papers, pp. 20-23, Feb. 2003.

[17] Y.K. Kim, Y.J. Jeon, B.H. Jeong, N.W. Heo, S.B. Chang, H.G.Jung, D.Y. Kim, H.J. Chung, C.S. Kim, S.B. Ko, K.H. Kyung, J.H.Yoo, and S.I. Cho, “A 1.5V, 1.6Gb/s/pin, 1Gb DDR3 SDRAMwith an Address Queuing Scheme and Bang-Bang JitterReduced DLL Scheme”, Symp. VLSI Circuits Dig. Tech. Papers,pp. 182-183, June 2007.

[18] T. Ohsawa, K. Fujita, T. Higashi, Y. Iwata, T. Kajiyama, Y. Asao,and K. Sunouchi, “Memory Design Using a One-Transistor GainCell on SOI”, IEEE J. Solid-State Circuits, Vol.37, No.11, pp. 1510-1522, Nov. 2002.

[19] IEEE Spectrum, p.29, Oct. 2007.

Figure 5 Trends in the estimated active current of DRAMs[15]. IDC; Subthreshold current, IAC; Charging current ofcapacitors, IACT; Total active current. Cycle time = 180 ns, T= 75_C, Subthreshold swing = 97 mV/decade.



TECHNICAL LITERATUREAbout the Author

Kiyoo Itoh received the B.S. and Ph.D.Degrees in Electrical Engineering fromTohoku University, Japan, in 1963 and1976. He is currently a Hitachi Fellow.He was a Visiting MacKay Lecturer atU.C. Berkeley in 1994, a Visiting Pro-fessor at the University of Waterloo in

1995, and a Consulting Professor at Stanford Universi-ty in 2000-2001. He was a Member of the IEEE FellowCommittee from 1999 to 2002, and an elected AdComMember of IEEE Solid-State Circuits Society from 2001to 2003. He is a Distinguished Lecturer of the IEEESolid-state Circuits Society.

Since 1972 he has led low-power/low-voltage RAMcircuits at Hitachi Ltd: He was the lead designer of thefirst prototype for eight generations of Hitachi DRAMsranging from 4-Kbits to 64-Mbits. In the course ofthese developments, in 1974 he invented the conceptof the folded data-line (i.e., bit-line) arrangement,which uses a pair of balanced data lines to eliminatevarious noise components, and presented the archi-tecture for a 64-Kbit DRAM at the 1980 ISSCC. Thisarchitecture has since been adopted for nearly allDRAM chips. He went on to develop high-densityDRAM devices and low-power/low-voltage DRAM cir-cuits and array architectures: triple-well substratestructures, advanced three-dimensional capacitors,pipe-lined DRAMs, on-chip substrate-bias generators,half-VDD sensing, on-chip voltage-down converters

enabling the aging (burn-in) stress test, the PMOSword driver, so-called direct sensing, multi-divideddata-line architectures, transposed data-lines, low-voltage charge pump, and stress-voltage tolerated I/Ocircuits. Many of them have become de-facto stan-dards. In addition, as a pioneer he initiated circuitinventions and developments as early as 1988 toreduce the subthreshold current of MOSFETs even forthe active mode, which is highlighted today in low-voltage CMOS LSI designs. Typical examples of thereduction circuits are multi-threshold (VT) CMOSlogic, various gate-source (self and offset) back-bias-ing schemes, multi-divided power line schemes, andpower switches that we take for granted today.

Dr. Itoh holds over 420 patents in Japan and the US.He has authored four books and three book chapterson memory designs, and contributed over 130 techni-cal papers and presentations, many of them invited, toIEEE journals and conference proceedings.

Dr. Itoh has won many honors, including the IEEEPaul Rappaport Award in 1984, the Best Paper Awardof ESSCIRC90, the 1993 IEEE Solid-State CircuitsAward, and the 2006 IEEE Jun-ichi Nishizawa Medal.He is an IEEE Fellow. In Japan, his awards include theNational Invention Award Prize of the Patent Attor-ney's Association of Japan 1989, the Commendationby the Minister of State for Science and Technology(Person of Scientific and Technological Merits 1997),and the National Medal of Honor with Purple Ribbonfrom the Japanese Emperor (2000).

Introduction to “In Quest of the Joy of Creation” Kiyoo Itoh. December 17, 2007

This article covers my life of research spanning 42 years and emphasizes DRAM developments since the early1970s. I have been lucky in consistently driving cutting-edge technologies with my continuous and deep ded-ication to influential developments.

Looking back, the announcement of the first production of semiconductor memory by Intel and IBM in 1970 hada profound impact on my research. At the young age of thirty, I was entrusted with developing a 4-Kbit DRAM forHitachi Ltd. in 1972 without any knowledge about semiconductors, and had to change my research field from mag-netic thin-film memory to semiconductor memory. As the lead designer of the first prototype for each of eight suc-cessive generations of Hitachi DRAMs ranging from 4 Kbits to 64 Mbits, I was constantly faced with the challenge ofbreaking through the limits on each consecutive generation. After failing four times in the face of global competition,Hitachi finally won the race with our 64-Kbit DRAM. We eventually overcame the difficulties with our best efforts.

This article also covers my way of thinking about invention, exemplified by three representative technologiesthat I and my team invented and brought up to product applications under severe competition during differentphases of growth in our relative technological power compared to our competitors. These technologies are

• the folded data-line arrangement cell (which was invented in the era when we were catching up with oth-ers in terms of technology);

• the voltage-down converter (which was invented in the era when we were getting stronger enough tocompete as equal with others);

• the leakage-reduction circuits (which was invented in the era when we had taken the lead of the pack). This article also includes how joyous technological creation was for me. Without question, this “joy of cre-

ation” exists in our everyday struggles through trial and error in the work place. When a small idea is born ina flash under the utmost stress, and it is successively polished up and incorporated into finished products, onefeels a sense of unquestionable joy and fulfillment. Moreover, when such ideas are objectively recognizedthroughout society, our job satisfaction is maximized. To sum up, starting with a challenge, then by focusingon solutions and putting them into practice, anyone can capture this joy.

I will be delighted if this article based on my personal experience inspires engineers and managers facingchallenges in the future.




In Quest of the Joy of CreationKiyoo Itoh, Hitachi, [email protected]

Reprinted from “Innovate the Future,” 2005 Hitachi Hyoron Special Edition, pp. 34-39,Hitachi Hyoronsha, Tokyo, Japan.




Device scaling and the DRAM cellThe key component in a computer system is memo-ry, since both data and instructions in a stored-pro-gram-type computer are stored in main memory. Mag-netic core memories, used in the early stages of com-puters, were replaced by semiconductor memoriesearly in the 1970’s. The first high density semicon-ductor memory was 1-Kbit dynamic random accessmemory (DRAM), developed by Intel. Since theadvent of this 1-Kbit DRAM, the packing density andcapacity of DRAM have continued to increase totoday’s 4Gbit. Such increases were achieved by theevolution of the memory cell from a four-transistor-type, three-transistor-type to a one-transistor- type.The invention of the one-transistor-type cell (1-T cell)by Robert Dennard especially accelerated the evolu-tion of DRAM in conjunction with his device scalingtheory [1, 2].

Scaling limitation of the planar (2D) DRAM cellThe one-transistor-type cell (1-T cell) consists of onetransistor and one capacitor. A transistor acts as aswitch, and the signal charges are stored in a capac-itor. The first 1-T cell was realized using one switch-ing transistor and one MOS capacitor. The number ofsignal charges stored in the storage capacitor has tobe maintained at almost a constant, or can be onlyslightly reduced, as the memory cell size is scaleddown. However, MOS capacitor value -- and hencethe amount of signal charges – is significantlyreduced as the memory cell size is reduced, even ifthe capacitor oxide thickness is scaled-down. There-fore, I forecast in 1975 that the 1-T cell with a two-dimensional (2D) structure using a planar MOScapacitor eventually would encounter a scaling-down limitation because we cannot reduce the MOScapacitor area according to scaling theory. In addi-tion, I pointed out that the use of a MOS capacitorin the 1-T cell would be a problem because the sig-nal charges are seriously reduced due to the influ-ence of the minority carriers generated in a siliconsubstrate. An inversion layer capacitance and adepletion layer capacitance are connected with thegate oxide capacitance in parallel in the MOS capac-itor. The charges in the inversion layer and thedepletion layer are easily affected by the minoritycarriers, which are thermally or optically generated orgenerated by the irradiation of energetic particles ina silicon substrate. Therefore, I predicted that the 1-T cell using an MOS capacitor would encounter ascaling-down limitation due to the influence of theminority carriers as well.

Invention of the three-dimensional (3D) DRAM cellIn my Ph.D. research during 1971-1974 [3], I hadcommented on the silicon surface and the inversionlayer in MOS structures. To evaluate the electricalproperties of the interface states and the inversionlayer, I myself built an impedance analyzer with thefrequency range of 0.01Hz to 100MHz. I examinedvarious kinds of capacitors, including high-k (highdielectric constant) capacitors as a reference capacitorof this impedance analyzer. Eventually, I made a vac-uum capacitor for a reference capacitor in which fin-type capacitor electrodes were encapsulated in a vac-uum container. From these studies, I learned that anideal capacitor with low loss should consist of metalelectrodes and a low loss insulator (MIM structure); athree-dimensional structure of capacitor electrodes iseffective to increase the capacitance value, and thereis a trade-off between high-k and loss in the capaci-tor insulator. In addition, I knew through my Ph.D.research that the charges in the inversion layer andthe depletion layer are easily influenced by the minor-ity carriers. Therefore, I questioned why the MOScapacitor with inversion capacitance and the deple-tion capacitance was used as the storage capacitor inthe 1-T cell when I first knew about it in 1975. Then,I tried to eliminate the inversion capacitance and thedepletion capacitance by employing a passive capac-itor such as the MIM as a storage capacitor and thusproposed a three-dimensional (3D) cell in 1976 [4, 5].I called this new 3D memory cell a stacked capacitorcell (STC).

Fabrication and evaluation of the three-dimen-sional stacked capacitor cellFigure 1 shows the basic structure of a stacked capac-itor cell (STC) where the storage capacitor is three-dimensionally stacked on a switching transistor [6, 7]. A passive capacitor with the structure of an electrode-

The Stacked Capacitor DRAM Cell and Three-Dimensional MemoryMitsumasa Koyanagi, Department of Bioengineering and Robotics, Tohoku University, Japan

[email protected]

Fig. 1. Basic structure of stacked capacitor cell (STC).

© 2008 IEEE




insulator-electrode is used as a storage capacitor. Thebottom electrode of the storage capacitor is connect-ed to the source/drain region. I proposed to use self-aligned contacts to connect the bottom electrode ofthe storage capacitor and a bit line to the source/drain of the switching transistor. This self-alignedtechnique was also used for the formation of capac-itor electrodes. By three-dimensionally stacking thestorage capacitor on the switching transistor we candramatically reduce the memory cell area. In addi-tion, we can use a high-k material as a capacitorinsulator to increase the storage capacitance, since apassive capacitor is used as a storage capacitor. Thisis also useful for reducing memory cell size. Fur-thermore, we can solve the problem that the signalcharges in the inversion layer and depletion layer areinfluenced by the minority carriers since an inver-sion capacitance is not used in a stacked capacitorcell. In 1977, I fabricated the first DRAM test chipwith a stacked capacitor cell using 3μm NMOS tech-nology and presented a paper on the stacked capac-itor cell in 1978 IEDM (IEEE International ElectronDevices Meeting) [6]. Figure 2 shows the SEM crosssection of a stacked capacitor cell fabricated using3μm NMOS technology.

Fig. 2. SEM cross section of a stacked capacitor cell fabri-cated using 3um nMOS technology.

In this figure it is clearly shown that a storage capac-itor is stacked on a switching transistor and a self-aligned contact is successfully formed, although plas-ma etching and RIE (reactive ion etching) were notavailable at the time. The self-aligned contact is wide-ly used in today’s memory LSI’s. In this stackedcapacitor cell, I employed polycrystalline silicon(poly-Si)- Si3N4 - polycrystalline silicon (poly-Si) as astorage capacitor. Thermal SiO2 had been used as acapacitor insulator in a conventional 1-T cell with aMOS storage capacitor. In the stacked capacitor cell,I used Si3N4 instead of SiO2 as a capacitor insulatorto increase the storage capacitance. The dielectricconstant of Si3N4 is approximately two times largerthan that of SiO2. I found that the leakage current ofSi3N4 was significantly reduced by oxidizing its sur-face, as shown in Fig.3.

Fig. 3. Leakage-current versus applied-voltage character-istics for Si3N4 films with thin oxides on their surfaces.

I also used a Ta2O5 film as a capacitor insulator for thefirst time [7]. Ta2O5 has a dielectric constant five or sixtimes larger than that of SiO2. Therefore, we cangreatly increase the storage capacitance, although theleakage current is larger compared to those of SiO2and Si3N4, as shown in Fig.4.

Fig. 4. Leakage current – applied electric field character-istics of storage capacitors. (a) poly-Si–SiO2–poly-Si, (b)poly-Si–SiO2 /Si3N4 (ON)–poly-Si, (c) poly-Si/Ta–Ta2O5–poly-Si.



TECHNICAL LITERATUREIn 1978, when I presented the first stacked capacitorcell paper in IEDM, it was revealed that the dataretention characteristics of DRAM are seriouslydegraded due to “soft-error,” which is caused by thecarriers generated by alpha-particle irradiation in thesilicon substrate. At that time, I believed that a stackedcapacitor cell is tolerant of soft-error, since the signalcharges stored in the passive capacitor are not influ-enced by the carriers generated in the substrate. Fig-ure 5 shows the dependence of soft-error rate oncycle time in a DRAM test chip [8]. As I expected, thesoft-error rate was dramatically reduced by employinga stacked capacitor cell.

Fig. 5. Dependence of soft-error rate on cycle time in 16K-bit DRAM test chip.

Eventually I proposed three types of stacked capaci-tor cells as shown in Fig.6 [9].

Fig. 6. Cross-sectional configuration of three types ofstacked capacitor cells. (a) top-capacitor-type cell, (b) inter-mediate-capacitor-type cell, (c) bottom-capacitor-type cell.

A storage capacitor is stacked on the switching tran-sistor and the bit line in a top-capacitor-type cell, onthe switching transistor in the intermediate-capacitor-type cell (original stacked capacitor cell) and on theisolation oxide (LOCOS) in the bottom-capacitor-typecell. The top-capacitor-type STC cell is another namefor the capacitor-over-bit line (COB) stacked capacitorcell and widely used in current DRAM [10]. We canuse various kinds of materials for the capacitor insu-lator and electrodes, and can employ low temperatureprocesses in the formation of the storage capacitor inthe COB-type stacked capacitor cell since the storagecapacitor is formed on the top of the memory cell.

Evolution of the three-dimensional (3D) memorycell and future memoryIn 1979, I fabricated 16K-bit DRAM using a stackedcapacitor cell with the oxidized Si3N4 (O/N) capacitorinsulator [9]. Then I tried to introduce a stackedcapacitor cell in 64K-bit DRAM production. However,it was too early to do this due to cost. As a result, theoxidized Si3N4 (O/N) capacitor insulator wasemployed in 64K-bit DRAM production. Since then,the oxidized Si3N4 (O/N) capacitor insulator has beenwidely used for DRAM production. A stacked capaci-tor cell was employed in a 1Mbit DRAM productionfor the first time by Fujitsu [11]. Hitachi also employeda stacked capacitor cell in 4Mbit DRAM production[12]. Many other DRAM companies used a trenchcapacitor cell in the early stage of 4Mbit DRAM pro-duction. However, the stacked capacitor cell, whicheventually came to occupy a major position in 4Mbitto 4Gbit DRAM’s, has evolved by introducing thethree-dimensional capacitor structures with fin-typeelectrode [13] and cylindrical electrode [14] in con-junction with a capacitor electrode surface morpholo-gy of hemi-spherical grain (HSG) [15]. In addition tothe introduction of the three-dimensional capacitorstructure, a storage capacitor insulator with highdielectric constant (high-k) was employed in highdensity DRAM’s. In general, the leakage current ofhigh-k material increases by high temperature pro-cessing. Therefore, a COB-type stacked capacitor cellis suitable for introducing a high-k capacitor insulatorsince the storage capacitor can be formed by a lowertemperature process. Thus, the Ta2O5 capacitor insu-lator was employed in 64Mbit and 256Mbit DRAM’swith a COB-type stacked capacitor cell. Since then,various kinds of high-k materials have been studied asstorage capacitor insulators in high density DRAM’sbeyond 1Gbit. The concept of the COB-type stackedcapacitor cell -- that various kinds of materials can bestacked on the switching transistor using a lower tem-perature process -- has been carried on in new mem-ories with a three-dimensional structure such as Fe-RAM (Ferroelectric RAM), P-RAM (Phase ChangeRAM), R-RAM (Resistive RAM) and M-RAM (MagneticRAM).

In a high density stacked capacitor DRAM beyond 16Gbit, a twitching transistor with a three-dimensionalstructure such as a Fin-FET and a vertical transistor




will be employed together with a cylindrical capacitorand high-k capacitor insulator. Furthermore, manyDRAM chips eventually will be vertically stacked torealize 3D-DRAM in which the memory capacity dra-matically increases. We have already succeeded infabricating a 3D-DRAM test chip with ten memory lay-ers as shown in Fig.7 [16, 17].

This 3D-DRAM test chip was fabricated using a newlydeveloped wafer-on-wafer bonding technology withthrough-silicon-vias (TSV’s) [18-20]. Such a 3D-DRAMcan be directly stacked on a microprocessor chip torealize a 3D-microprocessor and to solve the prob-lems of memory data-bandwidth between the memo-ry and the processor. We also fabricated a 3D-micro-processor test chip in which a DRAM chip is stackedon a processor chip, as shown in Fig.8 [21].

In the future, various kinds of LSI chips, sensor chipsand MEMs chips will be vertically stacked into anultimate 3D-LSI which we call a super-chip [17, 22].We have developed a new super-chip integrationtechnology using a novel self-assembly method.

References

[1] R.H. Dennard, USP-3387286, June 4, 1968. [2] R.H. Dennard, F.H. Gaensslen, H.N. Yu, V.L. Rideout,

E. Bassous, and A.R. LeBlanc, “Design of Ion Implant-ed MOSFET’s with Very Small Physical Dimensions”,IEEE J. Solid-State Circuits, Vol. SC-9, pp. 256-268, Oct.1974.

[3] J. Nishizawa, M. Koyanagi and M. Kimura, “Imped-ance Measurements to Study Semiconductor Surfaceand Thin Insulating Films on Its Surface”, Japanese J.Applied Phys., Suppl. 2, pp.773-779, 1974.

[4] M. Koyanagi and K. Sato, Japanese patent application,Tokugansho 51-78967, 1976.

[5] M. Koyanagi and K. Sato, USP-4151607, Jan. 5, 1977. [6] M. Koyanagi, H. Sunami, N. Hashimoto and M.

Ashikawa, “Novel High Density, Staked CapacitorMOS RAM”, IEDM Tech. Dig., pp. 348-351, Dec. 1978.

[7] M. Koyanagi, H. Sunami, N. Hashimoto and M.Ashikawa, “Novel High Density, Staked CapacitorMOS RAM”, Extended Abstracts of the 10th Confer-

Fig. 7. SEM cross section of 3D-DRAM test chip with ten memory layers fabricated by wafer-on-wafer bonding technol-ogy with through-silicon-vias (TSV’s).

Fig. 8 SEM cross section of a 3D-microprocessor test chip fabricated by wafer-on-wafer bonding technology withthrough-silicon-vias (TSV’s).



TECHNICAL LITERATUREence on Solid State Devices, 1978.

[8] M. Koyanagi, Y. Sakai, M. Ishihara, M. Tazunoki andN. Hashimoto, “16-kbit Stacked Capacitor MOS RAM”,IEICE Technical Report (Japanese), SSD80-30, 1980.

[9] M. Koyanagi, Y. Sakai, M. Ishihara, M. Tazunoki andN. Hashimoto, “A 5-V Only 16-kbit Stacked CapacitorMOS RAM”, IEEE Trans. on Electron Devices, ED-8,pp.1596-1601, 1980/ IEEE J. Solid-State Circuits, SC-15,pp.661-666, 1980.

[10] S. Kimura, Y. Kawamoto, T. Kure, N. Hasegawa, J.Etoh, M. Aoki, E. Takeda, H. Sunami and K. Itoh, “ANew Stacked Capacitor DRAM Cell Characterized by aStorage Capacitor on a Bit-line Structure”, IEDM Tech.Dig., pp. 596-599, Dec. 1988.

[11] Y. Takemae, T. Ema, M. Nakano, F. Baba, T. Yabu, K.Miyasaka, K. Shirai, “A 1Mb DRAM with 3-Dimension-al Stacked Capacitor Cells”, ISSCC Dig. Tech. Papers,pp. 250-251, Feb. 1985.

[12] K. Kimura, K. Shimohigashi, J. Etoh, M. Ishihara, K.Miyazawa, S. Shimizu, Y. Sakai, and K. Yagi, “A 65-ns4-Mbit CMOS DRAM with a Twisted Driveline SenseAmplifier”, IEEE J. Solid-State Circuits, SC-22, pp.651-656, 1987.

[13] T. Ema, S. Kawanago, T. Nishi, S. Yoshida, H. Nishide,T. Yabu, Y. Kodama, T. Nakano, M. Taguchi, “3-Dimensional Stacked Capacitor Cell for 16M and 64MDRAMs”, IEDM Tech. Dig., pp. 592-595, Dec. 1988.

[14] W. Wakamiya, Y. Tanaka, H. Kimura, H. Miyatake andS. Satoh, “Novel Stacked Capacitor Cell for 64MbDRAM”, Symposium on VLSI Technology Dig. Tech.Papers, pp. 69-70, 1989.

[15] H. Watanabe, T. Tatsumi, S. Ohnishi, T. Hamada, I.Honma, T. Kikkawa, “A New Cylindrical CapacitorUsing Hemispherical Grained Si (HSG-Si) for 256MbDRAMs,” IEDM Tech. Dig., pp. 259 - 262, Dec. 1992.

[16] K.W. Lee, T. Nakamura, T. Ono, Y. Yamada, T.Mizukusa, H. Hashimoto, K.T. Park, H. Kurino and M.Koyanagi, “Three-Dimensional Shared Memory Fabri-cated Using Wafer Stacking Technology”, IEDM Tech.Dig., pp. 165-168, Dec. 2000.

[17] T. Fukushima, Y. Yamada, H. Kikuchi, and M. Koy-anagi, “New Three-Dimensional Integration Technolo-gy Using Self-Assembly Technique”, IEDM Tech. Dig.,pp. 359-362, Dec. 2005.

[18] M. Koyanagi, “Roadblocks in Achieving Three-Dimen-sional LSI”, 8th Symposium on Future ElectronDevices Tech. Dig., pp.55-60, 1989.

[19] H. Takata, T. Nakano, S. Yokoyama, S. Horiuchi, H.Itani, H. Tsukamoto and M. Koyanagi, “A novel fabri-cation technology for optically interconnected three-dimensional LSI by wafer aligning and bonding tech-nique,” Proc. Int. Semiconductor Device ResearchSymposium, pp.327-330, 1991.

[20] M. Koyanagi, T. Nakamura, Y. Yamada, H. Kikuchi, T.Fukushima, T. Tanaka, and H. Kurino, “Three-Dimen-sional Integration Technology Based on Wafer Bond-ing With Vertical Buried Interconnections”, IEEE Trans.

on Electron Devices, vol.53, pp. 2799-2808, 2006. [21] T. Ono, T. Mizukusa, T. Nakamura, Y. Yamada, Y.

Igarashi, T. Morooka, H. Kurino and M. Koyanagi,“Three-Dimensional Processor System Fabricated byWafer Stacking Technology”, IEEE COOL Chips VTech. Dig., pp.186-193, 2002.

[22] T. Fukushima, Y. Yamada, H. Kikuchi, T. Konno, J.Liang, K. Sasaki, K. Inamura, T. Tanaka, and M. Koy-anagi, “New Three-Dimensional Integration Technolo-gy Based on Reconfigured Wafer-on-Wafer BondingTechnique”, IEDM Tech. Dig., pp. 985-988, Dec. 2007.

About the AuthorMitsumasa Koyanagi was born in1947 in Hokkaido, Japan. He receivedthe B.S. degree from Department ofElectrical Engineering, Muroran Insti-tute of Technology, Japan in 1969 andthe M.S. and Ph.D. degrees fromDepartment of Electronic Engineering,

Tohoku University in 1971 and 1974, respectively.

He joined the Central Research Laboratory, HitachiCo. Ltd. in 1974 where he had engaged in theresearch and development of DRAM and ASICprocess and device technologies and invented aStacked Capacitor DRAM memory cell which hasbeen widely used in DRAM production. In 1985, hejoined Xerox Palo Alto Research Center, where hewas responsible for research on submicron CMOSdevices, poly-Si TFT devices and analog/digital sensorLSI design. In 1988, he became a professor in theResearch Center for Integrated Systems, HiroshimaUniversity, Japan where he engaged in the research ofsub-0.1um device fabrication and characterization,device modeling, poly-Si TFT devices, 3-D integrationtechnology, optical interconnection and parallel com-puter system. He proposed a 3-D integration technol-ogy based on wafer-to-wafer bonding and through-Sivias (TSVs) in 1989. Since 1994, he has been a pro-fessor in the Intelligent System Design Lab., Depart-ment of Machine Intelligence and Systems Engineer-ing, and is currently a member of the Department ofBioengineering and Robotics, Graduate School ofEngineering, Tohoku University, Japan. His currentinterests are 3-D integration technology, optical inter-connection, nano-CMOS devices, memory devices,parallel computer system specific for scientific com-putation, real-time image processing system, artificialretina chip and retinal prosthesis chip, brain-machineinterface (BMI) and neural prosthesis chip, brain-likecomputer system.

Dr. Koyanagi was awarded the IEEE Jun-Ichi Nishiza-wa Medal (2006), the IEEE Cledo Brunetti Award(1996) and Japan’s Ministry of Education, Culture,Sports, Science and Technology Award (2002), inaddition to the Ohkouchi Prize (1992), SSDM (Solid-State Devices and Materials Conf.) Award (1994) andthe Opto-Electronic Integration Technology (IzuoHayashi) Award in 2004. He is an IEEE fellow.




Advent of DRAM The advent of dynamic-random-access memory(DRAM) is recognized to have been in 1970, whenIntel introduced a 1-Kbit chip using three-transistorDRAM cells. A few years later, 4-Kbit DRAM using theone-transistor cell1) was being widely manufactured,its low cost contributing to the development of thepersonal computer. This was just the time whenmetal-oxide-semiconductor (MOS) devices wereproven to deserve application as highly reliable mainmemory in mainframes.

Since then, DRAM capacity has been increasing by afactor of four every three years until today. As moderncomputers are based on von Neumann’s architecture,main memory is a key device together with processor.Along with the prosperity of computing, the demandfor memory has increased to produce a world-wide 30-B$ market for DRAM. Even if the main customer is stillpersonal computers, various applications such as cellphones, game machines, personal audio, and videomachines are extending DRAM’s usage.

Key factor of costThe strongest driving force for growing the DRAM marketis undoubtedly “cost.” Therefore, various developmentefforts have focused on the reduction of manufacturingcost. The bit cost has decreased by a factor of 106 since1970, and the 1-Gbit product will soon be sold at the sameprice as 1-Kbit. Since die cost is closely related to numberof dies on a wafer, wafer size has continually increased tobe such as 2”, 3”, 4”, 5”, 6”, 8”, and now 12” in diameter.Together with the diameter increase, memory cell size hasbeen reduced to be one-third for each DRAM generationin volume production to absorb die size increase. Conse-quently, the die size has been enlarged at most up to 10

times despite a bit increase by 106 from 1-Kbit to 1-Gbit,while the memory cell size decreasesd by 105 times asshown in Fig. 1.

One of the key processes to achieve cell sizereduction is patterning technology, including pho-tolithography and dry etching. Pattern size hasbeen reduced to 1/100 from 10 μm to 100 nmsince 1970. For a long time until the late 1990’s,DRAM was a unique vehicle to develop finer pat-terning technologies. As far as isolated patternssuch as transistor gate length are concerned, high-end microprocessors incorporate smaller dimen-sions than DRAM. But half-pitch of dense wiringstill denotes difficulty of overall patterning tech-nologies. Transistor density of DRAM is more than10 times larger than that of microprocessor.

Invention of the trench cell In response to die size reduction to cope with a 4-fold increase in memory capacity, memory cell sizehas been reduced by almost one-third for eachgeneration, previously shown in Fig. 1. The so-called 1-transistor DRAM cell1) consists of one celltransistor and one storage capacitor. Key specifica-tions in DRAM operation, such as noise margin,soft-error durability, operational speed, and powerconsumption, strongly depend on the storagecapacitor2). The capacitance value, CS is expressedas CS=ε iA/Ti, where ε i, A, Ti, are permittivity ofstorage insulator, area of capacitor electrode, andinsulator thickness, respectively. Therefore, cellsize reduction through scaling alone leads to areareduction and a subsequent decrease in capaci-tance value.

To cope with the dilemma of size vs. capaci-tance, insulator thickness was reduced by a factorof 10 from 100 nm in 1-Kbit chips to 10 nm in 1-Mbit chips, getting dangerously close to dielectricfield breakdown. When the author took a glimpseat some conference presentations in 1974 fromTexas Instruments introducing a highly efficientsilicon solar cell with a steep trench and forecast-ing the upcoming issue of cell size vs. capaci-tance, he got an idea of a trench capacitor DRAMcell. Even though his job at that time was to char-acterize the silicon surface with photoemissionspectroscopy, his amateur-radio hobby connectedthe shape of a trimmer condenser, which has twocoaxial cylindrical opposite electrodes as seen inFig. 2, with the needs of a 1-transistor cell. Fromthat idea, he invented the trench capacitor cell andapplied for a Japanese patent3) in 1975. Due to itslow score of assessment, this was not applied toany overseas patent.

The Role of the Trench Capacitor in DRAMInnovationHideo Sunami, Research Center for Nanodevices and Systems, Hiroshima University,[email protected]

Fig. 1 Memory cell size shrinkage at DRAM in volume pro-duction.

© 2008 IEEE




Fig. 2 An amateur-radio transmitter circuit designed by theauthor in 1960 and a photograph of a trimmer condenser.

After Hitachi had won a leader’s position in 64-Kbitproducts with a 5-V single power supply and foldedbit-line arrangement4), it’s research and developmentgroup could afford to challenge for novel cell devel-opment. After several years’ development, the first 1-Mbit level trench cell in trial production was imple-mented and presented in 1982 IEDM5). Its journalpaper won the 1984 Paul Rappaport Award6). An SEMcell cross-section is shown in Fig. 3.

Fig. 3 First 1-Mbit DRAM with trench capacitor cell.

Fig. 4 Soft error rates of planar and trench cells.

Changes of trench cell employment In the first trench cell in trial production, a seriousproblem of soft-error was found caused by alpha-par-ticle hit as shown in Fig. 4.

Fig. 5 Major advancement in DRAM cell innovation.

One alpha particle at maximum 5-MeV energy gen-erates almost one million electron-hole pairs. Onemillion electrons is about 190 fC, which is almostequivalent to signal charges stored in one storagecapacitor of a 1-Mbit DRAM cell. Due to extendeddepletion layer of the storage capacitor in the trenchcell, it “effectively” collects generated electrons. Inaddition to the soft-error problem, it was predictedthat punch-through current between any two adja-cent capacitors would soon limit further shrinkage ofthe cell. Whether the trench cell should be improvedor abandoned was a serious decision point.

In those days, most DRAM manufacturers madeefforts to supply their DRAM products to very limitedleading mainframe makers. That was a kind of cer-tificate that their products achieved first-rate reliabili-ty. The certificate surely made their business fruitful.Even with a half-year delay in product development,they might lose their business in the mainframe mar-ket. There is some evidence that the leading makerhas changed with each DRAM generation, from 1-K,Intel, TI, MOSTEK, Hitachi, NEC, Toshiba, NEC, andSamsung.

Being both a DRAM manufacturer and main framemaker, Hitachi focused keenly on the mainframeapplication with highest-grade reliability. Thus,Hitachi had abandoned the trench cell, despite devicedevelopment group proposals for several improvedstructures to reduce the soft-error problem. Addition-al development was thought to need more than half ayear. An invention of half-Vcc plate configurationwhich had a potential of storage-capacitance doublingcould prolong the conventional planar cell. This mightalso have influenced Hitachi’s decision.

However, several major manufacturers employedthe trench and have been improving the structureuntil today. Major advancement in cell innovation isshown in Fig. 5.

Together with the trench, the stacked capacitor cellwas also applied in products. The substrate-platetrench cell amazingly improves soft-error tolerancedue to its highly shrunk depletion layer. In addition tothese cell structure innovations, the hemi-sphericalgrain (HSG) structure7) was an inevitable technique todouble the storage capacitance due to increased sur-face area. Cylinder-type stack and substrate-platetrench, both with HSG, are the major cells being pro-duced today.




Material revolutionFrom 1 K to 1 M, shrinking dimensions was the keyissue. The storage capacitance value was kept almostthe same over several DRAM generations by reducinginsulator thickness. Consequently, the reduced thick-ness made the electric field across the insulator closeto 5 MV/cm, a value which was recognized to be anupper limit for keeping insulator integrity and refreshtime in DRAM operation. Thus, innovative techniqueother than thickness reduction was strongly required.

In response, three-dimensional structures wereproposed. From 1 M to 1 G, three-dimensional struc-ture innovation has been achieved as previouslyshown in Fig. 4. However, as the aspect ratio of thestorage capacitor exceeds more than 10, manufac-turability will be a much more serious issue. The finalparameter to be handled in the relation of CS=ε iA/Tiis permittivity, ε i. Thus, various kinds of high-k mate-rials have been developed as shown in Fig. 6. Butthere is a serious fact that the thinner the thickness is,the less its permittivity is. There may not be a uniqueultimate solution at this moment. Material revolutionwith ultra high-k material is solicited to extend DRAMfurther toward terabit DRAM.

To summarize innovation achieved in the past andrequirements for the future, there are three eras forDRAM development:

• 1-K to 1-M ---- dimension improvement(smaller cell, reduced insulator thickness)

• 1-M to 1-G ---- structure innovation (stackand/or trench cells)

• 1-G to 1-T ---- material revolution (ultra high-k films)

The final parameter which affects advanced shrink-age of the cell should be the insulator thickness itself.If the insulator is thick enough to fill the internal holeof the trench of the trench cell or the cylinder of thestacked cell, the plate of the capacitor cannot pene-trate inside the trench or the cylinder, resulting in nocapacitor formation8). In this sense, high-k filmsshould be thin enough, simultaneously keeping their

high-k value. This may be the deadlock for realizingsmaller cells of the 1-T type DRAM cell. Even utiliz-ing cutting-edge high-k films at present, 32 or 64-GbitDRAM will be the biggest capacity without die stack.We would like to expect novel main memory candi-dates in the near future.

References1) R. H. Dennard, U. S. Patent 3,387,286, 1968.

2) R. H. Dennard, “Evolution of the MOSFET Dynamic RAM-A

Personal View,” IEEE Trans. Electron Devices, ED-31, pp.

1549-1555, 1984.

3) H. Sunami and S. Nishimatsu, Japanese patent application,

Tokugansho 50-53883, 1975.

4) K. Itoh, R. Hori, H. Masuda, Y. Kamigaki, H. Kawamoto, and

H. Katto, “A single 5V 64K dynamic RAM,” ISSCC Dig. Tech.

Papers, pp. 228-229, Feb. 1980.

5) H. Sunami, T. Kure, N. Hashimoto, K. Itoh, T. Toyabe, and S.

Asai, IEDM Tech. Dig., pp. 806-808, December, 1982.

6) H. Sunami, T. Kure, N. Hashimoto, K. Itoh, T. Toyabe, and S.

Asai, “A Corrugated Capacitor Cell (CCC),” IEEE Trans. Elec-

tron Devices, ED-31, No. 6, pp. 746-753, 1984.

7) H. Watanabe, T. Tatsumi, S. Ohnishi, T. Hamada, I. Honma,

and T. Kikkawa, “A new cylindrical capacitor using hemi-

spherical grained Si (HSG-Si) for 256Mb DRAMs,” IEDM

Tech. Dig., pp. 259 - 262, December 1992.

8) K. Itoh, H. Sunami, K. Nakazato, and M. Horiguchi, “Path-

ways to DRAM Design and Technology for the 21st Century,”

Proc. the 8th Internat. Symp. Silicon Materials Science and

Technology, Volume 98-1, pp. 350-369, 1998.

About the AuthorHideo Sunami (Fellow, IEEE) receivedthe B.S., the M. S., and the Ph. D. Degreesin Electrical Engineering all from TohokuUniversity, Japan, in 1967, 1969, and1980, respectively. He is currently a Pro-fessor with Special Appointment in Inter-disciplinary Research on Integration of

Semiconductor and Biotechnology, Hiroshima Universityand a Technical Advisor to Consortium for AdvancedSemiconductor Materials and Related Technologies.

From 1998 to 2007, he was a Professor at ResearchCenter for Nanodevices and Systems in Hiroshima Uni-versity working on three-dimensional MOS devices andsilicon optical modulator. From 1969 to 1998, he hasbeen doing R&D on multi-level metallization, CCD,DRAM, three-dimensional devices, and process CAD,mainly in Central Research Laboratory, Hitachi Ltd.

He has published 113 papers both in technical jour-nals and international conferences and authored andcoauthored 16 books. He has held 115 Japanese andUS patents. He was awarded the 1985 Paul RappaportAward, the 1991 Cledo Brunetti Award, the 1998Tokyo Governor’s Distinguished Inventor Award, andthe 2006 Jun-ichi Nishizawa Medal. He is a Fellow ofJapan Society of Applied Physics and a Fellow of theInstitute of Electronics, Information and Communica-tion Engineers of Japan.

Fig.6 Relation between bandgap energy and permittivi-ty of high-k insulating films.




INTRODUCTIONComputing systems depend on the ability to movevast amounts of data to and from the processor itself.Early in the development of computers, it was recog-nized that a hierarchy of memory was essential toenable timely access to data.

Most computing systems have three basic cate-gories of memory: On-chip memory is the fastest andmost expensive, dedicated to the immediate needs ofthe processor. Main memory stores the software anddata for quick access when needed. It is often hun-dreds of times larger in capacity than on-chip memo-ry and about a tenth to a hundredth the speed. “Stor-age” is the term used for non-volatile memory, includ-ing hard-disc drives, solid-state flash devices, and/ormagnetic tape for vast amounts of data when fastaccess times are less important.

Dynamic Random Access Memory (DRAM) tech-nology has had a virtual monopoly on the main mem-ory segment. Its relatively low cost and high accessspeed are well-suited for computing system needs.The origin of DRAM technology and the invention ofthe one-transistor DRAM cell are addressed in otherarticles in this issue. This article looks at the overallDRAM industry since its beginnings in 1970 andexamines some of the key factors that determined itssuccess.

Figure 1 shows a graph of the number of DRAMbits shipped per year since the first DRAM chips weresold by Intel in mid-1970. In every year, the numberof bits shipped has been greater than the previousyear; there has been no downturn in volume: Theannual growth rate in shipped volume of bits was anincredible 150% in the first 15 years of the industry,an impressive 70% in the next 15 years and a stillrespectable 50% since then.

DRAM products are typically identified by thenumber of bits per chip, sometimes called its “gran-ularity.” The first products had 1,024 bits of storageand were dubbed 1K DRAM’s. Subsequent productsincreased the amount of storage by a factor of 4.

Figure 2 shows the volume of units shipped for allgranularities of DRAMs since 1970. The 4X increasein bits per chip per product generation was sus-tained in the industry until the introduction of the128Mb product, after which a 2X increment becamethe rule.

MOORE’S UBIQUITOUS LAWIn 1975, Gordon Moore reported that his prediction1

in 1965 of an annual doubling of transistors per diewas remarkably accurate.2 He also claimed the dou-bling rate would slow down to something less thantwo years. The relatively new DRAM industry, led byMoore’s own company, latched onto his scenario andfollowed it more closely than any other product line.DRAM products were subsequently developed at apace of a 4X increase in bits per chip every threeyears, a trend dubbed “Moore’s Law.” Figure 3 showsthe total number of bits shipped divided by the totalnumber of chips shipped, yielding an effective aver-age bit per chip. In recent years the trend has clearlyslowed down.

Another analysis considers the first year of manu-facturing for a given granularity. Figure 4 shows thatwhile DRAM introduction maintained the 4X/3yr paceuntil the latter part of the 90’s, the rate has slowed

The Remarkable Story of The DRAM IndustryRandy Isaac, Executive Director, American Scientific Affiliation, [email protected]

Figure 1: Volume of DRAM bits shipped per year.

Figure 2: Volume of DRAM bits shipped per year by chipgranularity.

Figure 3: Average DRAM bits per chip shipped per year.

© 2008 IEEE




considerably since then to approximately 2X/3yr. Pro-jecting from the trend of the 80’s and 90’s, a 16GbDRAM chip would have been expected to be manu-factured in 2007. Instead, it is a 2Gb chip that is mak-ing its debut.

The importance of Moore’s Law is not so muchthe doubling rate, which has varied from thebeginning. Rather, Moore’s keen insight was theroot cause of an increase in transistors on a die andits economic effects. In his 1975 article, Mooreidentified three major factors that enabled such arapid increase in transistors per chip: Improve-ments in manufacturability leading to larger diesizes; innovation in cell layout for more efficiency;and higher resolution lithography for increaseddensity. He attempted to quantify the relative con-tributions of each factor. The DRAM industry settledinto a slightly different balance of contributionswith 50% due to lithography, 25% due to anincrease in die size manufacturability, and 25% dueto innovative reductions in cell size per bit. Thisfundamental recipe guided the industry for severaldecades. To discover the reasons for the recent shiftin the trend line, we need to look at these underly-ing factors in more detail.

The near-mythic popularity of Moore’s Law was aboon to the development of the DRAM industry. Theunderlying principles were fundamentally sound andresonated with the technology community. The trendlines were clear targets for all suppliers, customers,and developers. Infrastructure needs could be identi-fied well in advance so that equipment supplierswere able to develop the necessary equipment intime. Innovative ideas were stimulated by the chal-lenge of sustaining the rapid pace of exponentialimprovement.

Lithography was the dominant factor in improvingbits per chip. The recipe cited above is equivalent toa 30% improvement in linear resolution for each 3-year cycle. That pattern was sustained as technologymigrated from broadband mercury illumination to g-line, h-line, i-line, and then DUV excimer laser tech-nologies at 248nm and now 193nm capabilities.Remarkably, the pace seems to have accelerated sincethe late 90’s with the introduction of DUV, when thepace increased to 30% every 2 years, as shown in Fig.

5. It is possible that this rate of progress will continueto the 22nm generation using 193nm lithography. Noeconomically feasible technology has yet been identi-fied beyond that level.

The more rapid increase in lithography progresswould normally have been expected to increase thepace of progress of DRAM granularity. However, theimprovement in bits per chip of DRAM products actu-ally slowed down at the same time that lithographyspeeded up. To understand this contrasting trend, weneed to understand the other two driving forces inDRAM density.

DRAM cell innovation was a creative aspect ofproduct development. Dennard’s invention of theone-transistor cell3 stimulated a critical improvementin areal bit density. Subsequently, each productreflected a more efficient layout of the key elementsdefining the transistor, the capacitor, and the neces-sary contacts.

A major split in the DRAM industry occurred withthe 4Mb products. To achieve the improvement man-dated by the recipe, the cell needed to become 3-dimensional. The two obvious choices were placingthe capacitor above the transistor vs. placing thecapacitor below the transistor. The industry split intoa stacked capacitor path vs. a trench capacitorapproach. A key innovation at IBM was the substrateplate trench capacitor in which the charge was storedinside the trench capacitor with the substrate ground-ed, as opposed to other approaches where the chargewas stored outside the trench. The latter approachwas not able to scale to smaller dimensions as thetrenches came closer together and the charge fromneighboring cells began to merge. This innovative cellbecame the only successful trench approach and waswidely deployed via IBM’s alliance with Siemens andToshiba. The rest of the industry placed the capacitoron top of the transistor. To this day, both approachespersist in the industry with neither ceding ground tothe other in extensibility.

However, in the last half of the 1990’s, bothapproaches reached a limit in area of approximately6-8F2 where F is the smallest lithographic feature size.A simple cross-point cell has a minimum area of 4F2.An area of 6F2 is felt to be the approximate limit ofmemory cells without going to multiple bit-per-cell

Figure 4: Trend of introduction of DRAM chips into manu-facturing.

Figure 5: Trend of lithography resolution for chip manu-facturing.



TECHNICAL LITERATUREtechnologies which trade off access speed. As a result,cell size innovation became a much smaller factor inthe improvement of bit density at about the same timethat lithography moved faster.

Die size is perhaps the most difficult parameter totrack. Silicon area is the single most important factorin manufacturing cost. As soon as a product is intro-duced, competitive survival requires a rapid reduc-tion in die size. A rough indicator is to consider thedie size of the first volume shipments of a particularproduct line. This die size increased according to therecipe until approximately the 64Mb generation. Bythat time, the DRAM market was dominated by thePC industry. Memory was being sold primarilythrough memory modules rather than as individualpackaged die. The most rapidly growing portion ofthat market was laptops, which constrained the phys-ical size of these modules. As module size becamestandardized, larger modules were not accepted inthe marketplace. This limitation meant that newDRAM product introductions needed to meet themodule size constraints. Hence, an increase in diesize was no longer a viable option for increasingDRAM granularity at about the same time that lithog-raphy moved faster.

Cost reduction played a major role in reducing diesize. DRAM prices have historically dropped approxi-mately 27% a year, though with significant fluctuationsdue to supply and demand variation. Accordingly, themanufacturers must drop costs by at least 27% a year.The most important parameter for cost is die sizewhich determines the number of die per wafer. Com-petitive pressures led to a rapid reduction of die sizeto approximately the same size, independent of gran-ularity. Consequently, die size could no longer con-tribute significantly to an increase in bits per chip.

Of the three technical factors identified by Moore,only lithography remained a major factor in improvingthe number of DRAM bits per chip by the end of the20th century. The faster rate of introduction of litho-graphic resolution in the late 90’s was more than offsetby the lack of increase in die size and the stable nor-malized cell sizes. The migration of the DRAM industryfrom a 4X/3 year pace to a 2X/3 year pace can beunderstood from these technology considerations.

THE ECONOMICS OF DRAM’sMarket demand must also be noted as an importantfactor in the changing pace of DRAM products. In thelate 80’s and most of the 90’s, the PC was the domi-nant market for DRAM’s. Approximately 75% ofDRAM’s were sold to PC clients or servers. For mostof that period, memory upgrades were a critical wayto improve PC performance and to enable the use ofnew applications. By the end of the 90’s, however, thesizes of operating systems and of applications wereno longer growing as rapidly. The amount of mainmemory per PC was not required to increase as quick-ly as it did in earlier years. Consequently, the domi-nant market for DRAM’s did not demand as fast anincrease in bits per chip.

The high-performance computing industry had nosuch letdown in demand. Its insatiable appetite forperformance demanded more memory with very highbandwidth. However, as a DRAM customer, its vol-umes were a small fraction of those represented byPC’s – not a large enough market to drive the devel-opment of more bits per chip. Since attention must bedirected to more efficient packaging to reduce thephysical size of a large main memory, innovativeways of stacking DRAM die with through vias arebeing pursued to reduce overall costs.

So far, our discussion has focused on the physicalsize of DRAM chips. A few words about performance,namely write time, access time and power are inorder. The physical reduction of memory cell sizedoes not automatically lead to better performance.Only a well-designed balance of improved transistorcharacteristics and matching capacitor capabilities canenable proper scaling with performance benefits. TheDRAM industry as a whole has always valued costmore than performance. As a system house, IBM wasa DRAM manufacturer with a captive market for manyyears. It had the luxury of optimizing its main memo-ry design to enhance system performance. As a result,IBM’s first 1Mb offering continued to use metal gatetechnology and an NMOS technology. Reliability andpower considerations drove the migration to CMOSwith polysilicon gates. Only in its 16Mb and 64MbDRAM products, developed in an alliance withSiemens, now Qimonda, and Toshiba did IBM moveto industry-standard products for cost reasons. Pro-posals for high-speed DRAM’s dotted the DRAM liter-ature, but the market simply did not bear any addi-tional cost per bit.

Power consumption has always been of some con-cern due to the large number of DRAM chips normal-ly used in a system, especially in high-performancesystems. As channel lengths have decreased andstandby power increased, these concerns havegrown. Future development will need to concentratemore on ways to reduce leakage and power requiredto write and access bits. The ability to fully leverageimprovements in lithography will depend on innova-tive ways to scale the transistor and capacitor whiledecreasing leakage such as pass gate devices with 3Dstructures.

The business and economic aspects of the DRAMindustry are every bit as influential as the technologyelements. As the DRAM product grew in demand,many companies jumped at the opportunity to partic-ipate. In the late 80’s there were as many as 30 com-panies worldwide that were producing DRAM memo-ry chips. But the torrid pace of increasing bits/chipwith its demands of competitive technology took itstoll. The cost of technology development was esti-mated at half a billion dollars by the early part of the90’s, with a comparable or larger capital investmentfor a manufacturing facility. Today the developmentcosts exceed a billion dollars and a fab investment isin the ballpark of 2 to 3 billion dollars. Such a vastinvestment of money and time with high risk chasedmost players out of the business. In the 90’s, the




CROSS-CULTURAL DRAM DEVELOPMENTOne of the most rewarding experiences of my careerwas the privilege of leading the joint 64Mb DRAMdevelopment project with IBM, Siemens, and Toshibafrom 1990 to 1995. Skyrocketing development costsforced DRAM manufacturers to join forces, sharingprocess lines and skilled engineers as well as costs.

Global alliances were already common, but forg-ing a close-knit team for an aggressive chip develop-ment project was a much greater challenge. Culturaldifferences were most obvious and had to beaddressed explicitly. Language issues were immedi-ately resolved with education and careful explanationof all unfamiliar terms. Only later did we observe theinsidious danger of multiple meanings or alternativeconnotations of words that slipped by with noawareness of the lack of understanding.

The problem of corporate cultural differences wasless anticipated. We learned by experience that eachcompany’s employees brought a different expecta-tion of the way in which decisions were made andreported. Democratic, autocratic, and oligarchicapproaches to authority had to be blended andrespected. Communication styles varied widely.Americans preferred bullets in a slide show; Germans

preferred technical memos with infinite detail, whileJapanese excelled in personal behind-the-scenes con-versations. Corporate priorities also differed. Ameri-cans emphasized good news and progress; Germanswanted a focus on issues and remaining problems,and the Japanese valued public consensus.

Each company derived significant benefit from thejoint development program that transcended costreduction. Sharing the skills and experience of engi-neers from three different DRAM manufacturers ledto an effective collective wisdom. IBM’s penchant forin-house tools and solutions came to be reconciledwith Siemens’ and Toshiba’s preference for industry-standard methods. Vigorous debates on strategicdirections for DRAM’s were sharpened by our globalperspective.

On a personal level, all engineers from the threecompanies expressed appreciation for the valuederived from their experience. Befriending and work-ing with colleagues from other cultures shaped ourlives in a most positive way. I found the experienceto be stimulating on many levels. Beyond the busi-ness and technical value, the friendships forged dur-ing our common focus on product developmentremain to this day.

industry moved to alliances. IBM worked withSiemens and then with Toshiba to share developmentexpertise and costs. That highly successful modelmigrated to a broad logic technology developmentthat still leads the industry. At the beginning of the21st century there were only eight significant playersremaining in the DRAM business.

Any business built around a core concept of rapidreduction in unit cost must realize a market growingfaster than the price reduction if the industry revenueis expected to increase. As seen in Fig. 1, the DRAMbit volume market increased very rapidly for the firstthree decades. Today that pace is much slower. If therate of increase in volume of bits slows to below theaverage rate of bit price reduction (historically 27%per year), overall industry revenue will drop. Theindustry would then have a most difficult time fund-ing the critical research and development necessary tomake technical improvements.

The cost per bit of DRAM production is primarilyset by areal bit density, assuming that high yield canbe achieved and that the economic scale is largeenough to amortize the investment costs. The marketprice, however, is dominated by supply and demand.In a field of such high investment with a long time ofimplementation and return on investment, the stage isset for great volatility. The DRAM industry has there-fore been marked by major swings. This unpre-dictability was a key reason for major companies suchas Intel and IBM to move away from the DRAM busi-ness, leaving it to companies able to risk majorresources.

The relationship between DRAM technology andlogic technology has also gone through a major shift.In the 70’s, most logic was built in bipolar technolo-gy. As NMOS, and then CMOS, grew popular as a

cost-performance technology, DRAM became a tech-nology driver. It had the volume scale and therequirements to enable an effective investment fortechnology development. The resulting transistor wasthen used as a low cost logic element. As the oppor-tunity grew for higher performance CMOS logic, therequirements for logic and DRAM transistors began todiverge. Low leakage, high threshold voltage deviceswere needed for DRAM applications while lowerthreshold voltage transistors were necessary for logicperformance. Gradually, the technologies weredecoupled, though DRAM’s were still viewed as adriver for process equipment, particularly lithography,and defect reduction.

THE FUTURE OF DRAM’SToday the lithography technology driver role haslargely migrated to non-volatile flash memory. Theflash memory industry is remarkably similar to theDRAM industry, with about a 16 year lag. It is cur-rently growing much faster than DRAM’s and the mar-ket is demanding a more rapid increase in bits perchip for flash compared to DRAM’s. With less demandfor performance, flash can tolerate multiple bits percell, helping to reduce effective cell size. Flash chipswith 64Gb of memory are now in development.

At each generation of DRAM development,immense technical difficulties have led to doubtsabout future scaling. So far, all hurdles have been metbut no exponential continues forever. Dielectric filmson the order of a few atomic layers thick seem to beas thin as could ever be achieved. Transistors are sodifficult to turn off that further scaling seems likely tolead to unacceptable leakage. Yet, innovation contin-ues to thrive. Young engineers who don’t know the




About the Author Randall D. Isaac became ExecutiveDirector of The American ScientificAffiliation after his retirement from IBMin 2005. He was previously Vice Presi-dent of Strategic Alliances for the IBMSystems & Technology Group. From1996 to 2003 he served as the Vice Pres-

ident, Science and Technology, for the IBM ResearchDivision where he had worldwide responsibility forsemiconductor, packaging, and communicationstechnologies.

In 1995 he was the founder and Director of the IBMAustin Research Laboratory in Austin, Texas whichfocuses on high-performance microprocessor design.From 1990 to 1995, Dr. Isaac was a senior manager in

the Semiconductor Research and Development Center ofthe IBM Microelectronics Division in Burlington, Ver-mont. In this capacity, he was the project manager forthe 64Mb DRAM development joint program withSiemens and Toshiba. From 1987 to 1990, he was Direc-tor of Silicon Technology in IBM Research in Yorktown.

Dr. Isaac received his B.S. degree in physics fromWheaton College in Wheaton, Illinois in 1972 and hisM.S. and Ph.D. degrees in physics from the Universi-ty of Illinois at Urbana-Champaign in 1974 and 1977,respectively. Dr. Isaac joined IBM in 1977 at the IBMThomas J. Watson Research Center at Yorktown as aResearch Staff Member in silicon technology.

Dr. Isaac is a Senior Member of IEEE , a Fellow ofthe American Physical Society, and a Fellow of theAmerican Scientific Affiliation.

meaning of “impossible” seem to find new ways ofsolving what appear to be intractable problems.

Competing technologies must provide superiorperformance and lower cost to be seriously consid-ered as a DRAM replacement. Magnetic tunnel junc-tions have been touted for their speed, but have notyet met cell size requirements. Phase-change memoryis a research candidate that might meet both speedand size requirements, but no technology has yetmatched CMOS DRAM’s in reliability. The DRAMindustry has nearly 40 years of experience in learninghow to meet rigorous reliability criteria. New tech-nologies are likely to be tested first in applicationswith less stringent requirements. The computer indus-try cannot afford to jump into a new technology untilall aspects have been clearly demonstrated in volume.

DRAM memory cells are now being deployed asembedded memory in logic technology, offering alower cost, lower power alternative to SRAM mem-ory cells. The greater soft-error immunity of DRAM’sgive them an edge as well as superior density. On-chip performance has been demonstrated that near-ly matches SRAM speed. DRAM and logic technolo-gies have been largely decoupled as specializationdemands fine-tuned process technology. Thoughthe technology differences mean that additionalprocess steps and costs are required to embed

DRAM cells, in many cases higher performance isworth the extra cost. Embedded DRAM arrays areideal for growing demands for directory and cacheapplications on microprocessors. The DRAM indus-try therefore has the opportunity to branch into newapplications.

DRAM played a critical role in establishing Moore’sLaw, leading the industry in technology developmentand enabling major improvements in computing sys-tems. The DRAM industry is far from over, eventhough its leadership role is no longer as strong.

Although the pace of increase of bits per chip mayhave slowed down, the pace of progress continuesand the enduring legacy of DRAM technology willnever disappear.

References

1 Moore, Gordon E., Electronics, Vol 38, No. 8, April19, 1965.

2 Moore, Gordon E., Proceedings of IEDM, 1975, p.11

3 “Field-Effect Transistor Memory DRAM" (U. S. PatentNo. 3,387,286. 1968)




Foreword. This article charts thestory of Dynamic Random AccessMemory and its crucial role in theinter-twined development of boththe computer and semiconductorindustries. It is based on the workof the author in the design, speci-fication and test of DRAM overmore than thirty years. During thistime, it evolved from a chip with1024 (1K) bits to parts in produc-tion having 256 mega bits. This bitdensity increased by a factor of 4every three years or so, partly as aresult of design sophistication,process complexity and anincrease in chip (die) size. Butmostly it came from the reductionsin feature sizes from 10 microns orso to around 0.1 micron. Over theyears the trend has been known as“Moore’s Law” after an observationby Gordon Moore. Apart fromdriving the semiconductor indus-try, it has been the single mostimportant enabling technology ofthe computer world and its tenta-cles reach into every aspect ofmodern life.

The Beginnings. From the earliestmachines up to today’s PC’s, theusefulness of computers has beendependent on the size and per-formance of their memories. Thefirst machine ever to run a pro-gram stored in its memory, theManchester “Baby,” had anadvanced memory (for its day),storing 1K and later 2K bits in a“Williams tube”.1 Fig.1.

(As a personal aside, its inven-

tor (to credit Tom Kil-burn) was this author’sexternal examiner forthe doctorate!) It had apleasing link to theDRAM in that each serialword could be randomlyaccessed and was storedas an electron chargewhich needed to berefreshed every 300 to400 microseconds. Thecharge was stored on theface of a Cathode RayTube (CRT), as vacuumtubes had yet to be sup-planted by transistors, never mindsilicon chips, in 1947. Machinesusing the Williams tube includedthe IBM 701 and 702. The ideasurfaced again in the “BEAMOS,” adevice from GE with an electronbeam in a vacuum and an unstruc-tured silicon target.2

The next standard approach tobuilding memory was the magnet-ic core.3 Fig.2. In one respect, thatwas a step backwards as each bitrequired threading wires throughminiature toroids. When siliconchips using Metal-Oxide-Silicon(MOS) technology could be

packed with hundreds and thenthousands of transistors, memorycould get back to having individ-ual bit storage locations that didnot need separate assembly.

IBM did pioneering work aimedprincipally at improving the speedof memories in its own computers.However, it was Intel, founded byBob Noyce and Gordon Moore to

make memory chips, that in 1972made and sold in volume a chipthat is sometimes called after afamous aircraft, “the DC 3” of theindustry.4 The i1103 was a 1KDRAM chip made with silicon-gatep-channel technology. It had 32rows and 32 columns of memorycells, each having three MOS tran-sistors. Fig.3.

When charge was stored on thegate of an inverter transistor, itturned it “on” and the remainingtransistors were used to write inthe data signal and to subsequent-ly read it out. Thus, the bit statewas “refreshed” every 2ms with a“refresh amplifier” at the top ofeach column. The chip ran on acomparatively high drain voltageof -17V and it was found to need abias supply of +3V between the nsubstrate and the p-channelsources to ensure minority carriersin the substrate did not attack thestored charge in the cells. Substratebias was to play a key role in allDRAM history, and the need for anextra pin made 18 pin dual-in-linepackages a memory standard(rather than the then-standard 14pins for logic).

Being on the edge of processfeasibility, the i1103 was difficult tomanufacture. It also suffered anumber of “pattern sensitivity”problems because its writecolumns floated, rather than beingheld to a set state at keymoments.5 These issues and theneed for buffers to drive high level

DRAM – A Personal ViewR.C. Foss, Founder and Retired Chair, Mosaid Technologies, Inc., [email protected]

Fig.1 Operation of Williams TubeMemory.

Fig.2 16 x 16 Core Memory (1951).

Fig.3 i1103 : Sources of Pattern Sensitivity.

© 2008 IEEE



TECHNICAL LITERATUREinputs, made it hard to use as well.Despite this, its cost fell below 1cent/bit, which seems ridiculouslyhigh now but started to competewith the core memories of the dayat the system level. A factor in itsacceptance was a second-source,licensed by Intel to MicroSystemsInternational in Ottawa, Canada(where the author worked up untilits closure in 1975). A few othercompanies offered their own inde-pendently developed parts, but themanufacturing difficulties led tofew successes.

Intel followed the i1103 with ann-channel 4K bit device, the i2107.This retained the 3T cell, putting itat a density and cost disadvantagecompared to the then-emergingsingle transistor ( 1T ) cell device(next section). However, it didhave lower power than the first 1Tcell parts and so found a nichemarket with Bell Labs. As theyremained responsible for payingthe power (and air conditioning)bills, the device’s initial cost wasonly one consideration. The chargestored on the now still-smaller gatewas such that it became the firstpart to show “soft errors.” (See“Soft Errors” sidebar, pg 55.)

The emergence of the single-transistor cell DRAM. The idea ofusing just one transistor to bothwrite charge into a capacitor andthen read it out when accessed,emerged well before the first com-mercial parts. IBM’s Dennard iscredited with realizing the meritsof the cell in a patent in 1968. 6 Inthe late 60’s, an early custom MOScompany (AMI), undertook workfor Shell Oil, which needed densermemory for its transportable com-puters used in seismic analysis. Asa result, Shell finished up owningsome DRAM patents which it usedto collect royalties! A key paperpublished by Stein of Siemens 7

introduced the idea of dividing thebit line and placing a flip-flop inthe center. This served as a differ-ential sense amplifier for the mod-est signal developed as the smallcell capacitance shared its chargewith larger capacitance of the bitline on one side, with the bit lineon the other side serving as a ref-erence. As the sense amplifier

developed a full logic swing, itautomatically restored the signalback in the cell. Fig.4.

The first commercial part featur-ing this cell and sense amplifierarrangement was the n-channelTMS 4030 from Texas Instruments.This used a 12V supply and a –3V(later –5V) substrate bias and con-sumed significant power. Like thesubsequent i2107A from Intel andsome other contemporary 4K parts,the sense amplifier flip-flop hadpull-up loads that drew current dur-ing the active cycle. Thus, there wasa trade-off between the powerdrawn and the cycle time as the bitline was restored high. Although thesupply was 12V, the part couldaccept standard TTL (Transistor-Transistor-Logic) logic levels,although the poor design of theaddress input buffer meant it stillreally needed a special driver. Thepackage standard for this generationwas a 22-pin 0.4” pin spacing dual-in line (DIP), though this was laterreduced to an 18-pin 0.3” DIP tocompete with the newly emergingmultiplexed address parts.

Address Multiplexing. The nextmilestone in the DRAM story wasthe establishment of the address-multiplexed part which set thebasic functional standard specifica-tion for some two decades. 8 Thisis credited to Bob Proebsting ofMostek, who had introduced theidea to the market around 1975 inits MK4096 4K part. The key con-

cept was that in the operation of aDRAM, the row address wasrequired first to select all the cellson one column. Only after sensingwould the column address be need-ed to select which column was tobe written into or read out so that aRow Address Strobe (RAS bar as itwas active low) could time the rowaddresses and a corresponding CASbar would follow to feed in the Col-umn addresses. RAS/CAS memorieswould go though multiple genera-tions for the next two decades untilthe Synchronous DRAM (SDRAM)would be standardized by JEDEC(Joint Electron Device EngineeringCouncil), the industry standardizingbody. Even then, the command sig-nals , would keep RAS and CASnames to ease understanding. Mul-tiplexing the address pins in thisway not only reduced the pin countneeded but offered other functions.For refreshing the cells, no columnaddress was needed, hence “RAS-only refresh.” After a row wasselected defining a “page” of data,several columns could be rapidlyselected in “page mode,” althoughthe pioneering part, the MK4096was only a limited success as itused a more complex process thanits competitors and did not usethe emerging standard circuitapproach of a balanced senseamplifier. This was all to changewith the circuit genius of PaulSchroeder. The MK4027 replacedthe earlier 4K and a closely related16K, the MK4116 was to be a land-

Fig.4 One-Transistor Cell with Sense/Restore.




mark part in the industry. 9,10

Fig.5.

The 16K and the MK 4116. TheMK4116 was the definitive designof the 16K generation. Every partmade by every maker was eitheran exact copy or at least owed agreat deal to its design, with thesole exception of Fujitsu. Theauthor’s company, MOSAID, alonesold its own version of the designto four companies and in theprocess standardized its nomen-clature for the internal interfacesof the part. Cell size wasreduced by the introduction of asecond layer of polysilicon. Fig.6.

Power was minimized by eliminat-ing sense amplifier pull-ups andinstead precharging bit lines to thefull 12V-supply level. The columndecoder was placed symmetricallyin the center to give balancedaccess to both halves of the bitline. A novel clock buffer designminimized the power consumed inestablishing charge on the “boot-strap” capacitor. Fig.7.

This further increased speeds inthe peripheral circuits. These clockbuffers also drove the addressinput buffers that were themselvesinternally multiplexed to save sili-con area. To ease debug testing, aningenious “margin test” modeswitched the internal write driversfrom operating with the 12V drainvoltage supply, VDD, to the 5VTTL I/O supply, Vcc, but onlywhen an “illegal” low CAS barinput level was used. This allowedexploration of the cell operatingmargins by varying the levels writ-ten into the cell. 11

The 4116 would be developedthough “shrinking” the die in revi-sions A through G, each revisiongiving further improvements incost and performance. The “F” ver-sion was found to have enhancedsoft-error issues. The 16K genera-tion was to be the last to use 12V,5V and –5V supplies and was thelast generation to be dominated byUS semiconductor companies serv-ing the merchant market.

Achieving a 5V-only part. Thenext generation, 64K chips, need-ed line widths that could not allowtransistors to operate on 12V sup-

plies. Attempts were made by BellLabs 12 and IBM to establish supplylevels around 8 volts but there wasno market acceptance as the nextlower voltage was seen as the 5Vsupply, already in widespread usefor logic devices such as TTL. Tak-ing such a big jump was seen as adifficult design problem. The tran-sistor threshold voltage could notbe scaled proportionately and sothe cell “one” level would becomean issue. Indeed, the MK4116 run-ning with its bit line precharged to12V could have as little as only 8Vas a cell “one” level. This was dueto the back-gate effect of source tosubstrate potential enhanced bythe narrow channel effect in theaccess transistor with its gate at12V. The eventual solution to thisproblem was to bootstrap theword line level by at least athreshold voltage above the new5V supply. A less obvious difficul-ty became evident in eliminatingthe –5V substrate bias supply. A“pumped” supply was possible butcreated new problems. One wasthe risk that a diode between thepumping transistor and the sub-strate would conduct and injectminority carriers into the sub-strate. The other was peculiar to4116-type circuits, with the com-mon source point of the senseamplifier flip-flop floating just onethreshold voltage lower than thebit lines. With no decouplingcapacitor on the substrate supply,the unselected row decoderskicked their diffusion capacitancelow. The substrate level then fell.This in turn coupled into thesense amplifiers, sufficient to havethem start to sense their ownunbalance before any signal tosense existed! Fig.8.

Solving all the 5V supply prob-lems took a little longer than theusual three-year generation gap andin that time, Japanese makers wouldemerge as major players. 13,14

Mostek would design a part rad-ically different in its circuit designfrom the MK4116 aimed at fixingsome of its problem points. Manypeople moved from Mostekincluding a talented designer, Den-nis Wilson, who went to a newcompany in Boise, Idaho, MicronTechnology. Its first product was a

Fig.5 4116 : Precharged High Bit Line.

Fig.6 MK4116 Double-poly Cell.

Fig.7 Schroeder Clock Buffer, DelayStage, Dynamic R-S Flip-Flop used inMK 4027 4K and MK4116 16K.




successful 64K, subsequently alsobuilt under license by Samsung,ITT Semiconductor and Com-modore personal computers.

Japanese Design Approaches. Aquite different design philosophywas to become evident in Japanese64K designs and generations. TheMK4116 had spotlighted the suc-cess of highly original designs.Indeed, a designer’s career wouldget a boost from an original paperat the International Solid State Cir-cuits Conference (ISSCC). Cultural-ly, the Japanese emphasized ateam approach and showed lesstendency to suffer from NIH (Not-Invented-Here!) syndrome. Unfair-ly seen as just copyists in this as inother areas, they would start with asuccessful concept and then fur-ther develop and improve it.15 So,for example, the Hitachi 64K 16

used a folded bit line but still usedscaled 4116 style circuits.

The folded bit line had beeninvented in at least three compa-nies in the 4K era. By ”folding” thebalanced bit line halves to lie par-allel, several advantages accrued.Better balance, even to noise fromsubstrate coupling and also sim-pler column access and simplercolumn shorting for precharge setup, were key benefits. Despite this,the Hitachi 64K design retained themore complex circuitry that hadbeen used in the MK 4116 to effec-tively tie together the bit linehalves! As will be seen, whenComplementary MOS (CMOS)using both n and p-channel tran-sistors became the normal way ofbuilding DRAM, the Japanese, bythen dominant, were to still retain

the old n-channel bootstrapapproach to having the word linedriven above the supply voltage.

Early CMOS Work. The 256K gen-eration was still n-channel, withFujitsu a leader surprisingly notusing the folded bit line as it had inits 16K. However, two companiespioneered the use of CMOS. Onewas Intel in its last attempt at theDRAM market. A key feature ofIntel’s 256K was its use of redun-dancy. Spare rows and columns toreplace defective ones or defectivecells were selected by blowingfuses at wafer probe. Redundancywas to become universally adoptedfor yield improvement, despiteearly misgivings on reliability. Intelhowever, abandoned the DRAMmarket and moved to become theworld’s leading microprocessorhouse while continuing memorywork only for non-volatile prod-ucts. The other CMOS pioneer wasINMOS, a company funded by theBritish Government with its memorydevelopment team in Colorado. Thatgroup was headed up by PaulSchroeder. Its innovative CMOS256K was licensed to Hyundai andthe Japanese company NipponMiniature Bearings (NMB). As anewcomer to semiconductors, NMBevidently saw its business in electro-mechanical products evolving inother directions! INMOS had man-agement problems not unrelated tothe geographic split and their back-ers ! So it was that CMOS processinghad to wait for the 1M generation.

The CMOS 1M. All the major (andseveral smaller) Japanese semicon-ductor makers were now the dom-

inant suppliers of DRAM. The lead-ing 1M was clearly that built byToshiba. Its design was solid andconventional and, as alreadynoted, was to keep the n-channelapproach to boosting the wordline. Fig.9. It was licensed toMotorola and also to Siemens, andthe form of its CMOS processinspired several other houses.

As something of a standardprocess now existed to work with,MOSAID began work on a designbetter utilizing CMOS capabilities.The difficulty with using a boot-strap approach to driving the wordline was in designing a circuit giv-ing a high enough level withoutover-driving nodes to where thelevel was greater than could safelybe maintained. While this was notinsoluble with 1M parts, it wouldclearly be an issue in later genera-tions as feature sizes werereduced. The solution was foundin using a pumped supply at alevel set by feedback-control to beused by the word line driving cir-cuits.17 This required significantdepartures from established cir-cuits in several areas.18 However, asuccessful 1M chip was built andthe use of feedback controlallowed it to subsequently scaleunchanged to 4M processing.Fig.10.

In fact, with some enhance-ments reducing standby power, ithas been successfully used rightthrough to the current generation.As had been foreseen, with varia-tions, the use of a pumped supplyreplacing the bootstrap techniquebecame the industry’s standardapproach.

Process sophistication. Theaddition of the second layer ofpolysilicon in the 16K had marked

Fig.8 Coupling via a floating Substrate.

Fig.9 Double-Bootstrapping a WordLine.




an early departure from processingused in other products. Thisallowed more capacitance in asmaller cell area. Capacitance asdetermined by the square of lineardimension and oxide thickness,was falling relatively faster thansimple feature size scaling. A fixed-target value was set in the range 30to 50 fF to both ensure an ade-quate ratio between cell and bitline capacitance (to achieveenough signal sensing margins)and, as was being discovered, forenough stored charge to resist softerror effects. By the time 4M den-sities were reached, newapproaches were needed toachieve sufficient capacitance. Asin construction work, the only pos-sibilities were to dig down or buildup! Both approaches are still used.One involves etching a hole in thesubstrate to build a “Trench”capacitor. Fig.11.

This figure shows the early ver-sion, whose problem was thatdepletion regions around thetrench could reach an adjacentstructure. This was fixed by arrang-ing for the cell stored charge to beon the inside of the trench. Thealternative was to use more layers

of conductor and dielectric abovethe surface, a “Stacked” capacitor.This requires additional processingto restore a reasonably flat surfacetopology.

With the increase in mask layernumbers (6 for a 4K to around 30for a 256M), far smaller featuresizes, bigger diameter wafers (10going to 30cm) and cleaner envi-ronments to achieve yields of gooddie, the cost of manufacturing facil-ities has increased exponentially.$30 million would buy a fabricationline for 4K parts. Today, a fab linecosts upwards of $5 billion. Notsurprisingly, the industry has con-solidated to the extent that only ahandful of DRAM suppliers remain.

The change to SynchronousDRAM (SDRAM). Starting from thepioneering 4K DRAM right up to16M (six generations!), the basicRAS/CAS specification hadremained the industry standard.Numerous additions had beenmade over the generations. Forexample, on-chip row-addresscounters were added to allow theDRAM chip to refresh itself. Never-theless, the pressure to maintainback compatibility of function withat least the previous density wasvery strong. Pushing standardDRAM to the limits of performanceand functionality is illustrated in anIBM paper describing a 16M. Thishad both redundancy and errorcorrection as well as a mode regis-ter to define additional functions. 19

Although density (and so cost) andpower consumption per bit had allimproved by orders of magnitude,there was remarkably littleimprovement in speed perform-ance. Access time to a random bit

of data, about 150 ns in a 4K, wasimproved by only a factor of threein the 16M.

In part this was due to the reten-tion of the TTL interface standardwhose interface specifications hadbeen set in the mid 1960’s! The inde-pendent asynchronous timings of theinputs and outputs timed to 10% and90% levels were difficult to marrywith increasing system clock speeds.In the early 1990’s, the issues wereall addressed in the JEDEC standardscommittee. This resulted in a newstandard for Synchronous DRAMissued in November, 1993 as part ofJEDEC standard JC21. Contributionsmade by representatives of suppliersand users from many companies hadbeen incorporated. All signals weretimed with reference to a singleclock which could operate at fre-quencies of up to around 100Mz.20

To allow for operation at a range offrequencies and for various bitcounts in bursts of data, on-chip reg-isters could be programmed in a set-up mode. All this was a huge changein the complexity and sophisticationof DRAM functioning, but eased thetask of system designers as comput-er speeds were increasing dramati-cally. Without the change to SDRAM,memory performance would limitwhat processors could achieve evenwhen using cache memory architec-tures to speed access to frequentlyused data.

Double Data Rate SDRAM (DDRSDRAM). As SDRAM was widelyadopted, it became clearer that therewere some changes needed in thebasic specification. The challenge ofa proprietary specification promotedby RAMBUS and supported for awhile by Intel had been fought off by

Fig.10 Regulated Supply System for Word Line.

Fig.11 Cross Section (Stored Chargeon Outside).



TECHNICAL LITERATUREthe performance of SDRAM, but fur-ther speed enhancements were need-ed. DDR matched the frequency ofthe basic clock with the frequency of10101…. data streams by synchroniz-ing to both edges of the clock. Adelay-locked loop matched the tim-ing of the output data and its match-ing data strobe to the input clock. 21

The JEDEC standard for DDRappeared in June 2000, JESD - 79.Most importantly, an interface specifi-cation appropriate to the high speedswas standardized. An earlier arrange-ment using a symmetrical drivearound a mid-point level had beenstandardized as “CTT” in JESD - 8-4 inNovember 1993. However, the con-temporary SDRAM’s still retained aTTL specification. CTT was improvedand standardized by EIAJapan andthen adopted by JEDEC as JESD- 8-8“SSTL.” This had the same symmetri-

cal drive around a mid-point level butadded Series Stub Terminating resis-tors (hence SSTL) to suppress trans-mission line reflection effects. PresentDDR2 memories, JESD-79-2, repre-sent further enhancements in speedperformance and avoid the need forseparate external discreet resistors inthe data-path. DDR3 is now expectedto become a mainstream part in 2008.Interestingly, progress in bit density isno longer the main thrust in DRAMdevelopment: densities now doublerather than quadruple each genera-tion, from 128M to 256M to 512M.Instead, the driving forces are per-formance and power (DDR3 oper-ates on 1.5V).

Conclusions. In the broad field ofsilicon chip circuit design, the sheerscale of modern parts has forcedincreasingly structured design

methodologies with Computer-Aided-Design tools taking over virtu-ally all the traditional tasks of the cir-cuit designer. Exceptionally, over thedecades, DRAM design has remaineda pinnacle of the circuit designer’s art.New circuits interacting with creativelayout combined with a deep under-standing of transistor behavior havebeen involved at every stage and inevery generation. The competitivepressure to better performance andlower costs in high volumes hasbeen, in this author’s view, the keydriver for the semiconductor industry.Often it has been creative individualswith broad multi-disciplinary back-grounds who have, in turn, drivenDRAM advances. Just a few havebeen cited in this piece. But thisauthor is proud to have met andknown many of them from manycompanies in many countries.

Soft Errors. Starting most famously with the 1K1103, early DRAM designs, showed that errors couldbe found that depended on certain patterns of dataor address. Tests were created to screen for sucherrors and many test patterns carried over to laterparts with quite different problems. Of course, man-ufacturing defects were also detected by the generaltest sequences that were used. Bit-map testing allow-ing an engineer to see error patterns helped greatlyin understanding what had gone wrong in a speci-men chip.

The discovery that DRAM’s could exhibit “softerrors,” in which random bit locations could losetheir stored contents caused great concern. Therewas no way to test for susceptibility, and a bad bitin a stored program could and did cause a systemcrash. The source of the problem was discoveredby Intel and published by May and Woods in aclassic paper. 22,23 An alpha particle (helium nucle-us) striking the silicon did not permanently dam-age the crystal structure but did create hole-elec-tron pairs. These occurred along the ionizationtrack, concentrated as the particle came to a stop.The million or so electrons thus created as minor-ity carriers in the p-type substrate represented acharge of around 150 fC. These could be attractedto either a cell or an n-diffusion in the bit-line/sense amplifier structure. Given a 3V signalmargin in a 50 fF cell (a charge of150fC), signalcould be lost, particularly if the particle had strucka glancing blow. Even a Static RAM using highresistance loads was found to be vulnerable witheven less “stored” charge. Fig. 12.

With a single particle sufficient to cause a dataloss, even minimal radio-active contamination was aserious concern. A particularly bad material was gold

with a thorium contamination. Packaging with a wirebond termination pad at just a higher elevation thanthe chip made for a prolific source, but just aboutany material could serve, including material of thechip itself.

The counter-measures were to ensure a mini-mum cell capacitance, control of materials andmodifications of the substrate doping profiles tohelp repel wandering minority carriers. As geome-tries shrunk, there was also a fortunate tendencyfor a single cell to have a smaller cross-sectioncapture area, minimizing the collected charge. Inthe context of a personal computer using no error-correction, common experience suggests that adata error or crash is much more likely to be asoftware problem. After the publication by Mayand Woods, one computer company executivenoted that both his hardware designers and hisprogrammers would each have matching comple-mentary excuses!

Fig.12 Alpha Strike on R-Load Static RAM




About the Author

Richard C. (Dick)Foss, Founder andRetired Chairman ofthe Board of MOSAIDTechnologies Incor-porated, was born in1936 and educatedin the U.K. He

joined the EMI group as anapprentice in 1952 and worked onthe design of the first EMI businesscomputer – a vacuum tubemachine. Simultaneously, he stud-ied for a higher National Certificatein Electrical Engineering and Grad-uate Membership of the IEEE,passing with distinction in 1956.

A scholarship then took him tothe University of Durham, wherehe studied for his B.Sc. in ElectricalEngineering (awarded with FirstClass Honours in 1959) and hisPh.D. in Electronics (awarded in1964 after the work was used in

missile telemetry systems by EMI).His career then turned to micro-electronics with the Plessey Com-pany, where he led a pioneeringcircuit design group with manycreative successes in linear ICs,high speed counters (the subject ofa 1968 International Solid-State Cir-cuits Conference paper) and earlyMOS devices.

In 1970, Dr. Foss left the U.K. tojoin Microsystems International(MIL), a Canadian company locatedin Ottawa, Ontario and worked invarious positions including head ofdesign, MOS engineering managerand new products manager. Togeth-er with a colleague, Robert Harland,he worked on a trend-setting 4KDRAM that was the subject of a 1975ISSCC paper. At its closure in 1975,MIL had become the second largestsupplier in the world (after Intel) ofMOS memory and microcomputers.

Richard Foss and Robert Har-land founded MOSAID in 1975.Dr. Foss held various positionswith the company, including Pres-ident and Chief Executive Officer.He served as a Director from 1975and was Chairman of the Boardfrom 1984 until his retirement atthe end of 2001. He currentlyserves on the Technical AdvisoryBoards of MOSAID and InnovativeSilicon in Lausanne. He also assistsin the licensing of key memorypatents granted to him while activein MOSAID. Many major compa-nies in the industry are nowlicensed under these patents.

Dr. Foss has published numer-ous papers pertaining to semicon-ductor design, including invitedpapers at major conferences. Hewas also elected a fellow of theIEEE for “leadership in the designand testing of memory circuits.”

References1) ”A storage system for use with binary

digital computing machines” F.C.Williams and Tom Kilburn. Proc. IEEVol.96 Pt II April 1949 pp 183 – 202

2) “BEAMOS. A new Electronic DigitalMemory” W.C.Hughs et al. ational com-puter conference, Anaheim, May 1975

3) “Digital Storage Techniques” W. Ren-wick. Proc. of the 2nd. Oxford Electron-ics Lecture Course, 1966. pp 100 -106

4) “A 3-transistor cell 1024 bit 500 ns MOSRAM” W.M. Regitz and J. Karp. Digest ofTechnical papers ISSCC 1970

5) “MOS Memory cells and their engineer-ing implications” R.C. Foss and J. Moni-co. Colloque international sur les circuitsintegres complexe Paris Dec. 3 – 6th.1974. pp 233 - 239

6) US Patent 3,387,286 Denard7) “Storage array and sense/refresh circuit

for single-transistor memory cells” K.U.Stein et al. Digest of technical papersISSCC 1972. pp 56 -57

8) “A TTL compatible 4096-bit n-channel

RAM’ R. Proebsting and R. Green.Digest of technical papers ISSCC 1973.pp 28 – 29

9) “A 16K x 1 Bit dynamic RAM” Paul R.Schroeder and Robert J. Proebsting.Digest of technical papers ISSCC 1977pp 12 – 13

10) US Patent 4,061,954 Proebsting andSchroeder

11) “Margins and margin testing in dynam-ic RAM” R.C. Foss. 1980 IEEE Test con-ference. Pp 4 – 6

12) “A fault-tolerant 64K dynamic RAM”Ronald P. Cenker et al. Digest of tech-nical papers ISSCC 1979

13) “The 64 Kb RAM teaches a VLSI lesson”R.C. Foss (interview). IEEE SpectrumJune 1981. pp 38 – 42

14) “Rethinking the 256 Kb RAM” RobertBernhard. IEEE Spectrum. May 1982.pp 46 – 51

15) “VLSI memory: a designer’s view point”R.C. Foss. Proc. conference onadvanced research in VLSI. Massachu-setts Institute of Technology, Cam-bridge . Jan.25-27. 1982 pp 94 - 96

16) “A single 5V 64K Dynamic RAM’ KiyooItoh et al. 1980 IEEE International Solid-State Circuits Conference pp 228 – 229

17) “High-Reliability circuit design formegabit DRAM” P. Gillingham et al.IEEE JSSCC, Vol.26, No.8 Aug. 1991. pp1171 – 1175

18) US Patent 5,267,201 R.C.Foss19) “A 50ns 16Mb DRAM with a 10ns data

rate” Howard Kalter et al. 1990 IEEEInternational Solid-State Circuits Con-ference pp 232 –233

20) “High-speed circuits for Mega-bit Syn-chronous DRAM’s Tomasz Wojcicki andR.C. Foss. 4th. International conferenceon VLSI and CAD Oct.15- 18th. 1995,Seoul Korea.

21) US Patent 5,796,673 Foss et al.22) “new physical mechanism for soft

errors in dynamic memories” T.C. Mayand M.H. Woods. Proc. of the 1978International reliability physics sympo-sium and IEEE Trans. Electron devicesEd – 26 No.1 Jan. 1979

23) “Soft error testing” T.C.May et al. 1980IEEE test conference. pp 137 - 149



PEOPLE

Asad Abidi will be recognizedat the ISSCC Plenary in Febru-ary with the IEEE Donald O.

Pederson Award in Solid-State Cir-cuits “for pioneering and sustainedcontributions in the development ofRF-CMOS.” This recognition, within a20-year history of circuit designergreats, is the highest IEEE technicalfield award for Solid-State Circuits.

Abidi’s award has generatedresponses from many experts in thefield, not only for his early and stead-fast advocacy of RF CMOS but alsofor his fundamental developmentwork on the problems essential tomaking RF CMOS a product forbroadly used consumer applications.

According to Akira Matsuzawa,previously general manager forSystem On Chip development atPanasonic and now a facultymember at Tokyo Institute ofTechnology, “Abidi prepared theneeded technical solutions to helpindustry apply the technology. Healso prepared the professionalsthat industry needed to developthe solutions.” Abidi has deliveredmany technical seminars in Japan.“When he teaches,” says Matsuza-wa, “he starts by explaining seem-ingly strange phenomena andtheir basic underlying mecha-nisms. Then he follows up withthe solutions that are fundamentaland yet the smartest.”

Richard Spencer of UC Davisand primary author of Introductionto Electronic Circuit Design (Pren-tice Hall, 2003) calls Abidi a con-summate engineer. “He has alwaysplaced the highest priority on com-ing up with truly useful solutions tosignificant problems, rather thansuccumbing to the temptation of

working on projects that wouldmaximize his publication rate.”

Tom Lee of Stanford and authorof The Design of CMOS Radio-Fre-quency Integrated Circuits (2E, Cam-bridge University Press) countsAbidi as an inspiring pioneer. “Myown thesis work on RF CMOS in the1980s interested absolutely no oneat the time,” he says. “ProfessorAbidi was the first expert I encoun-tered -- in academia or industry --who not only expressed interest, butfelt certain that RF CMOS had abright future. His steadfast advocacyof this position -- despite the nega-tive view held by almost every otherexpert -- went a long way towardestablishing CMOS not only as acredible RF medium, but in manycases, superior.”

Payam Heydari, whose JSSCarticle this fall on “Design andAnalysis of a Performance-Opti-mized CMOS UWB DistributedLNA” was among the top 100downloads in Xplore, points toAbidi as a “role model to manyyounger faculty members” includ-ing himself. But Abidi’s continu-ing and current work on soft-ware–defined radio is Heydari’s“ah-ha” moment, particularlyresearch published in the JSSC(December 2006 and May 2007)that “lays the groundwork forfuture development of multi-stan-dard programmable transceivers.”

Teacher of the teachersWorld class teachers Matsuzawaand Spencer recall Abidi helpingthem to better understand con-cepts with lessons lasting a life-time. Matsuzawa remembers howimpressed he was when Abidishowed him “the mechanism ofAM-PM conversion and frequencyconversion in a voltage controlledoscillator and the appearance of1/f noise in a mixer.” A vivid mem-ory for Spencer from his graduatework on relaxation oscillators atStanford is Abidi’s “very clean geo-metric picture of how noise on thethreshold was converted into jitterand how that conversion depend-ed on the bandwidth of the noiserelative to the slope of the wave-form.”

New Path As Dean at LUMSAbidi is leaving his LA home anda settled 22 year existence atUCLA to begin what he calls anadventure to serve humanity asthe first Dean of a new School ofScience & Engineering in Pakistan(sse.lums.edu.pk). LUMS is a pri-vate endowment-based universitymodeled after MIT and Caltech,with an advisory group drawnfrom those and other reputableinstitutions.

Asad Abidi Recognized for Work in RF-CMOSAnne O’Neill, Executive Director of SSCS, [email protected]

Asad Abidi, IEEE Fellow, member ofthe National Academy of Engineer-ing and Professor for 22 years atUCLA, is now the first Dean of a newSchool of Science & Engineering inPakistan. LUMS is a private endow-ment-based university modeledafter MIT and Caltech.

Nominations Open for 2010 RecipientsNominations for the 2009 recipient of the Pederson Award close 31 January2008. The nomination and reference process takes some thought and effort.So begin now with the inspiration of this year’s recipient fresh in your mind.Discuss with your colleagues, your ideas for potential nominees for thisachievement award. Prepare to advance a nominee for the January 2009deadline. Review the process online. sscs.org/awards/Fieldawards.htm



PEOPLE

Asad Abidi is an IEEE Fellowand a Member of the Nation-al Academy of Engineering.

He received the 1997 IEEE DonaldG. Fink Award, the 1997 ISSCC JackRaper Outstanding TechnologyDirections Paper Award, and theIEEE Millennium Medal and wasnamed a top-ten author by theISSCC. The UCLA Henry SamueliSchool of Engineering and AppliedScience recognized him in 2007with the Lockheed-Martin Award forExcellence in Teaching.

Dr. Abidi obtained the BSc(Hon.) degree from Imperial Col-lege of Science & Technology,London, England in 1976, and theMS and PhD degrees from the Uni-versity of California, Berkeley, in1978 and 1981, all in ElectricalEngineering.

He worked at Bell Laboratories,Murray Hill, NJ from 1982 to 1985,when much of the basic technolo-gy of submicron MOS VLSI wasbeing developed there in theAdvanced LSI Development Labled by Marty Lepselter (inventor ofthe beam lead -- perhaps the firstexample of silicon micromachin-ing), George Smith (co-inventor ofthe CCD), and Harry Boll (inventorof the standard cell and of theauto-refreshed dynamic RAM cell).As one of the few circuit designersin that lab, Abidi’s task was todemonstrate the potential of thenewly emerging submicron NMOSIC technology in high-speed com-munication circuits. This led to thefirst MOS amplifiers developed forGb/s data rates in the then-impor-tant optical fiber receivers. Basedon the belief that the speeds ofsimple MOSFETs would continueto scale upwards with shrinkingdimensions, and that good circuitscould be devised around the pecu-liar characteristics of these transis-tors, this work was carried outamidst much skepticism from pro-ponents of GaAs and BJT ICs, thedominant technologies then forhigh-speed circuits. Years later, thisexperience would shape the gene-sis and development of RF-CMOS.

In 1985 Asad Abidi joined theElectrical Engineering faculty at the

University of California, Los Ange-les (UCLA). In 1989, he took a yearleave as a Visiting Researcher atHewlett-Packard Laboratories toinvestigate A/D conversion atultrahigh speeds. At UCLA, Abidiand his students have researchedanalog signal chains for disk driveread channels, high-speed A/Dconversion, and various analogCMOS circuits for signal processingand communications.

As mobile telephones enteredwidespread use in the mid 1990sand it became apparent that theywould soon lead to an era ofuntethered computers networkedwith wireless devices, the researchcommunity identified many of theimportant hardware and softwarechallenges ahead: low power cir-cuits and systems to conserve bat-tery life, miniaturization of anten-nas, the challenges of transmittinghigh data rates over unpredictablewireless channels, new networkingalgorithms, and so on. The RF cir-cuits in the mobile telephones ofthose days comprised mainly dis-crete circuits with a mix of tech-nologies. Abidi’s research with hisgraduate students at UCLA wasamong the earliest to recognizehow single-chip integration wouldbring about miniaturization, thuslowering power, and addingsophistication and adaptive func-tionality to radios in mobiledevices. Furthermore, he was con-vinced that CMOS was the righttechnology for integrated radios.Practicing RF circuit designers ofthe time did not share this view.

The earliest research in RF-CMOS circuits, as they soon werelabeled, proved that it was possibleto build fully integrated amplifiers,mixers, oscillators, and filters withconfigurations devised to exploitthe unique properties of MOSFETsthat achieved performance levelsonly slightly inferior to the well-optimized discrete or semi-inte-grated circuits in the mainstreambipolar or GaAs technologies.

Had its role remained limited toa cheap replacement of legacy RFcircuits, RF-CMOS would not havemade much impact on industry.

What drove Abidi’s research atUCLA was his belief that the nextgeneration of low power, adaptive,manufacturable radios could onlybe realized when RF and analogcircuits were intimately embeddedinto digital circuits to tune theirperformance, correct their imper-fections, adapt or control theircharacteristics, and otherwiseunburden difficult analog signalprocessing. This is what had hap-pened in wireline modems, themost sophisticated communicationcircuits of the day, and it was clearthat only full CMOS realizationsafforded the mixed-signal integra-tion being sought.

Progress in RF-CMOS evolvedalong these lines. As circuit build-ing blocks grew into integratedreceivers and transmitters, theunique needs of integration led tonew, or at least at that point notwidely used, architectures such aszero IF receivers, constant-enve-lope transmitters based on frac-tional-N phase-locked loops, andso on. The newest generation ofRF-CMOS circuits is so muchshaped by digital paradigms thatmuch of the analog portion of thereceiver uses discrete-time multi-rate signal processing, while in thetransmitter, which is today all-digi-tal, analog waveforms appear onlyat the power amplifier’s output thatdrives the antenna.

As a result of these advances inRF-CMOS, a new paradigm ---thesoftware defined radio-- is takingpractical form, bringing to a con-clusion the long-standing quest fora universal radio device whichtunes, or transmits, any channelcarrying any modulated waveformin any radio band.

The radio transceivers for allwireless networking devices andfor the new generation of mobilephones are mass produced todayas RF-CMOS devices. These real-izations are a far cry from the dis-crete component realizations of the1990s; CMOS has enabled, andmarket forces have compelled, theintegration of processors andmemory on the same chip as theradio.

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The Career of Asad Abidi



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Dr. R. Jacob Baker was presented with theHewlett-Packard Frederick Emmons TermanAward on 14 October at the meeting of the Fron-

tiers in Education Conference in Milwaukee. The award,conferred by Wayne C. Johnson on behalf of the Elec-trical and Computer Engineering Division of the Ameri-can Society for Engineering Education, lauds Dr. Bakeras “an outstanding young electrical engineering educa-tor in recognition of his contribution to the profession.”

Russel Jacob (Jake) Baker was born in Ogden,Utah, on October 5, 1964. He received his B.S. andM.S. degrees in electrical engineering from the Uni-versity of Nevada, Las Vegas, and a Ph.D. degree inelectrical engineering from the University of Nevada,Reno.

From 1981–1987, he was in the U.S. Marine CorpsReserves. From 1985–1993, he worked for E. G. & G.Energy Measurements and the Lawrence LivermoreNational Laboratory designing nuclear diagnosticinstrumentation for underground nuclear weaponstests at the Nevada test site. During this time, hedesigned over 30 electronic and electro-optic instru-ments including high-speed (750 Mb/s) fiber-opticreceiver/transmitters, PLLs, frame- and bit-syncs, dataconverters, streak-camera sweep circuits, micro-chan-nel plate gating circuits, and analog oscilloscope elec-tronics. From 1993–2000, he was a faculty member inthe Department of Electrical Engineering at the Uni-versity of Idaho. In 2000, he joined a new electricaland computer engineering program at Boise StateUniversity where he was Department Chair from 2004

to 2007. Also, since 1993, he has consulted for variouscompanies and laboratories including Micron Tech-nology, Amkor Wafer Fabrication Services, TowerSemiconductor, Rendition, Lawrence Berkeley Labora-tory, and the Tower ASIC Design Center.

Dr. Baker holds over 200 granted or pendingpatents in integrated circuit design. He is a member ofthe electrical engineering honor society Eta KappaNu, a licensed Professional Engineer, and theauthor/coauthor of the books: CMOS: Circuit Design,Layout, and Simulation, CMOS: Mixed-Signal CircuitDesign, and DRAM Circuit Design: Fundamental andHigh-Speed Topics. His research interests are in theareas of CMOS mixed-signal integrated circuit designand the design of memory in new and emerging fab-rication technologies. He was also a co-recipient ofthe 2000 Prize Paper Award of the IEEE Power Elec-tronics Society.

About the Terman AwardThe Frederick Emmons Terman Awardis presented annually to an outstand-ing young electrical engineering edu-cator by the Electrical and ComputerEngineering Division of theAmericanSociety for Engineering Education. TheTerman Award, established in 1969 by the Hewlett-Packard Company, consists of $5,000, an engravedgold-plated medal, a bronze replica of the medalmounted on a walnut plaque, and a parchment cer-tificate. The recipient must be an electrical engineer-ing educator who is less than 45 years old on June 1of the year in which the award is presented and mustbe the principal author of an electrical engineeringtextbook published before June 1 of the year ofhis/her 40th birthday. The book must have beenjudged by his/her peers to be an outstanding originalcontribution to the field of electrical engineering. Therecipient must also have displayed outstandingachievements in teaching, research, guidance of stu-dents, and other related activities.

About Frederick Emmons TermanFrederick Emmons Terman received hisA.B. degree in chemistry in 1920, thedegree of Engineer in electrical engi-neering in 1922 from Stanford Universi-ty, and his Sc.D. degree in electricalengineering in 1924 from MassachusettsInstitute of Technology. From1925–1965 he served as Instructor, then

Professor of Electrical Engineering, Executive Head ofElectrical Engineering Department, Dean of theSchool of Engineering, Provost, Vice-President, and,finally, as Acting President of Stanford University.

Among the many honors bestowed upon him were:the IEEE Medal of Honor; the first IEEE Education

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R. Jacob Baker Honored at FIE Conference in October

Wayne C. Johnson, a Vice President of Hewlett Packard(right) presented Dr. R. Jacob Baker with a parchmentcertificate for this year’s Frederick Emmons TermanAward.


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Medal; the ASEE’s Lamme Medal; the 1970 HerbertHoover Medal for Distinguished Service to StanfordUniversity; an honorary doctor’s degree by Harvard; adecoration by the British government; the PresidentialMedal for merit as a result of his war work; and the1976 National Medal of Science from President Fordat a White House ceremony. Dr. Terman was a pro-fessor at Stanford University when William Hewlettand Dave Packard were engineering students there. Itwas under Dr. Terman’s guidance in graduate workon radio engineering that Mr. Hewlett built the first

tunable and automatically stabilized Weinbridge oscil-lator. Partially through Dr. Terman’s urging, Hewlettand Packard set up their partnership in an old garagewith $538 and the oscillator as their principal assets.

Dr. Terman died in December 1982. It is in appre-ciation of his accomplishments and guidance thatHewlett-Packard is proud to sponsor the FrederickEmmons Terman Award.

More information about the Frontiers in EducationConference may be obtained at http://fie.engrng.pitt.edu/fie2007/.

Van der Spiegel Acclaimed for EducationalInnovation at IEEE EAB Meeting Katherine Olstein, SSCS Administrator, [email protected]

SSCS Chapters Chair Jan Van der Spiegel of the Uni-versity of Pennsylvania received the IEEE 2007 EABMajor Educational Innovation Award “for his efforts

in promoting undergraduate research and creatingrobust opportunities for undergraduate students toenrich their education through integrative researchexperiences.”

His nominator, IEEE Fellow Kenneth R. Laker said,“Professor Van der Spiegel is a highly accomplished

scholar and educator in electrical engineering whohas dedicated his career to successfully bridgingresearch and teaching. He has won all of the Univer-sity teaching awards for which he was eligible.”

According to IEEE President Leah Jamison, educa-tion is a high IEEE priority. In her remarks at the EABceremony, she said, “In a recent “pulse” survey, a rep-resentative panel of IEEE members ranked “Growthand nurturing of the profession: encouraging educa-

Dr. Moshe Kahn, IEEE Educational Activities Vice President (left) and Dr. Bruce Eisenstein, Chair of the EAB Awards andRecognition Committee (right) presented Jan Van der Spiegel with the IEEE 2007 EAB Award for Educational Innovationin a ceremony at the IEEE Educational Activities Board Awards Dinner in Boston, MA on 16 November, 2007.



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tion as a fundamental activity of engineers, scientistsand technologists at all levels and at all times; ensur-ing a pipeline of students to preserve the profession”as the most important of our core values, with 92%agreement.”

When Dr. Van der Spiegel was Undergraduate Cur-riculum Chair in 1994 – 1997, he led the developmentof a new computer and telecommunications engi-neering (CTE) degree program that was one of thefirst to integrate computer engineering with telecom-munications and networking. He also created one ofthe first FPGA-based digital systems courses for soph-omore engineering, computer science, and telecom-munications majors.

In 1986, Prof. Van der Spiegel established theSummer Undergraduate Fellowships in Sensor Tech-nologies (SUNFEST) program at Penn and has beenits director and champion ever since. Over the pastten years, nearly seventy percent of SUNFEST’s 190students have gone on to graduate school. The pro-gram became a model for the National Science Foun-dation’s Research Experience for Undergraduates(REU) program, and has received continuous NSFfunding since it began in 1987. The Penn Microfab-rication Facility, directed by Dr. Van der Spiegel inthe past, and the Center for Sensor Technologiesdirected by him today, contribute resources to SUN-FEST students.

The ten-week SUNFEST experience provides stu-dents with an opportunity to work on an interdisci-plinary research project under the guidance of aPenn faculty member and alongside other graduatestudents. In addition to doing research, the stu-dents participate in workshops on how to giveeffective presentations, write technical reports, andapply for graduate school. They also learn aboutethics in engineering and science. The programmakes a special effort to include students from col-leges with little or no opportunity for undergradu-ate research activities, and also focuses on attract-ing students from groups underrepresented inresearch fields in engineering.

In addition to SUNFEST, Professor Van derSpiegel has brought undergraduates into hisresearch projects though Penn’s capstone seniordesign course. Over the past ten years, he and his

graduate students have mentored more than forty-three senior design projects, often advising three ormore design teams in a given year. “As the instruc-tor in charge of senior design, I know first handhow students working with Professor Van derSpiegel have developed and matured under hismentorship,” Dr. Laker said. “More than one-half ofhis senior design teams have won senior designawards at the Department and School of Engineer-ing and Applied Science levels.”

Professor Van der Spiegel developed courses onMicroelectronics and Emerging Technologies forPenn’s Executive Master’s in Technology Manage-ment weekend program, a blend of technology andbusiness that is targeted to high technology man-agers. Since they have been in industry for at leastfive years and have backgrounds spanning all theengineering disciplines, EMTM courses are very dif-ferent from those taught in other graduate pro-grams. The “Emerging Technologies” course devel-oped by Prof. Van der Spiegel is a lecture seriesintroducing students to advancements that areexpected to significantly impact industry. It is theonly course in the program that EMTM students takeevery semester.

Professor Van der Spiegel’s commitment to andimpact on engineering education has extended tocampus life. As House Master of Ware College Housefrom 1992-1998, he organized extracurricular activitiesthat realized his goal of integrating engineering edu-cation into campus life in a manner that enriched bothengineering and non-engineering students.

Prof. Van der Spiegel has been an active volun-teer for the IEEE Solid-State Circuits Council/Soci-ety for more than 20 years and has served asChapters Chair since the Society was formed tenyears ago. During his tenure, the number of chap-ters has grown from one to more than 60. Chap-ters provide continuing professional educationthrough guest seminars and short courses formembers in their local areas. Professor Van derSpiegel has also served as Technical ProgramChair of the International Solid-State Circuits Con-ference (ISSCC 2007), the world’s foremost confer-ence on semiconductors, and is a DistinguishedLecturer of the Society.

“Encouraging education and

ensuring a pipeline of students to

preserve the profession is the most

important of our core values.”Leah Jamison, IEEE President

“More than half of the 43 senior

projects mentored by Prof. Van der

Spiegel in the past decade won

departmental design awards.”Kenneth R. Laker


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Avery successful and warmevent was hosted by theIEEE SSCS Greece Chapter

on 18 September, 2007 at the Cen-tral Library of the National Techni-cal University of Athens. The idea,simple and effective, was to

arrange for a combined visit offour Distinguished Lecturers(instead of one at a time) whowould speak in a half-day specialevent. This idea, which was con-ceived by the SSCS EducationCommittee Chair, Dr C.K. Ken

Yang, was named the “IEEE-SSCSDL Region 8 Tour” because thesame distinguished lecturers wouldalso visit neighboring Bulgaria dur-ing the same trip.

The invited speakers and theirpresentations were:

Lanzerotti Applauded for Editorship of LEOS Newsletter

Mary Lanzerotti was presented withthe IEEE/LEOS 2007 DistinguishedService Award for dedicated serviceas Editor of the LEOS Newsletterfrom 2001 through 2006 by AlanWillner, LEOS President. In a ceremo-ny during the Society’s Awards Ban-quet on 23 October in Lake BuenaVista, Florida, she received a plaqueand an honorarium for work “result-ing in outstanding changes to thepublication.” The LEOS DistinguishedService Award recognizes outstand-ing contributions by a Society mem-ber to the benefit of the group. Formore information about LEOS seewww.i-leo.org.

SSCS Distinguished Lecturers Visit Athens andVarnaA. N. Skodras, Hellenic Open University, School of Science & TechnologyPatras, Greece ([email protected])

Prof. Takayasu Sakurai University of Tokyo, Japan •“Moore's Law Plus: What are Needed other thanScaling in Interconnects?” solving issues of IC'sby 3D-stacking and large area integrated circuitsbased on organic transistors

Prof. Mircea R. Stan University of Virginia •“Power-aware and Temperature-aware CircuitDesign” power-aware and temperature-awarecircuit design techniques

Prof. Ian Galton University of California, •Performance enhancement techniques for fractional-San Diego, N PLLs

Prof. John R. Long Delft University of Technology, •“Wireless IC Building Blocks in CMOS/BiCMOS” the Netherlands wireless IC building blocks in CMOS/BiCMOS



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In view of the fact that nationalelections had forced many peopleto be out of the city, the caliber anddiversity of the attendance wasgratifying. For those who could notparticipate in person, the programwas streamed to provide access on-line. Remote attendees could posequestions via email or skype to theChapter Chair, Prof. A. Skodras.The event was reported in the thirdissue of the “THE CIRCUIT”www.upatras.gr/ieee/thecircuit.ht

m), a newsletter published quarter-ly in Greek and sent to all CAS/SSCmembers in Greece. The contribu-tions of Prof. N. Hadjiargyriou andProf. N. Koziris of the IEEE GreeceSection were instrumental in organ-izing the tour.

On the day before the program,the group visited the HTCI (HellenicTechnology Clusters Initiative)www.htci.gr), a new and dynamiceffort that supports the creation ofInnovative Technological Clusters

aiming to make the companies thatcomprise them competitive in inter-national markets. The first clusterfocuses on the semiconductor, micro-electronics, and embedded systemssector. Based in Maroussi (Athens) atthe Microelectronics Innovation Cen-tre, it constitutes a reference point forover twenty rapidly developing hightechnology companies, with morethan 650 executives—mainly researchand development engineers—nation-wide.

Ian Galton T. Sakurai M. Stan John Long

At the Hellenic Technology Clusters Initiative (HTCI),from left: T. Chaniotakis, I. Tsiatouchas, V. Makios, I.Galton, J. Long, and M. Stan.

After the program, from left: M. Stan, A. Skodras (Chair, SSCS-Greece), T. Sakurai, I. Galton, and J. Long.

Jordan Kolev, SSCS Chapter Chair,Organizes DL Program at theTechnical University of Varna

Takayasu Sakurai Mircea Stan In the foreground, M. Stan, J. Long, I. Galton.

From left, J. Long, J. Kolev, T. Sakurai, I. Galton, M. Stan.


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Bertan Bakkaloglu Phoenix Section

David Blaauw Southeastern Michigan Section

O Buhler Denver Section

David Chiang Oregon Section

Carl Debono Malta Section

Michael Fischer Central Texas Section

Kyung Han Santa Clara Valley Section

Teo Tee Hui Singapore Section

Chung Chih Hung Santa Clara Valley Section

Wern Ming Koe Dallas Section

Ravishanker Krishnamoorthy Singapore Section

Kent Lundberg Boston Section

Adrian Maxim Central Texas Section

Paul Murtagh Buenaventura Section

Kevin On Xian Section

John Rogers Central Texas Section

Robert Schuelke Twin Cities Section

Akio Ushida Shikoku Section

Fu-Cheng Wang Orange County Section

Yuan Xie Central Pennsylvania Section

Betty Prince Talks in Brazil

SSCS DL Betty Prince chatted with Carlo Requiao daCunha, a faculty member at the Federal University ofSanta Catarina in Florianopolis, after presenting a three-

hour tutorial on "Embedded Non-Volatile Memories" at theCongresso Chip in Rio Conference on 5 September in Rio deJaniero. She also presented the conference plenary addresson “Nanotechnology and Embedded Memories." The meet-ing, which is sponsored annually by the Brazilian Micro-electronics Society, was held in conjunction with the 22ndSymposium on Microelectronics Technology and Devices(SBMICRO 2007) and the 20th Symposium on Integrated Cir-cuits and Systems (SBCCI 2007) in 2007. These conferencescomprise the most advanced forum for integrated circuitsand systems in Brazil.

Congratulations New Senior Members20 Elected in August and September

Call for Fellow NominationsNominations are being accepted until March 1, 2008for the 2009 class of IEEE Fellows.

IEEE Fellows are an elite group from around theglobe. The IEEE looks to the Fellows for guidance andleadership as the world of electrical and electronictechnology continues to evolve. The accomplishmentsthat are being honored should have contributedimportantly to the advancement or application ofengineering, science and technology, bringing signifi-cant value to society.

Revisions to the IEEE Fellow nomination processhave taken place over the past few years, mainly in aneffort to generate more Fellow nominations fromindustry. Fellow nominees are now classified as

Research Engineer/Scientist, Application Engineer/Practitioner, Technical Leader, or Educator.

Candidates for Fellow must hold Senior Membergrade at the time the nomination is submitted andshall have been an IEEE member in good standing (inany grade) for a period of five years or more preced-ing January 1 of the year of election.

Any person, including a non-member, is eligible tobe an IEEE Fellow nominator with a few exceptions.The Steps, responsibilities and forms are online at www.ieee.org/web/membership/fellows/fellow_steps.html

Nominations, references and endorsements may besubmitted electronically.



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Writing a formal proposal for an externalcustomer can be a daunting task thatsends people scrambling for help. In par-

ticular, standard formats and canned sections seemto offer safety.

Unfortunately, these safe approaches are almostguaranteed not to work because they violate the corerequirement of a persuasive proposal: a precise fitbetween benefits offered and perceived needs of thecustomer. Since each customer’s situation is special,no all-purpose strategy can be effective. Instead, youneed an individual approach.

Two Keys to a Winning ProposalWhat are the things that really work with proposalreaders? Here are the two that come up most often:

• An executive summary that states the benefits ofyour solution strongly and ties them clearly to thecustomer’s needs

• A proposal body that backs up the claims of theexecutive summary crisply and without techno-babble

Your first step is to study the customer’s needs asexpressed in the request for proposal, if there is one.(Otherwise, do your own thorough research on thecustomer’s situation.) People usually spend too littletime on this stage of proposal preparation; instead,they waste it on writing up a lot of irrelevant detail inhyper-technical language.

Next, identify the solutions you can offer for thecustomer’s needs and describe them in a trial execu-tive summary. Then use that summary as your guidein developing the rest of the proposal.

Typically, components include transmittal letter,executive summary, background and overview, tech-nical, objectives, work plan, related experience, keypersonnel, facilities and equipment, schedule, cost orbudget, and conclusion. However, the actual titles andorder must carefully follow any guidelines laid out inthe request for proposal.

Four Temptations to ResistWhat makes writers spend a great deal of time, onlyto produce unfocused, overdetailed proposals? Wehave observed four common reasons:

1. Getting overwhelmed by the demands of format.People fear proposals must be very formal and

technically impressive. In truth, they just need tobe persuasive—with no more technical detailthan appropriate for the readers. In particular,remember that the front sections and conclusionare read by everybody on the evaluation team,so keep them brief and nontechnical. Reserveintricacies for the sections specifically labeled astechnical.

2. Writing detail sections before formulating yourmain message in the summary. Beginning withthe executive summary offers tremendous bene-fits, especially if the writing is a team effort. Itfocuses all details on key selling points. From theoutset your document will be leaner and morerelevant, and you’ll have less cutting and editingto do.

3. Falling into features thinking. Especially if youhave not managed to fit your benefits to the cus-tomer’s needs, you may be tempted to switch toa features-based approach to unload all yourselling points. Go back to the beginning: Identi-fy the key needs and work out the winning strat-egy to fill them.

4. Giving in to plain laziness. Pulling standard com-ponents off the shelf and slapping them togetherfor a proposal, after changing a few names andother incidentals, seems so much faster and eas-ier. It is—but what good does it do? You mightas well not write a proposal at all; that would beeven easier and faster, and would get the sameresult! As we said, proposals inherently must betailored to the special needs of the customer.Those needs aren’t sitting around on your shelf.

Cheryl and Peter Reimold have been teaching com-munication skills to engineers, scientists, and busi-nesspeople for 20 years. Their firm, PERC Communi-cations (+1 914 725 1024, [email protected]), offersbusinesses consulting and writing services, as well ascustomized inhouse courses on writing, presentationskills, and on-the-job communication skills. Visit theirWeb site at http://www.allaboutcommunication.com.

This article is gratefully reprinted with permissionfrom the authors as well as with permission from theIEEE Professional Communication Society NewsletterEditor. This article is reprinted from the January/Feb-ruary 2003 issue, Volume 47, Number 1, page 8 of theIEEE PCS Newsletter.

TOOLS:How to Write Readable Reports and Winning ProposalsPart 5: Persuasive External Proposals

Peter and Cheryl Reimold, www.allaboutcomunication.com



CONFERENCES

ISSCC 2008 to Focus on System Integration for Lifeand StyleSSCS Flagship Conference to Meet on February 3-7 in San Francisco

Bill Bowhill, Intel Corporation, ISSCC Program Vice Chair, [email protected]

As semiconductor technology continues itsadvance into the nanometer domain, the rangeof electronic systems is broadening from enor-

mous processing and storage in computing to micro-power and wireless mobile functions.

Design and system integration must master all lev-els of today’s technology jigsaw puzzle to enable thenew and exciting systems which alter our lives andlifestyles in endless ways:

Ultra-low-power-sensor and wireless techniquesthat deliver new tools for advances in medical and lifesciences; entertainment and computing functions thatmerge on the desktop; mobile phones that host awhole range of functions such as on-line information,finance, security and audio/video entertainment.

The integration of these advances into sophisticat-ed systems allows more processing to fit into tinierpackages and brings power consumption down to thepoint that everything can be battery powered in ahand-held device. However, the huge opportunities ofnanometre technology also present daunting chal-lenges: Designers must manage both vast complexityin the digital domain and the realization of high-per-formance analog, RF and interface functions withcomplex device behavior and low-voltage supplies.

ISSCC 2008 will feature presentations that demon-strate ways in which the integration of novel circuitand systems can deliver functions that enrich theusers’ life and style.

Plenary Session• Hyung Kyu Lim from the Samsung Advanced Insti-

tute of Technology will discuss “The 2nd Wave ofthe Digital Consumer Revolution: Challenges andOpportunities.” The rapid advancement of wirelesscommunication and mobile Internet combined withadvances in user interfaces and input device tech-nologies are changing the way people interact.Examples include online social networking,nomadic lifestyles that burst the boundariesbetween work and personal life, and remote med-ical services such as on-the-spot diagnosis andemergency paging.

• New human interface technologies are changing theway people interact with each other and with the vir-tual computing network. Bill Buxton from MicrosoftResearch will discuss surface computing using inter-active display technologies. The talk is entitled “Sur-face and Tangible Computing, and the ‘Small’ Matterof People and Design.” The rapid evolution of elec-tronic technologies, integration techniques, and fab-rication processes has spurred the development of a

wide range of new interactive products. The presen-tation will examine the evolution of large surface-type computing devices and small graspable compu-tational objects and demonstrate that these twoextremes of the computational spectrum can meet ina seamless integrated experience.

• Advanced CMOS technologies and ultra-lower powerdesign are enabling integration of significant compu-tational power into small form factors. Mike Mullerfrom ARM will discuss “Embedded Processing: At theHeart of Life and Style”. As the largest supplier ofprocessor IP to SoC developers, ARM has a uniqueperspective on the problems of performance, cost,and power for mobile products in nanometer CMOS-- a technology that allows great improvements andmore functions for each chip. Nevertheless, power isan increasing problem: While power consumption inthe active state increases with the number and speedof the gates, standby power gets worse due to leaki-er transistors. This presentation will explore how ICsystem developers may address this problem by thebetterment of circuit cells, power optimization, andprocessor architecture, and by better synergybetween hardware and software.

• The final plenary talk discusses the future of com-puting. “Why Can’t A Computer Be More Like ABrain? Or What To Do With All Those Transistors?”will be presented by Jeff Hawkins from Numenta.The age of intelligent machines may be on thehorizon. If so, there will be many opportunities torethink how integrated circuits may play a leadingrole. The brain’s physical structure, like that of themodern microprocessor, constrains how informa-tion is stored. To build machines which approachhuman-transaction throughput rates, data willneed to be organized in hierarchical memorystructures. Hierarchical Temporal Memory (HTM)is a new theory based on the behavior of thehuman neocortex that provides a framework forbuilding models that can be executed on conven-tional computers to dramatically advance artificialintelligence hosted in high-performance computerplatforms.

Regular Paper SessionsThe world’s semiconductor industry and researchinstitutions continue on a fast path of innovation andimproved device performance. Following the PlenarySession, 237 technical papers will be presented in 31sessions over 2 1/2 days. They highlight the latestadvancement in circuit design and technology. Noveldesigns to be presented include:



CONFERENCES• 6 data converters in 65nm and the first in 45nm. A low-

voltage ADC for a sensor application operates down to200mV supply.

• High-performance processors demonstrating improve-ments in both single- and multi-threaded performance.

• The highest level of processor integration ever reported (2billion transistors).

• Micro-architecture and circuit innovations reduce powerconsumption of an x86 processor by 5x.

• A single-chip eye tracker provides extremely high-frame-rate and fast processing for tracking eye movements in realtime.

• A 45nm 3.5G baseband and multimedia-application-processor SoC extends the features and services of next-generation mobile phones.

• Memories: Fastest embedded DRAM macro in bulkCMOS; First GDDR5 DRAM (with quadruple data-rate)developed; First high-volume functional 153Mb SRAMchip in 45nm high-κ metal-gate technology; First-report-ed NAND-Flash memory with three-dimensional siliconintegration in 45nm lithography.

• 60GHz integrated frequency-tripler with quadrature out-puts in 90nm CMOS.

• An op-amp with a 0.33μV offset independent of tempera-ture using a single room-temperature calibration.

• A wireless sensor-node SoC for smart bandaids is used forvital-sign monitoring in body-area network applications.

• The smallest Nuclear-Magnetic-Resonance (NMR) system(2500cm3) is used for detection of bio-molecules.

• The first imager (1.1x1.5 mm2) implanted into a humaneye, partially restoring vision to a blind patient.

• The first fully-integrated 14-band MB-OFDM UWBtransceiver.

• The first dual-band MIMO CMOS radio SoC for 802.11nwireless LAN.

• A 40Gb/s CMOS serial-link Receiver with adaptive equal-ization and CDR.

Educational Events: Tutorials The Conference will also include many educationalevents: Ten independent tutorials will be presented(Sunday, February 3rd) by experts from each of theISSCC 2008 Technical Program Subcommittees: Ana-log; Data Converters; High-Performance Digital;Imagers, MEMS, Medical and Displays; Low-PowerDigital; Memory; RF Technology Directions; Wireless;and Wireline:

• T1: Fundamentals of Class-D Amplifier Operation &Design

• T2: Pipelined A/D Converters: The Basics• T3: CMOS Temperature Sensors• T4: SoC Power-Reduction Techniques• T5: Digital Phase-Locked Loops• T6: Leakage-Reduction Techniques• T7: NAND Memories for SSD• T8: Silicon mm-Wave Circuits• T9: CMOS+ Bio: The Silicon that Moves and Feels

Small Living Things

• T10: Basics of High-Speed Chip-to-Chip and Back-plane Signaling

Short Course: “Embedded Power Manage-ment for IC Designers”This year’s short course (Thursday, February 7th) willexplain the fundamental power management issuesfaced by IC designers and explore state-of-the-art cir-cuit- and system-level techniques for power manage-ment. The four 90-minute presentations, intended forboth entry-level and experienced engineers will be:

SC1: Navigating the Path to a Successful IC SwitchingRegulator Design

SC2: Circuit Techniques for Switching RegulatorsSC3: Power Reduction and Management Techniques

for Digital CircuitsSC4: Power/Energy for Autonomous and Ultra-

Portable Devices

While new generations of consumer electronicproducts consume less power than their predeces-sors, the requirements for power delivery keepchanging in the direction of lower voltage and high-er current. At the same time, market pressures dictatethat every new generation of a product providesincreased functionality at reduced cost: and emergingapplications such as RF ID tags and sensor networksrequire elimination of conventional power sourcesaltogether.

These trends have caused power management tobe a critical issue in modern IC design. The switchingregulators predominantly used for DC power conver-sion in battery-operated devices introduce switchingnoise as the current they supply is increased, where-as analog and mixed-signal circuits that use the powerbecome increasingly sensitive to such noise as theirsupply voltages are decreased. Increasingly, multiplevoltage domains, each with different load scenarios,must be supported. Moreover, cost minimization oftenrequires that as much of the power management cir-cuitry as possible to be implemented in a highlyscaled CMOS technology optimized for digital circuit-ry. Thus, techniques to convert and use power effi-ciently are essential for success.

Advanced-Circuit-Design Forums7 Advanced Circuit Design Forums will be heldduring the conference. They provide an informalall-day interaction in which circuit expertsexchange information on their currentresearch. The Forum topics this year are as follows

F1: Embedded Memory Design for Nanoscale VLSISystems

F2: Wide-Dynamic-Range ImagingF3: Architectures and Circuit Techniques for

Nanoscale RF CMOSF4: Power Systems from the Gigawatt to the

Microwatt – Generation, Distribution, Storageand Efficient Use of Energy

F5: Future of High-Speed Transceivers


CONFERENCES


F6: Transistor Variability in Nanometer-Scale Tech-nologies

F7: Digitally Assisted Analog and RF Circuits

The evening program provides seven Special EveningTopic Sessions (SETs), in which experts provide insightand background on a subject of current importance andtwo panel discussions in which experts debate a select-ed topic and field audience questions in a semiformalatmosphere. The SET sessions cover a diverse range oftopics this year including: Environmental impacts andopportunities of semiconductors; the challenges associ-ated with designing sensors used in life-critical applica-tions; and the highlights of IEDM 2007.

The two panels will debate the role of private equi-ty firms in the IC industry; the limits of multi-coreintegration for general-purpose processors andwhether it is better to integrate many simple cores orfewer complex cores.

The full program is as follows:

Special Topic SessionsSE1: Green Electronics: Environmental Impacts,

Power, E-WasteSE2: MEMS for Frequency Synthesis and Wireless

RF Communications (or Life without QuartzCrystal)

SE3: From Silicon to Aether and BackSE4: Unusual Data-Converter TechniquesSE5: Trusting Our Lives to SensorsSE6: Highlights of IEDM 2007SE7: Trends and Challenges in Optical Communi-

cations Front-End

Panels:E1: Private Equity: Fight them or Invite them E2: Can Multicore Integration Justify the Increased

Cost of Process Scaling?

More information about ISSCC 2008 may be foundat: www.isscc.org/isscc/.

Iwould like to invite you to attend the55th ISSCC, which will be held in SanFrancisco on February 3-7, 2008. The

conference theme is “System Integrationfor Life and Style” in recognition thatintegration of novel circuits and systemscan deliver functions that enrich the

users’ life style.There will be 237 papers distributed over 31 techni-

cal sessions covering advances in analog and digitalcircuits; data converters; imagers, medical and displays;MEMS; memories; RF building blocks; technologydirections, and wireless and wireline communications.

Beside the regular paper sessions, the ISSCC willoffer a wide variety of high-quality educational pro-grams, adding to the already significant value of theISSCC. This year, there are ten Tutorials, sevenAdvanced Circuit Design Forums, and one ShortCourse. This year's short course deals with the popu-lar topic of “Embedded Power Management for ICDesigners.”

There are also four plenary presentations. • “The 2nd Wave of Digital Consumer Revolution:

Challenges and Opportunities,” Hyung Kyu Lim (Samsung Advanced Institute of

Technology) • “Surface and Tangible Computing, and the ‘Small’

Matter of People and Design,” Bill Buxton (Microsoft Research)

• “Embedded Processing: At the Heart of Life and Style,”Mike Muller (ARM)

• “Can’t A Computer Be More Like A Brain? OrWhat To Do With All Those Transistors?,” Jeff Hawkins (Numenta)

In addition, Evening Sessions will include: Twopanels that will bring together experts and visionarieswho share their views. Moreover, seven special-topicsessions will provide an opportunity to learn about anemerging topic in a relaxed setting.

As you can see, the upcoming ISSCC continues itstradition of presenting the best in solid-state circuitsand providing an opportunity to learn about the latestdevelopments through its rich choice of educationalactivities. In addition, the ISSCC is a great avenue fornetworking, meeting old colleagues and making newfriends. I am sure you'll enjoy ISSCC and I hope to beable to welcome you in San Francisco.

Yoshiaki HagiharaISSCC 2008 Technical Program Chair

[email protected]

Invitation from the ISSCC 2008 Technical Program Chair



CONFERENCES

VLSI Technology, Systems, and ApplicationsDr. Reinhard Ploss Trends in Electronics and

Semiconductors for Automo-tive ApplicationsInfineon, Germany

Dr. Clark T. C Nguyen Integrated MicromechanicalRadio Front-EndsUC Berkeley, USA

Dr. Kinam Kim Future Memory TechnologyChallenges and OpportunitiesSamsung, Korea

VLSI Design, Automation, and Test Dr. Willy Sansen Efficient Analog Signal pro-

cessing in nm CMOS Tech-nologiesK.U Leuven, Belgium

Dr. Randal E. Bryant Reasoning about Data: Bits,Bit Vectors, or WordsCarnegie Mellon University,USA

Dr. Janusz Rajski Logic Diagnosis, YieldLearning and Quality ofTest Mentor Graphics,USA

VLSI-TSA and VLSI-DAT to Convene on 21-25 April inHsinchu, Taiwan15th International Symposium on VLSI Technology, Systems, and Applications & 4th VLSIDesign, Automation and Test

Clara Wu, Symposia Secretariat, [email protected]

Dr. ReinhardPloss

Dr. Clark T. CNguyen

Dr. Kinam Kim Dr. WillySansen

Dr. Randal E.Bryant

Dr. Janusz Rajski

The 2008 International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA) and the2008 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) will be held from April21 to 25, 2008 at the Ambassador Hotel in Hsinchu, Taiwan. Sponsored by the Industrial Technology

Research Institute (ITRI) and divided into separate annual symposia since 2005, VLSI TSA-DAT lasts for twoand a half days in the same week, with a one day overlap.

The aim of the joint conference is to bring together scientists and engineers actively engaged in research,development, and manufacturing on VLSI technology, systems, and applications and on VLSI design, automa-tion and test to discuss current progress in this field.

In 2008, each symposium will feature three keynote speakers:

VLSI-TSA will also include fifty juried papers; three tutorials; two special sessions on Post-CMOS and High Volt-age Device & Process; a short course on “DRAM and new Channel Material vs. New Devices Structure,” andinvited talks on FEOL, NVM, BEOL, CMOS integration, Characterization & Modeling, 3D & packaging, CMOSdevices and DRAM.

Please register at vlsitsa.itri.org.tw or http://vlsidat.itri.org.tw. Should you have questions, please contact con-ference registrar, Ms. Yvonne Chen at +886-3-5913003 or email to [email protected] for assistance.


CONFERENCES


How long will GaAs and SiGecontinue as the mainstreamtechnology for hi frequency

applications? The Compound Semi-Conductor IC Symposium (CSICS)experts are one group very interest-ed to hear the prognosis for futureapplications and the feasibility of 60GHz WLAN/WPAN in CMOS. Andthe questions at the panel discus-sion during the November 29th Pro-gram in Portland Oregon, showedtheir attention.

Millimeter wave IC products arenot around the corner but here.Gabriel Rebeiz from UCSD remind-ed the audience that an automo-tive radar chip described by IanGresham at the Microwave Sympo-sium in June 2006 is now in pro-duction. General Motors is count-ing on M/A-COM shipments of 1Munits per year (rate of 100K unitsper month) to occur at the end of2008. The primary problems stillon their way to a better solutionare a commodity package andappropriate low-cost high-volumetesting. Currently QFN packagesdesigned for 5GHZ operation arebeing used simply because theyare available in quantity althoughthey are much too big and intro-duce too much inductance. Sopackaging and testing are twobusiness challenges for this BiC-MOS application.

Although these mm wave prod-ucts are Si-Ge and operate at 24GHZ, the future of 60 GHz CMOSproduction is closer. Joy Laskarreported that Georgia Tech hasdemonstrated a 60 GHz transceiverand beam-former that is not a

MIMIC combining some portion ofIII-V on a separate substrate, but atrue IC. It is a scaled phased arrayon a single chip that includes anLNA, mixer chain. It is RF-in andbit-out and hot pluggable intoexisting back-ends.

Key to driving advances will bethe communication standards thatare almost agreed upon.Nishikawa of NTT listed ECMAtechnical committees still in discus-sion and 802.15.3c which is in vot-ing now. Mahbod Eyvazkhani ofNokia got the audience to laugh bytalking about consumer interest totransfer movies to their cellphones. But all the panelists admit-ted that high definition video andhigh bit rate data transfer will pro-vide the high volume demand thatwill make investing in this technol-ogy worthwhile.

However Nishikawa of NTTshowed a chart indicating that unitcosts will drop below $10 a chiponly when the volume is greaterthat a million chips a month. Hedoubted that new LAN standardsalone would be enough to makethis product type a going businessline. Jonghae Kim of IBM SRDCsimply said that a lot more data onproduction runs, process variationand yield will be needed beforesuch answers are known. Initialcosts for CMOS will cost consider-ably more than pHEMT solutions.

Ali Niknijad of UC-Berkeleyticked off other applications thatwould benefit from 60 GHZ CMOStechnology for data transfer, HDset-top boxes, high density DVDs.And HD displays. “Just moving

memory around will do it,” he saidabout applications driving thetechnology. After posting about 15specifications, Niknijad distilledthe transceiver to the sweet spot of10 dBm Pout and less that 10 dBfor a noise factor. This is achiev-able he assured the audience.Flash will be the first memory tohandle the 60 GHz transmission heasserted. And 802.11 applicationswill probably move UWB aside.

A challenge for the circuitdesigner of 60 GHz IC applica-tions, is solving issues about theantenna. Currently on-chip anten-na design can take up a lot of valu-able real estate when integrated ona CMOS chip with other logic.Some panelists advised to shrinkthe design and not use transmi-sion-line, making the design moreRFIC like, not MMIC like. Niknijadpointed audience attention to apatented bond wire antenna inuse, that works at 60 GHz.

Joy Laskar from Georgia Techwhere a lot of research has beendone on packaging, pointed outthat it is preferable to have a singleRF input and to use a differentarchitecture chain that C-Band.Switch beam will use less realestate than beam forming butthose switch designs are a topic foranother session.

Then panel closed with one lastaudience question that contrastedoptimal designs with the businessreality. Why not W band that hasless path loss and greater band-width than 60 Hz? Answer: Thereare no standards being written forW band.

Mm-wave CMOS Applications: A Report from aCSICS PanelAnne O’Neill SSCS Executive Director, [email protected]



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SSCS-Germany Cosponsors SAMOS 2007Conference Founder Stamatis Vassiliadis Memorialized

Holger Blume, Program Chairman IC-SAMOS 2007, Chairman IEEESSCS Germany Chapter, [email protected]

Prof. Stamatis Vassiliadis (IEEEFellow, ACM Fellow, Member ofthe Dutch Academy of Sciences,

and Professor at Delft University ofTechnology), who passed away on 7April, 2007 was memorialized at the2007 SAMOS VII conference. Thisyear’s Embedded Computer Systems:Architectures, Modeling and Simula-tion symposium took place on the

Greek island of Samos, from 16-19 July. Born in Manolates, Samos, Stamatis founded the

SAMOS conference and workshop series in 2000and was the head and the heart of these events untilhis death. The series will not be the same withouthim. In a short presentation about Stamatis’s life,SAMOS board member John Glossner recognizedhim as an outstanding computer scientist and agood friend to all of us due to his vivid and heartymanner.

In order to create a permanent commemorationof this inspiring scientist and to preserve his specialspirit, the SAMOS organizing committee establishedthe "Stamatis Vassiliadis Best Paper Awards." The IC-SAMOS Award and the SAMOS Workshop Awardwere given for the first time to:

This year’s program focused on SAMOS’ tradi-tional areas of interest: embedded systems andembedded architectures. Session topics includedprocessor architectures, design space exploration,multiprocessor architectures, VLSI architectures, sys-tems and applications and reconfigurable architec-tures. Special sessions were devoted to SoC archi-tectures for software defined radio and embeddedsensor systems and sensor networks.

Highlights were invited talks by Willie Anderson(VP Engineering for Qualcomm CDMATechnologies)on "Software Is The Answer but What Is The Ques-

tion?" and by John Glossner (CTO and EVP forSandbridge Technologies) on "The SandblasterSB3011 Processor." Both presentations inspired live-ly discussions among conference participants.

The two co-located SAMOS events -- the Interna-tional SAMOS Conference (IC-SAMOS), sponsored andco-organized by the Germany Chapter of the IEEESolid-State Circuits Society and the IEEE Circuits andSystems Society, and the SAMOS workshop -- attract-ed an increasing number of paper submissions com-pared to 2006 (207 from 30 countries, a 40% increase).Due to their high quality, the selection process wasvery competitive, entailing four reviews per paper.The overall acceptance rate was less than 30 % for theconference and less than 40 % for the workshop. Tra-ditionally, the symposium features presentations in themorning, while in-depth, formal discussions onresearch results and future directions take place in aninformal setting after lunch. The best papers of theconference are published in special issues of the Jour-nal of VLSI Signal processing and the Journal of Sys-tems Architecture. Proceedings of the SAMOS work-shop have been published in the Springer LNCS series.

SAMOS VIII will take place in 2008 from July 21 - 24.For more information visit: samos.et.tudelft.nl/samos_viii/

See you in Samos next year!

Prof. StamatisVassiliadis

SAMOS '2007 symposium board and program chairs (fromleft): John Glossner (Sandbridge Technologies, USA), JarmoTakala (Tampere University of Technology, Finland), MladenBerekovic (IMEC, Belgium), Holger Blume (RWTH AachenUniversity, Germany), Andy Pimentel (Univ. of Amsterdam,The Netherlands), and Georgij Gaydadijev (TU Delft, TheNetherlands); missing from this photograph: Shuvra Bhat-tacharyya (Univ. of Maryland, USA).


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SSCS DL Takayasu Sakurai of Tokyo Universityspoke on “Organic Integrated Circuit Designfor Ubiquitous Electronics” at Ewha Womans

University on 6 July, 2007. According to AssistantProfessor Sung Min Park, “Almost fifty percent ofthe faculty members of the EE Department ofEwha Womans University specialize in semicon-ductors, IC design, SoC design, and the like. SoProf. Sakurai's talk was very much related to ourinterests.”

Precis: The other extreme of the silicon VLSI'swhich stay as small as a centimeter square, a newdomain of electronics called large-area integratedcircuit as large as meters is waiting, which mayopen up a new continent of applications in the eraof ubiquitous electronics. One of the implementa-tions of large-area electronics is based on organictransistors. This talk provides perspectives onorganic circuit design taking E-skin, sheet-typescanner, Braille display and wireless transmission

sheet as examples.Prof. Behzad Razavi presented a lecture entitled

“60-GHz Transceivers in CMOS : Why and How ?”on 14 August at Korea University, which houses acenter for 60GHz wireless transceivers.

Precis: The 7-GHz unlicensed band around 60GHz offers the possibility of wireless communica-tion at data rates reaching several gigabits per sec-ond. Moreover, the short wavelength allows inte-gration of the antenna on-chip and opensprospects for beam forming and MIMO signaling.

With multiple antennas and transceivers operat-ing on one chip, and with the enormous analogand digital signal processing required for high-ratecommunications, the use of CMOS technologybecomes attractive and perhaps essential.

This talk presents the challenges in circuit andarchitecture design for 60-GHz CMOS transceiversand describes our recent work on receiver designfor this frequency band. Specifically, a heterodynereceiver is presented that achieves a noise figureof 6.9-8.3 dB with a power dissipation of 80 mWin 90-nm CMOS technology.

Sakurai and Razavi Visit SSCS-Seoul in July and August

Dr. Takayasu Sakurai (front row, fourth from left)addressed 35 students at Ewha Womans University inSeoul, Korea on 6 July, 2007. At his right is Prof. Sung MinPark; at his left are Prof. Shin-Il Lim (in back), Prof. Kwang-sup Yoon, and Prof. Nak-Myeong Kim and Prof. HyesookLim (in back). Professors Park, H. Lim and N. Kim are EwhaUniversity faculty.

Dr. Behzad Razavi addressed an audience of 80 at KoreaUniversity in Seoul on 14 August, 2007. From Left (firstrow): Prof. Jae-Sung Rieh, Prof. Chulwoo Kim, Prof. Yogen-dera Kumar, Prof. B. Razavi, and Prof. Andy Chung.

18th VLSI Design/CAD Symposium Cosponsored byIEEE Taipei and Tainan SectionsAnnual Meeting of IEEE SSCS and CAS in August

Chua-Chin Wang, Chapter Chair SSCS-Tainan, [email protected]

The 18th VLSI/CAD Symposium was held on 8-10August, 2007 in Hualien, Taiwan. Home tosemiconductor foundries such as TSMC and

UMC, Taiwan is renowned as an IC design powerhouse. The VLSI Design/CAD Symposium, whichplays an important role in stimulating local research,is aimed at providing an open forum for professors,industrial engineers and, most important of all, gradu-ate students to exchange cutting-edge RD knowledgeand ideas in the fields of SOC/ASIC design and EDAresearch

General Chair Prof. Chua-ChinWang of National Sun Yat-SenUniversity greeting attendees atthe 2007 (18th) VLSI Design/CADSymposium on 8 August, 2007.



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Prof. Chung-Yu Wu, President of National Chiao Tung Uni-versity, gave a keynote speech entitled “What HappensNext? When Engineering Falls in Love with Biology, Med-ical Science, and Life Science,” describing the cutting-edgechip design developed by his research team.

A second keynote speech, “Sustainable Development andHi-Tech Industries,” by Prof. Jyuo-Min Shyu, Dean of theCollege of EE and CS, National Tsing Hwa University, ignit-ed a discussion about the need for a long term develop-ment plan for Taiwan and the worldwide IC industry.

In a talk on “Design for Reliability and Robustness - Cop-ing with Increasing Variability and Reliability Concerns,”Prof. Kwang-Ting Tim Cheng of UC Santa Barbara pointedout the rising cost of DFT and DFM in the next decade.

Prof. Shey-Shi Lu of National Taiwan University describedthe latest SoC solutions for nodes used in a wireless sen-sor network – - the next biomedical and electronic inter-discipline research topic -- in “A SoC for Biomedical Wire-less Sensor Network.”

Other highpoints of the symposium were• a panel discussion on the national SOC project of

Taiwan entitled “NSoC : Naïve or Novel Soc?” host-ed by Prof. Chau-Chin Su;

• three “Live Demo” sessions, where SOC systems werephysically presented on chips or boards by speakers

from brand-name Korean IC design companiesincluding RDC, Sunplus, Faraday, and Andes, andmedalists of national IC/IP design contests. The entireballroom was packed during the all the sessions;

• fifteen oral sessions with 90 papers, and threeposter sessions with 88.

SSCS Chapter Chairs Shen-luan Liu (Tapei) and C. – C. Wang (Tainan) hosted the annu-al joint meeting of SSCS members. Prof. C. K. Wang, SSCS Region 10 Representative(seated in front at left) spoke about SSCS local and worldwide activities.

“Among the social activities organized for the conference, my favorite was the magic show (left) and the gourmet seafoodat the banquet. All the attendees were so impressed, they kept saying that the symposium should do this more often.”C.C. Wang

Details about the symposium program and organization team can be found in www.ee.nsysu.edu.tw/vlsi2007/.


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In light of the importance of digitally-assistedapproaches to analog design, SSCS-Taipei invitedProf. Boris Murmann of the Department of Electrical

Engineering, Stanford University to present a shortcourse on the topic of deep-submicron ADC. Entitled“Challenges and Solutions for A/D Converter Design inDeep Submicron CMOS” and funded by an extra chap-ter subsidy from the Society, it took place in Hsinchuand Taipei on 5-6 September, respectively, and attract-ed over one hundred attendees, in almost equal pro-portions from industry and academia.

Two weeks later, SSCS Distinguished Lecturer,Prof. Behzad Razavi of UCLA presented an invitedtalk on millimeter-wave circuit design at NationalTaiwan University (NTU), Taipei. Hosted by theDirector of the Graduate Institute of ElectronicsEngineering, Prof. Shey-Shi Lu, Dr. Razavi’s one-hourlecture, entitled “A Millimeter-Wave Circuit Tech-nique,” attracted an audience of approximately 200on 19 September.

Murmann Describes Design Methodology forDevices Not Obeying Square LawDeep submicron CMOS technologies have broughtmany benefits to digital designs, but have also intro-duced harsh challenges for analog designers: The sim-ple square-law model can no longer predict deepsubmicron transistor behaviors. Thus, a paradigm shifthas occurred to take advantage of the cheap andpowerful digital capability to compensate for non-ideal analog circuits in deep submicron processes.

Focusing on amplifier design with deep submicron

devices, Prof. Murmann introduced his course with asystematic circuit design approach for devices that donot obey square law. He described the designmethodology in detail and showed several case stud-ies. In the second part of his lecture, he dove intoADC design, introducing several figure-of-merit defi-nitions for evaluating ADC performance and dis-cussing the fundamental limits. Then he presenteddigitally-assisted ADC design, including illustrations ofseveral examples bringing a mix of theoretical andpractical design knowledge to the lecture.

Razavi Introduces Inductive Peaking Technique For millimeter-wave/RF circuits, deep submicronCMOS technologies have enabled higher operatingfrequency. However, some limitations still pose greatchallenges for circuit designers. In his presentation,Prof. Razavi introduced an inductive peaking tech-nique that allows operation near the self resonancefrequency of inductors. Using the proposed tech-nique, fundamental oscillators operating at 130 GHzand frequency dividers achieving a maximum fre-quency of 125 GHz have been demonstrated. Theprototypes have been fabricated in TSMC's 90-nmCMOS technology.

Prof. Razavi is an award-winning researcher, teacher,and author. He joined UCLA in 1996, where he has pur-sued research on high-speed analog circuits, RF andwireless design, phase-locking phenomena, and dataconverter design. He was recognized as one of the top10 authors in the 50-year history of ISSCC. Prof. Razavihas authored five textbooks on analog and RF designand edited two on phase-locked systems.

Murmann and Razavi Visit SSCS-Taipei SSCS Extra Chapter Subsidy Underwrites Short Course on A/D Converter Design

By IEEE SSCS Taipei Chapter

Prof. Boris Murmann presented a short course on ADC Con-verter Design to an audience of 75 at National Chaio-TungUniversity in Hsinchu, Taiwan on 5 September.

Thirty-five attended Prof. Murmann’s ADC Converter Designcourse on 6 September at National Taiwan University,Taipei.

Behzad Razavi addressed an audience of 200 on 19 Sep-tember at National Taiwan University (NTU) on “A Millime-ter-Wave Circuit Technique.”



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ASICON is one of the most important interna-tional conferences about Integrated Circuitsdesign held in China. Sponsored by IEEE, the

Institution of Engineering & Technology (IET) and theChinese Institute of Electronics (CIE) and held seventimes since 1994, the conference provides a forum forresearchers, students, and engineers working in thefields of SOC/VLSI circuits design, EDA/CAD tech-nologies and related areas to discuss and exchangestate-of- the- art information.

SSCS-Shanghai and Fudan University jointly organ-ized and prepared the program for the 7th Interna-tional ASIC Conference, which took place on 26-29October, 2007.

On its opening day, the conference offered seventutorials:• “Design of Integrated Radio Transceiver Front-ends in

Submicron and Deep Submicron CMOS Technologies,”Prof. John Long, TU Delft, The Netherlands;

• “A/D Converters for Wireless Communication inNanometer CMOS,” Prof. Yun Chiu, University ofIllinois at Urbana-Champaign, USA;

• “SOC Design Flow Case Tutorial: Design a VideoProcessing Pipeline,” Dr. Wei Ruan, Shengqi Yangand Tiehan Lu, Intel, USA;

• "Inductance Extraction and Compact Modeling ofInductively Coupled Interconnects in the Presenceof Process Variations,” Prof. Sheldon Tan, UC River-side and Prof. Jeffrey Fan, Florida International Uni-versity, USA;

• “Recent Advances and Trends in Semiconductors,”Dr. Linming Jin, Brocade Communications SystemsInc., USA;

• “ESD and Latch-up: Computer Aided Design (CAD)Tools And Methodologies For Today And FutureVLSI Designs,” Dr. Steven Voldman IBM, USA;

• "Software Defined Cognitive Radios," Prof. A.H., Tewfik, Prof. Ramesh Harjani , Prof.

Gerald E. Sobelman, University of Minnesota.

Four keynote speakers gave invited speeches on threesuccessive mornings:• Dr. Kevin Zhang (Intel), "Circuit Design in Nano-

Scale CMOS Era";• Dr. Steven Voldman (IBM) “ESD advanced technol-

ogy”;• Prof. Takeshi Ikenaga (Waseda University, Japan),

"Video Compression LSI: Past, Present, and FutureTrends";

• Dr. Steve Leibson (Technology Evangelist Tensilica,Inc., USA), “Challenges for Consumer Electronics inthe 21st Century.”Of 464 papers submitted from 22 countries, 403

came from universities (86%) and 63 from industriesand institutes (14%). 230 papers were accepted fororal presentation in four parallel sessions.

Attendees at a presentation and discussing poster papersat ASICON, 2007.

At the closing banquet, the four winners of the ASI-CON 2007 Excellent Student Paper awards wereannounced:• M. AbdEsalam Hassan (Osaka University of Japan),

“A SystemC Simulation Modeling Approach for\Allocating Task Precedence Graphs to Multi-processors”;

• Lang Mai (Fudan University), “A novel CML-basedsynchronization algorithm for IR-UWB communica-tion”;

• Xin Li (Tsinghua University of China), “Thermal-aware Incremental floorplanning for 3D ICs”

• Guohua Chen (Chinese Academy of Sciences),“Design of a Low Power Digital Core for PassiveUHF RFID Sensors.”

This year was the first time that ASICON was heldin Guilin, one of the most beautiful cities for touristsin China. Attendees enjoyed the mountains and riversas well as the opportunity to share research results atthe Conference. The 8th ASICON will be held inShanghai in October, 2009.

230 Papers Represent International Community atASICON 2007 in Guilin, China7th International ASIC Conference Organized by SSCS-Shanghai and Fudan University

Ting-Ao Tang, Chair, SSCS-Shanghai, [email protected]

Fudan University Professor Ting-Ao Tang, Chair of SSCS-Shanghai and General Chair of ASICON 2007, welcomingattendees to the Conference.


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Forty-eight people, includingtwo members from industryand three Georgia Tech pro-

fessors attended Ian Galton’s lectureon PLLs at SSCS-Atlanta on 7November, 2007. According tochapter member Oscar Palomino,“PLL technology is a very populartopic at Georgia Tech, which offersgraduate courses and features vari-ous research teams developingnovel designs on the subject.”

Abstract: This talk provides atutorial-level explanation of fraction-al-N PLLs for frequency synthesisfollowed by a description of recent-ly-developed techniques that can beused to enhance their performance.The tutorial portion of the talk

briefly reviews integer-N PLLs andthen explains the additional ideasand issues associated with theextension to fractional-N PLLs. Top-ics include a self-contained explana-tion of the relevant aspects of _¤__modulation, and non-ideal effectsof particular concern in fraction-al-N PLLs such as charge pumpnonlinearities and data-depend-ent divider delays. Then, acharge pump linearization tech-nique and an adaptive phasenoise cancellation technique arepresented, including implementa-tion details and experimentalresults associated with a 2.4 GHzISM-band fractional-N PLL CMOSintegrated circuit.

Ian Galton Speaks on “Performance EnhancementTechniques for Fractional-N PLLs” at SSCS-CASS/AtlantaProf. Gabriel A. Rincón-Mora, Chairman, Atlanta SSCS-CASS Chapter, Georgia Institute of Technology,[email protected]

Dr. Gabriel Rincón-Mora presents acertificate of appreciation to Dr. IanGalton on behalf of the Atlanta SSCS-CAS chapter, 7 November, 2007.

From left to right: Dr. Gabriel Rincón-Mora (Chair, SSCS-CAS), Dr. Ian Galton (Distinguished Lecturer), Luke Milner andHuseyin Dinc (Ph.D. EE candidates), Oscar Palomino (M.S.E.E candidate), and Patrick O’Farrell (Secretary, Atlanta SSCS-CAS Chapter & Design Engineer, National Semiconductor).


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As Ireland pushes a nationalresearch and technologytransfer agenda, the SSCS Ire-

land Chapter has been actively pro-moting interaction between acade-mia and the circuit design industryby organizing guest lectures, confer-ence previews, and workshops.

Highlights of the year for SSCSIreland include Distinguished Lec-tures by Marcel Pelgrom, whospoke about “Nanometer CMOS: AnAnalog Challenge” in Dublin inMarch; Ian Galton, who gavepresentations on “Performance

Enhancement Techniques for Frac-tional-N PLLs” and “Mismatch-Shap-ing DACs for Delta-Sigma Data Con-verters” in Cork in September; andRinaldo Castello, who spoke about“Reconfigurable RF front-ends forwireless transceivers” in Cork and atthe IEEJ Analog VLSI workshop inLimerick in November.

The presentations were attend-ed by graduate students and stafffrom leading universities andresearch institutes, as well asmixed-signal and RF designersfrom a range of companies, includ-

ing Analog Devices, ChipSensors,Cypress, Freescale, Silicon & Soft-ware Systems (S3), and Xilinx.

The Distinguished Lecturer pro-gramme is highly appreciated bySSCS members in Ireland, 30% ofwhom attended at least one of thelectures. A typical comment is thatof Cormac O’Sullivan, S3, whoremarked, “It’s great that we canhave such a high calibre of speak-er here in Cork” thanks to SSCS.

Further details about the SSCSIreland Chapter can be found at:sscs.ucc.ie.

Academia and Industry Interact in IrelandSSCS DLs Pelgrom, Galton, and Castello Speak at Chapter Events

Peter M. Kennedy, FIEEE MRIA Vice-President for Research Policy & SupportNorth Wing, Main Quad University College Cork, Ireland, [email protected]

SSCS Ireland Chapter Chair Prof. Peter Kennedy, UniversityCollege Cork (left), with Distinguished Lecturer Ian Galton,UCSD (center), and Roger Whatmore, Director, TyndallNational Institute.

Prof Katsutoshi Saeki of the Institute of Electrical Engi-neers of Japan (IEEJ) making a presentation to Prof. Rinal-do Castello of the University of Pavia, Italy as a token ofappreciation for his invited lecture at the IEEJ Analog VLSIDesign Workshop in Limerick on 9 November 2007.


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The Denver SSCS Chapter hosted a total of eightseminars in 2007, three of which were spon-sored by the SSCS Distinguished Lecturer

Series. Topics ranged from cutting-edge microproces-sors to techniques for designing high-speed seriallinks to forefront technologies such as next-genera-tion lithography.

The year started with Robin Porter from VentureOperations describing ingredients for establishing asuccessful start-up. By comparing two companiescompeting in the thin server appliance space (Cobaltand Whistle), she emphasized the importance of busi-ness model strategy and supply chain management incontributing to boom vs. bust.

Given the high concentration of local companiesinvolved in serial link design, it was no surprise thatour next talk by Troy Beukema from IBM Research(Yorktown, NY) was a big hit. Mr. Beukema provideda broad overview of the systems, circuits, and model-ing challenges that lie ahead to overcome successfullinks beyond 10Gb/s.

Three new SSCS Distinguished Lecturers visited ourchapter: Dennis Fischette, from Advanced MicroDevices (Sunnyvale, CA), delivered a practicaloverview of monolithic phase-locked loop design.Next, Prof. David Allstot from the University of Wash-ington did a phenomenal job explaining bandwidthextension fundamentals using inductors and trans-formers. Shunt and series peaking never looked easi-

er! Finally, Prof. Clark Nguyen from the University ofCalifornia rounded up the year with a fascinatingseminar on MEMS for RF front-ends.

Dr. Shawn Searles from Advanced Micro Devices(Austin, TX) gave an extended encore of his ISSCC2007 paper on AMD's Barcelona native quad-coreprocessor. In addition, Profs. Gu-Yeon Wei andDavid Brooks came from Harvard University toexplain how they are tackling device variabilityusing joint architecture and circuit techniques suchas local voltage regulation for dynamic voltage-fre-quency scaling for multiple cores and alternativememory structures.

Local adjunct professor Dr. Hugh Grinolds fromColorado State University (Fort Collins, CO) present-ed a nice overview of extreme ultraviolet (EUV)lithography as the next viable replacement for 193nmimmersion ArF. He introduced key optical principlesand discussed the present state of development fromboth equipment and process perspectives.

The 2008 elections for chapter officers were recent-ly held and we welcome two new members to theteam: Steve Martin from Avago Technologies andVisvesh Sathe from AMD.

Please visit ewh.ieee.org/r5/denver/sscs/ for moreinformation, including past presentation slides, aboutour chapter events. Starting in 2007, all seminars havebeen videotaped onto DVDs, thanks to Program ChairBruce Doyle doubling his duties as videographer!

Eight Technical Meetings in Fort Collins during 2007SSCS DLs Fischette, Allstot and Nguyen Speak

Alvin Loke, Denver Chapter Chair, [email protected]

After SSCS DL David Allstot explained bandwidth extension fundamentals in Fort Collins, from left: Bob Barnes (ViceChair & Treasurer), Ron Kennedy, Bruce Doyle (Program Chair), Mike Gilsdorf, Prof. David Allstot, Don McGrath (formerChair), Alvin Loke, and Tin Tin Wee (Secretary & Webmaster).



CHAPTERS

SSCS Far East Chapters Meet in Jeju, Korea on 13November, 2007

Coinciding with the 3rd annual A-SSCC, the 2nd SSCS Region 10 chapter meeting was chaired by Jan Van der Spiegel (SSCSChapters Committee Chair) and attended by AdCom President-Elect Willy Sansen, SSCS Region 10 Representative andChapter Committee member C.K. Wang and the officers of eight Chapters (Beijing, Kansai, Seoul, Shanghai, Singapore,Tainan, Taipei and Tokyo). The participants, who shared best practices with each other and the AdCom, were (from left):Prof. Hanjun Jiang (Beijing), Prof. Suki Kim (Seoul), Prog. Zhihua Wang (Beijing), Dr. Kabuo Hideyuki (Kansai), Prof. Sung-min Park (Seoul), Prof. Tohru Furuyama (Tokyo), Prof. Andy Chung (Seoul), Prof. Willy Sansen, Prof. Jan Van der Spiegel,Prof. Shen-luan Liu (Taipei ), Prof. Akira Matsuzawa (Tokyo), Prof. Chua-Chin Wang ( Tainan), Prof. C. K. Wang (Taipei),Prof. Ting-Ao Tang (Shanghai), Prof. Kwang Sub Yoon (Seoul) and Prof. Yong Ping Xu (Singapore).

Dear Editor,

With regard to Thomas Lee's "Tales of the Continuum:A Subsampled History of Analog Circuits" in the Fall2007 issue, I'd like to make a comment.

This article would have been improved had it includ-ed some reference to Karl D. Swartzel, Jr.'s op amp.Swartzel was the Bell Labs designer of the originalamplifier used in the M-9 analog computational system(US patent 2401779). A Google link search on this May

1, 1941 patent filing shows a string of 77 references,some indication that it was indeed an influential work.It is truly unfortunate that this key development so oftengets overlooked.

The author's Reference 9 includes a narrative of theearly Bell Labs projects, and places the earliest op ampdevelopments and Swartzel's work in some perspective.

Walt JungIEEE Member

Letters to the Editor

On p. 58 of the Fall ’07 issue, the middle name of Dr.R. Jacob Baker was misspelled as Jakob.

In the same issue, “A History of The ContinuouslyInnovative Analog Integrated Circuit,” section iv, para-graph 1, line 4 should have read “Max Hauser” not

“Mark Hauser” and “Bob Brodersen,” not “BobBroderson.”

In the same article, section iv, paragraph 2, line 8should have read “In 1987 they were able” not “In1985.” Stephen Lewis, UC-Davis, [email protected]

Corrections



Fiez, Kuroda, Nauta, Sevenhans and Soyuer Elected to AdCom

SSCS NEWS

Terri Fiez Tadahiro Kuroda Bram Nauta Jan Sevenhans Mehmet Soyuer

Terri Fiez, Tadahiro Kuroda, Bram Nauta, JanSevenhans and Mehmet Soyuer were elected toSSCS AdCom and will serve three year terms

governing the Society, beginning 1 January 2008.Coming from industry and academia, from Asia,Europe, and North America, these five join ten otherelected AdCom members whose terms overlap.

Terri S. Fiez received the B.S. and M.S. in ElectricalEngineering in 1984 and 1985, respectively, from theUniversity of Idaho, Moscow. In 1990, she receivedthe Ph.D. degree in Electrical and Computer Engi-neering from Oregon State University, Corvallis. From1985 to 1987 and in 1988 she worked at Hewlett-Packard Corp. in Boise and Corvallis, respectively.

In 1990, Dr. Fiez joined Washington State University asan assistant professor and became an associate professorin 1996. In the fall of 1999, she joined the Departmentof Electrical and Computer Engineering at Oregon StateUniversity as Professor and department head andbecame the Director of the School of Electrical Engi-neering and Computer Science in 2003. She has servedon the committees of the IEEE International Solid-StateCircuits Conference, IEEE Custom Integrated CircuitsConference, and ISCAS, and was a guest editor of theJournal of Solid-State Circuits. Dr. Fiez was awarded theNSF Young Investigator Award, the Solid-State CircuitsSociety Predoctoral Fellowship, and the 2006 IEEE Edu-cation Activities Board Innovative Education Award. Herresearch interests are the design of high performanceanalog signal processing building blocks, simulation andmodeling of substrate coupling effects in mixed-signalICs, and innovative engineering education approaches.This will be Dr. Fiez second term as an elected memberof the Solid-State Circuits Society (SSCS) AdministrativeCommittee (AdCom). She is an IEEE Fellow.

Tadahiro Kuroda received the Ph.D. degree in electri-cal engineering from the University of Tokyo in 1999. In1982, he joined Toshiba Corporation, where hedesigned CMOS SRAMs, gate arrays and standard cells.From 1988 to 1990 he was a Visiting Scholar at the Uni-versity of California, Berkeley, where he conductedresearch in the field of VLSI CAD. In 1990, he returnedto Toshiba for research and development of BiCMOS

ASICs, ECL gate arrays, high-speed and low-powerCMOS LSIs for multimedia and mobile applications. Hedeveloped a Variable Threshold-voltage CMOS (VTC-MOS) technology for controlling VTH through substratebias and a Variable Supply-voltage scheme for control-ling VDD by an embedded DC-DC converter, andemployed them in a microprocessor core and an MPEG-4 chip in 1997. In 2000, he moved to Keio University,Yokohama, Japan, where he has been a professor since2002. This year he is Visiting MacKay Professor at theUniversity of California, Berkeley. His research interestsinclude ubiquitous electronics, sensor networks, wire-less and wireline communications and ultra-low-powerCMOS circuits. He has published more than 200 techni-cal publications including 50 invited papers, 18books/chapters, and filed more than 100 patents.

Dr. Kuroda served as the General Chairman for theSymposium on VLSI Circuits and as Vice Chairman forASP-DAC. He has chaired sub-committees for A-SSCC,ICCAD and SSDM, and served on conference programcommittees for the Symposium on VLSI Circuits, CICC,DAC, ASP-DAC, ISLPED, and others. He is an IEEEFellow and an IEEE SSCS Distinguished Lecturer.

Bram Nauta was born in Hengelo, The Netherlands in1964. In 1987 he received the M. Sc. degree cum laudein electrical engineering from the University of Twente,Enschede, The Netherlands. In 1991 he received thePh.D. degree from the same university on the subjectof analog CMOS filters for very high frequencies.

In 1991 he joined the Mixed-Signal Circuits and SystemsDepartment of Philips Research, Eindhoven the Nether-lands, where he worked on high speed AD convertersand analog key modules. In 1998 he returned to the Uni-versity of Twente as full professor heading the IC Designgroup, which is part of the CTIT Research Institute. Hiscurrent research interest is high-speed analog CMOS cir-cuits. He is also a part-time consultant in industry.

Dr. Nauta served as Associate Editor of IEEE Trans-actions on Circuits and Systems -II; Analog and Digi-tal Signal Processing (1997-1999), as Guest Editor(1998) and Associate Editor (2001-2006) for the IEEEJournal of Solid-State Circuits. He is member of thetechnical program committees of ISSCC, ESSCIRC, andSymposium on VLSI circuits. He is co-recipient of theISSCC 2002 "Van Vessem Outstanding Paper Award".



SSCS NEWS

Nauta is the Editor in Chief of the IEEE Journal ofSolid-State Circuits and recently elevated IEEE Fellow.

Jan Sevenhans, who is an IEEE Fellow recognized for"contributions to solid-state telecom transceiver integra-tion," joined the Communication High Voltage businessunit of AMI Semiconductor in Belgium in 2005 and pre-viously was a distinguished Member of the TechnicalAcademy of Alcatel Bell in Antwerp, Belgium. Heserved as Program chair of ISSCC 2006 and has beenEuropean Chair of the International Solid-State CircuitConference (ISSCC). In 2002 he chaired the workshop"Analog telecom access circuits and concepts" at ISSCC.

Born in 1955, Dr. Sevenhans received a Mastersdegree in 1979 and a Ph.D. in 1984 from the KU Leuvenin Belgium; his doctoral dissertation focused on CCDimagers for facsimile applications. He joined Alcatel Bellin 1987, working on analog and RF circuit design fortelecom applications in GSM, ADSL, ISDN, and POTs,and on CMOS and bipolar silicon technology. He hasfiled many patents and published numerous articles inIEEE conference proceedings and journals. Since thelate eighties he has been involved in many Europeanresearch projects such as GSM in Jessi, Medea, Medea+,RACE, IST, and ESPRIT and Girafe - Gigahertz Radiofront Ends, in addition to Medea A203, SODERA, andSPACE. Over the past ten years, he has served as review-er and/or evaluator of several European projects, and asRegion 8 representative for the SSCS AdCom.

Mehmet Soyuer received the B.S. and M.S. degreesin electrical engineering from the Middle East Techni-cal University, Ankara, Turkey in 1976 and 1978. Hereceived the Ph.D. degree in electrical engineeringfrom the University of California at Berkeley in 1988,subsequently joining IBM at the Thomas J. WatsonResearch Center, Yorktown Heights, NY as a ResearchStaff Member. His work has involved high-frequencymixed-signal integrated circuit designs, in particularmonolithic phase-locked-loop designs for clock anddata recovery, clock multiplication, and frequencysynthesis using silicon and SiGe technologies.

At IBM Thomas J. Watson Research Center, Dr.Soyuer managed the Mixed-Signal CommunicationsIntegrated-Circuit Design group from 1997 to 2000.He was the Senior Manager of the CommunicationCircuits and Systems Department from 2000 to 2006.In 2006, he was promoted to the position of Depart-ment Group Manager, Communication Technologies,at Thomas J. Watson Research Center.

Dr. Soyuer has authored numerous papers in theareas of analog, mixed-signal, RF, microwave, and non-linear electronic circuit design, and he is an inventor andco-inventor of eight U.S. patents. Since 1997, he hasbeen a technical program committee member of theInternational Solid-State Circuits Conference (ISSCC). Hewas an Associate Editor of the IEEE Journal of Solid-StateCircuits from 1998 through 2000, and was one of theGuest Editors for the December 2003 Special ISSCCIssue. Dr. Soyuer chaired the Analog, MEMS and Mixed-Signal Electronics Committee of the International Sym-posium on Low Power Electronics and Design (ISLPED)

in 2001. He was also a technical program committeemember of the Topical Meeting on Silicon MonolithicIntegrated Circuits in RF Systems (SiRF) in 2004 and2006. This will be Dr. Soyuer’s second term as an elect-ed member of the Solid-State Circuits Society (SSCS)Administrative Committee (AdCom). Dr. Soyuer is a sen-ior member of IEEE and a Distinguished Lecturer ofIEEE-SSCS.

Look for the responsibilities of AdCom members in theaccompanying announcement for next years election,“Call for Nominations for AdCom.” Thanks to theseglobal technical experts for being willing to serve!

Call for Nominees for SSCS AdministrativeCommittee Election

Each year SSCS elects five members to govern the Society on thebody called the Administrative Committee (AdCom). TheseAdCom members serve three year terms. The Bylaws of theSociety guarantee a choice for members in the election by requir-ing that the nominating committee prepare a slate of a minimumof 8 candidates for the 5 positions. The nominating committeebegins its work in the beginning of the year in order to announceits candidates in the summer News issue. Members interested torun or to nominate others should send their recommendations tothe Chair of the Nominating committee, Richard C. Jaeger,[email protected]. The election is in the fall and studentmembers are not eligible to run or vote. The five nomineesreceiving the highest number of votes of the Society membershipwill be elected. There is also a petition process for interested par-ties who are not endorsed by the Nominating Committee.

ScopeElected AdCom members are expected to attend the twoadministrative meetings each year. Some Committee work iscarried on by email throughout the year. The AdCom overseesthe operations of chapters, publications and conferencesincluding the Journal of Solid-State Circuits, the InternationalSolid-State Circuits Conference, the Custom Integrated CircuitsConference, the VLSI Circuits Symposium, and the Asia Solid-State Circuits Conference. In addition, the Society cosponsorsor technically cosponsors a number of other conferencesincluding the European Solid-State Circuits Conference.

The AdCom has responsibility for overseeing these and forother potential future technical activities within the Society'sfield of interest.

Terms of Office• The term of office is three years beginning 1 January 2009. • AdCom members may be reelected to a second consecutive

term. • Members who miss two consecutive AdCom meetings shall

be dropped from membership in the absence of extenuatingcircumstances.

Nominees by PetitionThose interested to use the petition process must begin nolater than July 15, immediately after the Nominating Commit-tee’s slate has been announced in the summer issue. Contactthe SSCS Executive Director, [email protected]. Once eligibilityof the petition candidate is verified, any society voting mem-ber who wishes to sign such petition may do so electronicallythrough ton-line software under the administration of the IEEECorporate Office. The number of signatures required for a peti-tion candidate is 2% of SSCS voting members at the time thepetition process begins. This is expected to be approximately140 signatures. Once a member is posted on the site, he or shewill remain up to receive endorsement signatures, until a pre-determined date in late August or early September when theelection begins.



SSCS NEWS



SSCS NEWS

CEDA Celebrates Second Anniversary

President’s MessageThe IEEE Council on Electronic Design Automation(CEDA) has made great progress in the two yearssince its creation. In June 2005, CEDA was formed tocreate a focal point and pull together EDA activities inthe IEEE. The CEDA Board of Governors, officers, andvolunteers have done a lot to create the CEDA thatyou now recognize. Since its formation, CEDA hasincreased sponsorship of conferences, added publica-tions, and started technical activities. If you are inter-ested in volunteering a few hours a month, please e-mail me ([email protected]) or any of the coun-cil officers, and we can plan a useful, rewarding activ-ity for you.

At its inception, CEDA took the leadership incosponsoring the Design Automation Conference(DAC), the IEEE/ACM International Conference onComputer-Aided Design (ICCAD), and the Design,Automation and Test in Europe Conference (DATE).These are significant conferences in the EDA space.We have since grown to sponsor 12 conferences andworkshops focusing on specific topics or regions, andthe roster is increasing. A list of the specific meetingsthat CEDA sponsors is available at CEDA’s Web site,www.ieee-ceda.org.

In publications, the council copublishes IEEETransactions on Computer-Aided Design of IntegratedCircuits and Systems (T-CAD) with the IEEE Circuitsand Systems Society. We started the CEDA CurrentsNewsletter in 2006 to cover news and noteworthyevents. Recently, CEDA launched the electronic ver-sion of IEEE Design & Test, working in cooperationwith the IEEE Computer Society and the Test Tech-nology Technical Council (TTTC).

CEDA established an awards committee in 2005,which became part of the IEEE Fellow selectionprocess in 2006. This year, CEDA became a cospon-sor of the Phil Kauffman award with the EDA Con-sortium.

The CEDA Technical Activities Committee supportsseveral activities, including student competitions inphysical design, logic synthesis, and circuit design;and a Distinguished Speaker Series featuring the bestpapers from DAC, ICCAD, T-CAD, and other forums.(Videos of the Distinguished Speaker Series are avail-able on our Web site.) CEDA also cosponsors theComputer-Aided Network Design (CANDE) TechnicalCommittee (www.cande.net) and the Design Automa-tion Technical Committee (http://tab.computer.org/datc) with the IEEE Circuits and Systems Societyand the IEEE Computer Society, respectively.

This is only the beginning. There are many otheractivities on the horizon and many more possibilities.At the core, they are driven by the interests and zealof our volunteers. For instance, we are in the processof creating an infrastructure for research and haveseeded a small effort in this area. We are looking forvolunteers for this project, and of course, any other

project you may have preference for. So, look us upon the Web or in person, and drop us a note if youare interested in learning further.

Al Dunlop, CEDA President

TTTC Joins CEDA’s Launch of IEEE D&T ElectronicEditionWorking in cooperation with the IEEE ComputerSociety Press, CEDA recently launched the IEEE D&TElectronic Edition. We are happy to report that theTest Technology Technical Council (TTTC) has joinedthis effort.

The D&T Electronic Edition is an exact, cover-to-cover copy of the printed magazine including all illus-trations, graphics, conference calls and other advertis-ing. This compact, easy-to-navigate format will bedelivered every two months for an annual subscrip-tion cost of $19.95 (half the best member price forsubscription to the regular D&T print issue). Toreceive this excellent rate, you will not need to be amember of the IEEE or any society. Simply sign up forthe electronic edition through CEDA.

Here is what our friends are saying about IEEED&T Electronic Edition:

D&T and TTTC have enjoyed a long and close rela-tionship at multiple levels, from editors and authors tospecial sections, embedded newsletters, and electronicbroadcasts; to membership and readership of D&T. Ina changing publishing environment, easy access topublishing and distribution channels enables us toprovide worthwhile exclusive benefits to a broadercommunity. The importance of peer-reviewed, careful-ly produced, and high-quality technical content iseven more acutely felt by the busy professional. We areproud to see D&T take the lead in providing low-costaccess to such content.

—Yervant Zorian, D&T EIC Emeritus and TTTCSenior Past Chair

The D&T Electronic Edition joins a growing list ofattractive membership benefits for test technology profes-sionals. As the lead representative of an expanding world-wide test community, TTTC is pleased to actively supportand participate in this initiative, as this will provide clearbenefits for existing and future members of TTTC.

—Andre Ivanov, TTTC Chair

D&T Electronic Edition is a bold new experiment inproviding low-cost access to high-quality peerreviewedtechnical material for the EDA professional. With thislaunch, D&T joins IEEE Transactions on Computer-Aided Design as a complementary publication target-ed toward the busy professional. We hope you like thenew magazine and join us in the expanding EDAcommunity at CEDA.

—Al Dunlop, CEDA President


SSCS NEWS


For more information and to sign on, please visitCEDA’s Web site at www.ieee-ceda.org.

New Codesign Contest at MEMCODEForrest Brewer, University of California, Santa Bar-bara and James C. Hoe, Carnegie Mellon University

New to the 5th ACM/IEEE International Council onFormal Methods and Models for Codesign --MEM-OCODE, held 30 May through 1 June 2007 in Nice,France and cosponsored by CEDA -- is the hardware-software codesign contest. Its goal is to identify issuesspecific to codesign practice and to foster greaterinterest in the design aspects of MEMOCODE. Thecontest also serves to showcase advances in codesigntools and methodologies.

To make the contest feasible, we decided to keepthe term relatively short and to provide a workingcode base for at least one inexpensive, easily avail-able platform. We ultimately opted for a problem thatcould be done well in a week, and we allowed thecontestants a month’s lead time to solve it.

We did not wish to limit the competition to a particularexecution platform because we thought that many designgroups would be more familiar with their preferred plat-forms. Instead, we left the choice of platform to the con-testants and provided a grading metric that attempts toequalize the differences. We did, however, select the Xil-inx XUP2VP prototyping board as the reference platform.The XUP2VP board provides a large variety of interfaces,is well supported, and is inexpensive. The onboard Virtex-II Pro XC2VP30 FPGA has a substantial programmable-logic fabric, a fair amount of on-chip memory, and twoPowerPC 405 embedded processors. For the XUP2VPenvironment, we provided reference starter design materi-als, including a software-only reference solution and a ref-erence hardware-software interface library comprisingready-to-use C functions and Verilog modules.

The design problem chosen for 2007 was the BlockedMatrix-Matrix Multiplication. The basic algorithm, thoughfundamentally simple to understand, lends itself to alarge space of high-leverage optimizations in managingdata movement, storage, and bandwidth. We designedthe problem to require hardware involvement in thedesign as well as a software component. We focused onperformance as the primary metric of merit. The metricused is the speedup achieved by the contestants’ design,relative to the official software-only reference design ontheir platform of choice. We further asked the contestantsto describe the design in sufficient detail so that a panelof judges could make decisions about the elegance of theapproach as well as the efficacy of a particular design.We felt that it was important for the judging panel to beable to reward a unique or novel solution, even if itsoverall performance was less competitive.

Two teams, from MIT and Virginia Tech respec-tively, successfully submitted final designs, whichwere presented and discussed at the MEMOCODEconference on 31 May 2007. The audience selectedthe MIT team as the winner, and the Virginia Techteam as a co-winner of the cash award to each team.

Although the contest did not have the number ofentrants we had hoped for, the two final entries were

of very high quality and offered real technical contri-butions to share with the conference audience. Webelieve the codesign contest adds an important newdimension to MEMOCODE and should remain a valu-able component in the future. The call for participa-tion for next year’s contest is available at mem-ocode07.ece.cmu.edu/contest.html.

Recipients of National Medal of TechnologyAnnounced in JuneOn 12 June 2007, President George W. Bushannounced the recipients of the nation’s highest

honor for technology, the 2005 National Medal ofTechnology. This prestigious award honors leadinginnovators in the US. The award is given to individu-als, teams, and companies or divisions for their out-standing contributions to the nation’s economic, envi-ronmental, and social well-being through the devel-opment and commercialization of technology prod-ucts, processes, and concepts; technological innova-tion; and development of the nation’s technologicalmanpower. The 2005 award recipients included

• Semiconductor Research Corporation; • Alfred Y. Cho of Lucent Technologies, Murray

Hills, N.J.;• Dean L. Sicking, University of Nebraska-Lincoln; • a team from Wyeth Pharmaceuticals, Madison,

N.J.; • Genzyme Corp., Cambridge, Mass.; • Xerox, Stamford, Conn.The US Department of Commerce administers the

award, which was established by an act of Congress in1980. For more information about the National Medal ofTechnology, visit www.technology.gov/medal.

The Most-Downloaded Articles in 2006The most-downloaded articles in 2006 from IEEEDesign & Test and IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems were:• ‘‘Embedded Systems and the Kitchen Sink’’

Jan.–Feb. 2006 452• ‘‘Dynamic Power Management in Wireless Sensor

Networks’’ Mar.–Apr. 2005 423• ‘‘Physical Design for 3D System on Package’’

Nov.–Dec. 2005 381• ‘‘Design, Synthesis, and Test of Networks on Chips’’

Sep.–Oct. 2005 340

CANDE Holds Successful Workshop on Queen MaryThe Computer-Aided Network Design (CANDE) Tech-nical Committee—a venerable group of EDA stal-warts, thought leaders, and decision-makers— held itsannual workshop on 6-8 September 2007 aboard theQueen Mary in Long Beach, California.

The program included sessions on multicore andmany-core chips, statistical design, and nano- andbiodesign, with keynote talks by Bill Joyner of Semi-conductor Research Corp. (SRC) on ‘‘CAD and theQueen Mary: Tied Up at the Dock?’’ and by DrewEndy of MIT on ‘‘Technologies for Engineering Biolo-gy.’’ More information on CANDE is available atwww.cande.net.



SSCS NEWS

MEMOCODE and DAC Colocated in 2008The 6th IEEE/ACM Conference on Formal Methods andModels for Codesign (MEMOCODE) will be collocatedwith the 45th Design Automation on 5-7 June 2008 inAnaheim, California. Every year, MEMOCODE featuresa design contest to demonstrate the value of system-level design tools and methods in real-life designs, in acompetitive environment. For more information, go towww.memocode-conference.com.

Upcoming GRC and FCRP Funding OpportunitiesThe Global Research Collaboration (GRC), an arm ofSRC, conducts mission-driven research on behalf of itsmembers’ companies, responding to broad industryneeds in semiconductors. The first step in this processinvolves submitting calls for white papers in responseto identified industry needs in various areas, groupedunder the following thrusts: computer-aided designand test (CADTS), device sciences, integrated circuitsand systems, interconnects and packaging, nanomanu-facturing, and cross-disciplinary thrusts. For more infor-mation and to see any current calls for white papers,go to //grc.src.org.

The Focus Center Research Program (FCRP) ismanaged by the directors of five FCRP research cen-

ters in charge of research addressing long-termindustry needs. For more information, seewww.src.org/member/about/funding.asp.

Upcoming CEDA EventsDesign, Automation and Test in Europe Conference (DATE)10-14 March 2008Munich, Germanyhttp://www.date-conference.com

2nd ACM/IEEE International Symposium on Net-works-on-Chip (NoCS)7-11 April 2008Newcastle University, UKhttp://www.nocsymposium.orgFor more information regarding sponsorship of con-ferences and meetings, contact Richard Smith,[email protected].

CEDA Currents is a publication of the IEEE Councilon Electronic Design Automation. Please send contri-butions to Kartikeya Mayaram ([email protected]) Preeti Ranjan Panda ([email protected])or Anand Raghunathan ([email protected]).

At the 5th ACM/IEEE International Council on Formal Methods and Models for Codesign (MEMOCODE) in May, a teamfrom MIT won the first hardware-software codesign contest.


SSCS NEWS


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Europe/Africa/Middle EastHeleen VodegelPhone: +44-1875-825-700Fax: [email protected], Africa, Middle East

Asia/Far East/Pacific RimSusan SchneidermanPhone: 732-562-3946Fax: [email protected], Far East, Pacific Rim, Australia, NewZealand

RECRUITMENT ADVERTISINGMidatlanticLisa RinaldoPhone: 732-772-0160Fax: [email protected], NJ, CT, PA, DE, MD, DC, KY, WV

New England/Eastern CanadaJohn RestchackPhone: 212-419-7578Fax: [email protected], VT, NH, MA, RICanada: Quebec, Nova Scotia, Prince EdwardIsland, Newfoundland, New Brunswick

SoutheastThomas FlynnPhone: 770-645-2944Fax: [email protected], NC, SC, GA, FL, AL, MS, TN

Midwest/Texas/Central CanadaDarcy GiovingoPhone: 847-498-4520Fax: [email protected]; AR, IL, IN, IA, KS, LA, MI, MN, MO, NE, ND,SD, OH, OK, TX, WI. Canada: Ontario, Manitoba,Saskatchewan, Alberta

West Coast/Southwest/Mountain StatesTim MattesonPhone: 310-836-4064Fax: [email protected], CO, HI, NV, NM, UT, CA, AK, ID, MT,WY, OR, WA. Canada: British Columbia

Europe/Africa/Middle EastHeleen VodegelPhone: +44-1875-825-700Fax: [email protected], Africa, Middle East

Solid-State CircuitsSociety Newsletter

Advertising Sales Offices445 Hoes Lane, Piscataway NJ 08854

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SSCS SPONSORED MEETINGS2008 ISSCC International Solid-StateCircuits Conferencewww.isscc.org3– 7 February 2008 San Francisco, CA, USAContact: Courtesy Associates,[email protected]

2008 Symposium on VLSI Circuitswww.vlsisymposium.org19–22 June 2008Honolulu, HawaiiPaper deadline: Passed.Contact: Phyllis Mahoney,[email protected]

2008 Custom Integrated CircuitsConferencehttp://www.ieee-cicc.org/21–24 September 2008San Jose, CA, USAContact: Ms. Melissa Widerkehr, ConferenceManager19803 Laurel Valley PlaceMontgomery Village, MD 20886Phone: 301-527-0900 x 101Fax: [email protected]

SSCS PROVIDES TECHNICAL CO-SPONSORSHIP 2008 International Symposium on VLSITechnology, Systems and Applications (VLSI-TSA) vlsidat.itri.org.tw21 - 23 Apr 2008Hsinchu, Taiwan Contact: Ms. Stacey C.P. [email protected]

2008 Design Automation Conferencewww.dac.com

9–13 June 2008Anaheim, CA, USAPaper deadline: Passed.Contact: Kevin Lepine, Conference [email protected]

2008 Radio Frequency Integrated CircuitsSymposium www.rfic2008.org15–19 June 2008Atlanta, GAPaper deadline: Passed.Contact: Mr. Stephen [email protected]

2008 IEEE Symposium on VLSI Technologywww.vlsisymposium.org19–22 June 2008Honolulu, HawaiiPaper deadline: Passed.Contact: Phyllis Mahoney, [email protected] Business Center for Academic Societies, Japan,[email protected]

Hot Chipswww.hotchips.org3-8 Aug 2008 Palo Alto, CA, USAPaper deadline: 24 March 2008Contact: John Sell, [email protected]

ISLPED International Symposium on LowPower Electronics and Designwww.islped.org/ Aug 2008Contact: Diana [email protected]

ESSCIRC/ESSDERC 2008 - 38th European SolidState Circuits/Device Research Conferenceswww.esscirc2007.org 15 Sep - 19 Sep 2008

Edinburgh, ScotlandPaper deadline: 5 April 2008Contact:Bill Redman-White, ESSCIRC [email protected]

2008 IEEE Integrated Circuit Ultra-Wide BandICUWBwww.icuwb2007.org10-12 Sep 2008Hannover, GermanyPaper deadline: 10 February 2008Contact: Michael Y.W. [email protected]

2008 IEEE Bipolar/BiCMOS Circuits andTechnology Meeting - BCTM www.ieee-bctm.orgA14-16 Oct 2008Monerey, CAPaper deadline: 17 March 2008Contact: Ms. Janice [email protected]

2008 IEEE Compound SemiconductorIntegrated Circuit Symposium (CSICS)www.csics.org12 Oct - 15 Oct 2008Monterey CA Paper due date: 12 May 2008Contact: William Peatman [email protected]

2008 International Conference on ComputerAided Design (ICCAD)9-13 November 2008Place: TBDContact: Kathy MacLennan, Conference ManagerMP Associates, Inc.5405 Spine Rd., Ste. 102Boulder, CO 80301Tel: (303) [email protected]

SSCS EVENTS CALENDARAlso posted on www.sscs.org/meetings

SSCS IEEE SOLID-STATE CIRCUITS SOCIETY NEWS is published quarterly by the Solid-State CircuitsSociety of The Institute of Electrical and Electronics Engineers, Inc. Headquarters: 3 Park Avenue, 17thFloor, New York, NY 10016-5997. $1 per member per year (included in society fee) for each member ofthe Solid-State Circuits Society. This newsletter is printed in the U.S.A. Application to mail Periodicalspostage rates is pending at New York, NY and at additional mailing offices.Postmaster: Send address changes to SSCS IEEE Solid-State Circuits Society News, IEEE, 445 Hoes Lane,Piscataway, NJ 08854. ©2008 IEEE. Permission to copy without fee all or part of any material without acopyright notice is granted provided that the copies are not made or distributed for direct commercialadvantage and the title of publication and its date appear on each copy. To copy material with a copy-right notice requires specific permission. Please direct all inquiries or requests to IEEE Copyrights Man-ager, IEEE Service Center, 445 Hoes Lane, Piscataway, NJ 08854. Tel: +1 732 562 3966.

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