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What You See Is What You Get
1 ©All rights reserved thevtool.com
Asi Lifshitz, CTO 4 February Verification Future Conference, UK
Design and Verification Technology Evolution
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Verilog / VHDL Testbenches
Specman e Language – High level language with HW ‘awareness’
SystemVerilog as a 2nd language
eRM, OVM, VMM Methodology above the language
Verification IPs for standard protocols
UVM – All methodologies converge into one
Till late 90’s 2000 2005 2005-2011 2006-Today 2011-Today
• Formal Verification
• Did evolve significantly in the last 5 years
• Adoption is quite high
• Cannot replace functional verification
• HW/SW co-verification
• Becomes a real problem for product TTM issues
• More usable due to accelerators
• Still – On top of functional verification and not as a replacement
Other Verification Techniques
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Verification Today
• 22% verification development, 37% debug • Majority verification methodologies UVM
Source: Wilson Research & Mentor Graphics, 2014
Improvements significantly accelerate overall schedule
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Modern Verification Environments : SystemVerilog UVM
• UVM developed by Accellera committee using OVM and VMM as a basis
• Object Oriented based methodology designed to simplify reuse and team work
• Generally accepted as the defacto verification methodology by many teams
Testbench Code/VIPs
UVM Class Structure
Ver
ific
atio
n L
ayer
s
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SystemVerilog Language
Simulation Tool
“UVM = Ugly Vicious Monster”
Stu Sutherland, noted SystemVerilog & UVM Trainer, 2015
“Design IP gets rewritten all the time, but try getting anyone to rewrite verification IP”
Cliff Cummings, noted SystemVerilog Consultant, DeepChip 2015
• UVM is useful but extremely complex, verbose
‐ Leads to wasted time and bugs
• HW engineers must learn OO, etc.
‐ Learning curve 6 months minimum, limits reuse
• Few experts write UVCs & TBs, proliferate to team
‐ Everyone accepts it, most engineers hate it
The Reality of UVM
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Functional Verification Flow Challanges
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What slows down the Process: • Specs are incomplete or DUT is not available – Process is incremental • Need to reuse, but can’t even assess the old code reusability • Verification code is 3 times larger than design code - Most of the time spent on
debugging it • UVM is complex – Only experts are efficient • Hard for designers to assist at peak times – not familiar with language and methodology • Hard to ramp-up on someone else’s code • Documentation never stays in sync with code
That’s reality and it will happen in every project
#1: Env. Setup
10%
#2: Verification
Planning
10%
#3: Test Bench Implementation & debug
35%
#4: RTL Testing & Debug
40%
#5: Review, Doc &
Closure
5%
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Leveraging WYSIWYG: What you see is what you get
Draw scenarios, understand ideas invest your time in core verification
• WYSIWYG: concept widely used in Web and App Programming
• The main principle is that people process visual images better than text
• Define whatever you can graphically, then dive into coding when necessary
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Leveraging WYSIWYG: What you see is what you get
Why spend your time housekeeping
thousands of lines of UVM code?
When you can
Draw scenarios, understand ideas
invest your time in core verification
What Is ’Vtool’
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Restoring engineering creativity…
through automated UVM development
• Vtool applies WYSIWYG principles for verification
‐ Untangles UVM complexity
• Vtool fits into existing verification environments
• Vtool helps you:
‐ Create and maintain testbenches, faster and easier
‐ Automatically generate clean, bug free code
‐ Execute simulation and debug results on the fly
‐ Efficiently import, understand and reuse existing code
Synchronized Code and Abstract Visual Editing
• Powerful mechanism for experts and new users
‐ Visual abstract “whiteboard” editing
‐ Text code editing with updating overview
• Fast comprehension, no UVM complexity
‐ Easily understand reused code
• Enhances team co-operation, code maintenance
• Continuously synchronizes with existing code base
Build UVM environments from scratch or reused code
quickly, easily & accurately
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Optimized UVM Infrastructure Code Generation
• Saves weeks of complex coding, 50-80% of code-base
• Code efficient, optimized, easy to understand
• Code consistent and bug free across testbenches
• Generates documentation from visual plan
• Automates functional coverage creation
Dramatically Reduces Schedule, Allows Engineers to Focus on Verification
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Immediate Execution and Debug
• Execute simulation instantly
• Code runs with IUS, VCS, Questa
• Key debug issues extracted from noisy logs
• Clears a rapid, visual path to problem source
Execute simulation and narrow down code problems rapidly during development
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Cadence, Synopsys, Mentor
How It Works
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Use flow and under the hood operation
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Start a new project or open
existing one (UVC or TB)
Fill content in GUI (signals,
fields, coverage, etc.)
Vtool creates a UVM, Accellera
1.1 compilable
code base from templates
Vtool updates UVM
code with every click
HTML doc generated
Use the editor to code specific functions and
tasks
Vtool lints UVM on-the-fly and
Updates the GUI
Import user code
(Next release)
Run tests from GUI
Use Log Analyzer
for Debug
Vtool invokes attached simulator (IUS, VCS, Questa)
Vtool parses simulation log
file
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Block Diagram “Whiteboard”
Level
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UVM Code Editor Level
Stimulus Properties
Level
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Synchronous Operation: Every click regenerates the code Every edit updates the database
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Click ‘Run’ to start a
simulation
Code will always compile
and run
How it works
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Open Log for debug
How it works
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Graphical scenario
representation
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On-the-fly Documentation
creation
Targeting Verification Productivity Issues
Classic UVM Issues Vtool Environment
Incomplete spec, unavailable DUT
Reuse code match issues
Verification code debug complexity
Expert required for core modeling
Designers unable to assist in testing
Ramp on unintelligible, old code
Documentation out of sync
Templating schemes inflexible
Incremental development capability
Reuse through library function
Simplified code visualization & creation
Easy to employ for UVM novice
Designers understand the testbench
Load in old code, visualize structure
Automated documentation generation
Code regeneration enables flexibility
Vtool automates away many UVM complexities
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About the Company
San Jose Austin Belgrade Tel Aviv Munich Tokyo
• Vtool established in 3/2014 as a spinoff from Veriest, Israel’s #1 verification consulting firm
• Vtool developed over 4 years as part of
Veriest consulting, based on real project work
• Vtool operating worldwide, headquarters
located in verification powerhouse community, Israel
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Revolutionizing Verification Engineering
Summary - Vtool Saves you time for better work and better living
• UVM is useful, but complex, time consuming, and irritating
• Vtool: The verification WYSIWYG
• Proven schedule & quality improvements on real projects
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