Week 2Dr David WardDr. David Ward

Hybrid Embedded Systems

Today’s AgendaDiscuss Homework and LabsReminder: Buff One card numbers neededReview Chapter 5 (textbook)

FPGA basics

Embedded Core Design with FPGAs(Textbook)(Textbook)

A Simple Circuit (3 input / 4 output)•Simplest way to implement

• minterms using AND gates• Outputs by ORing appropriate minterms

m = minterm

AND-OR implementation

Not usedused

• No simplification of Karnaugh Map

Block Diagram

NOR implementation• Complement inputs => AND• Complement outputs => OR

Distributed Gates•Solves routing wires and building gates large inputs (e.g. 16 input = 64K minterms)

• AND plane: wires from inputs must be routed to > 64K NOR gates• OR plane: NOR gates must be large enough for every minterm of the function

to reach their inputs (> 64K minterms)

y = m2,m5, and m6m3 = a b c

to reach their inputs (> 64K minterms)•Distribute gates along rows and columns

-

fused

not fused

Array Programmable•Fixed AND-plane and programmable OR-plane

•Fusable transistors along OR-plane•OR-plane can only be known when the output functions are determined

Memory View (ROM)• Fixed AND-plane acts as a memory decoder• Progammable OR-plane becomes the memory array• One-time programmable logic array

ROM VariationsPROM: Programmable ROM

one-time programmableEPROM: Erasable PROMEPROM: Erasable PROM

Exposed to ultra-violate light for minutes to eraseEEPROM: Electrically Erasable Programmable ROM

Electrically erasableCan be erased and reprogrammed without remove it from its circuit

Flash Memory: Large EEPROMsPartitioned into smaller fixed sized blocks that can independently be erasedindependently be erased

Programmable Logic Array (PLA)Alt ti ith l fl ibilit d l• Alternative with less flexibility and less area

• Only use the rows that are actually used (m7 not used)• Minimize output functions; implement regained product terms• Must program both AND and OR planes outputs

sharingproductterms

PLA Implementation

Programmable Array Logic (PAL)• ROM: array logic with fixed AND-plane and programmable OR-plane• PLA: array logic with programmable AND-plane and programmable OR-plane• PAL: array logic with programmable AND-plane and fixed OR-plane

• Rationale:Rationale: • Outputs of large functions use a limited number of product terms • All product terms for all function outputs most likely not used• Fixed number of product terms per

( )output (maximum of three)• What if product terms for output is greater

than three?

unused

PAL ith P d t T E d bilitPAL with Product Term Expandability• Requires feedback from PAL outputs back into the AND-plane• Requires feedback from PAL outputs back into the AND-plane• Feedbacks used in AND-plane like regular inputs of PAL•Allows ORing a subset of product terms of the function

• Further ORed with remaining product terms of function

W= a b c+a b c+a b+a b cW= a·b·c+a·b·c+a·b+a·b·c

01

W = o2

Output feedbacks areOutput feedbacks are fixed not fused

PAL with Three-State Output Control• Pin (io2) used as output can also be used as input by turning off the three state gate that drives it

• Feedback lines allow for connection of io input into AND plane• Feedback lines allow for connection of io2 input into AND-plane• Three state output controlled by a programmable product term• Three-state inverting buffer can be replaced by XOR gate with three-state

output and fusable input

PAL with Registered Outputs• io2 capability:

•Registered output with three-state•Two-state output•Registered feedback into logic array•Input into the AND-plane

•Possible enhancements:•By-passing output register (registered or combinatorial output)By passing output register (registered or combinatorial output)

Commerical PartsPAL is trademark of American Micro Devices (AMD)PALs are referred to as PLDs or programmable logic devicesAl PLD d iAltera PLD devices

EPROM based (300 to 900 usable gates)Group of product terms that are Ored together referred to asGroup of product terms that are Ored together referred to as Macrocell

Number of Macrocells varies between 16 to 48Macrocell has a programmable register that can be programmedMacrocell has a programmable register that can be programmed as D,T,JK and SR flip-flop

EP1810 largest devicebl 8 M ll d i f 6 I/O i900 usable gates, 48 Macrocells, and a maximum of 64 I/O pins

Altera Classic Macrocell (EPLD Family)Mode 0: oe : tri-state output buffer controlled by single product term

combinatorial or registered

clk : global clockMode 1: oe: Always enabled

clk: clock signal generated by product term

tri-state

d f db kdirect feedback• registered• combinatorial

input

inversion

Complex Programmable Logic Devices (CPLD)•Extending PLDs using larger AND-plane and more macrocells to implement complex is not economical

•Instead CPLD use multiple PLDs with programmable wiring channels between thePLDs

PLD PLD

PLDs.

PLD PLD

PLDPLD

Altera MAX 7000s CPLDEPM7128S CPLD

EEPROM-based programmable logic device with in-system programmability feature via JTAGsystem programmability feature via JTAGLogic densities: 600 to 5000 usable gates (2500 for EPM7128S)

i l h Al PLD2 to 4 times larger than Altera PLDs8 PLDs referred to as Logic Array Blocks (LABs)

Each LAB has 16 macrocells (total macrocells is 128)( )LABs are linked by wiring channel referred to as Programmable Interconnect Array (PIA)Macrocells include hardware for expanding product terms byMacrocells include hardware for expanding product terms by linking several macrocells

Altera CPLD Architecture

PIA bus:• all dedicated inputs,•I/O pins• macrocell outputsLABs inputs:

6 i l f PIA d f l l i i• 36 signals from PIA used for general logic inputs• Global controls for secondary register functions•Direct input paths from the I/O pins to the register

Field Programmable Gate Array (FPGA)• More advanced programmable logic than CPLD• More advanced programmable logic than CPLD• More flexible then CPLD• Allows more complex logic implementation• Implement circuits >> 1 million gates

FPGA General Structure

Altera FLEX 10K FPGAEPF10K70 FPGA

SRAM-based FPGA that can be programmed via JTAG i t finterfaceLogic densities: 10,000 to 250,000 (118,000 for EPF10K70)40 960 RAM bits w/o reducing logic capacity (18 432 for40,960 RAM bits w/o reducing logic capacity (18,432 for EPF10K70)468 LABs (52 columns x 9 rows)Each LAB has 8 Logic Elements (LEs) => 3,744 LEs358 user I/O pins

FLEX 10K Block Diagram

•Each group of Les is combined into an LAB•LABs arranged into rows and columns•Each row contains a single Embedded Array Block (EAB)•LABs and EABs are interconnected by the FastTrack Interconnect•IOEs are located at the end of each row and column of the FastTrack Interconnect

Embedded Array Block (EAB)Used to implement memory and specialized logic functionsEAB for memory:

2048 bitsRAM, ROM, dual-port RAM, or FIFO

Dual port RAM has ability to simultaneously read and write different memory cells at different addresses.

EAB for logic function:100 to 600 gates for complex logic functions

Multipliers state machines DSP functionsMultipliers, state machines, DSP functionsImplemented by programming EAB with read-only pattern during configuration, creating a large look-up table

Combinatorial function are implemented by looking up the results,Combinatorial function are implemented by looking up the results, rather than computing them

FLEX 10K LAB Architecture

•8 LEs•Local•Local interconnect

FLEX 10K Logic Element (LE)FLEX 10K Logic Element (LE) Structure

•Smallest unit of logic•Smallest unit of logic•Four-input LUT (64K functions)•Programmable flip-flop

•D,T,JK,and SR

High speed data path:•Carry chain supports high-speed counters and adder•Cascade chain implements wide-input functions

Altera Cyclone FPGASRAM-based FPGALogic densities: up to 20,060 LEsPhase-locked-loops (PLLs) for clockingM4K RAM blocks are true dual-port memory blocks

General Outline of a Cyclone Device