vlsi projects completed list 2016-2017

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VLSI IEEE TRANSACTION - COMPLETED PROJECT

2016-17

Sno. TOPIC TECH.,

1 A Single-Ended With Dynamic Feedback Control 8T Sub-threshold SRAM Cell

TANNER

2 OTA-Based Logarithmic Circuit for Arbitrary Input Signal and Its Application

TANNER

3 A Robust Energy/Area-Efficient Forwarded-Clock Receiver With All-Digital Clock and Data Recovery in 28-nm CMOS for

High-Density Interconnects

TANNER

4 Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation

TANNER

5 A 0.1–3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS

TANNER

6 Read Bit line Sensing and Fast Local Write-Back Techniques in Hierarchical Bit line Architecture for Ultralow-Voltage

SRAMs

TANNER

7 Online Measurement of Degradation Due to Bias Temperature Instability in SRAMs

TANNER

8 Incorporating Process Variations Into SRAM Electro-migration Reliability Assessment Using Atomic Flux

Divergence

TANNER

9 A Fast-Transient Wide-Voltage-Range Digital-Controlled Buck Converter With Cycle-Controlled DPWM

TANNER

10 Designing Tunable Sub-threshold Logic Circuits Using TANNER

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Adaptive Feedback Equalization

11 Low-Power Variation-Tolerant Nonvolatile Lookup Table Design

TANNER

12 Low-Energy Power-ON-Reset Circuit for Dual Supply SRAM TANNER

13 Frequency-Boost Jitter Reduction for Voltage-Controlled Ring Oscillators

TANNER

14 High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator

TANNER

15 EMDBAM: A Low-Power Dual Bit Associative Memory With Match Error and Mask Control

TANNER

16 A Single-Stage Low-Dropout Regulator With a Wide Dynamic Range for Generic Applications

TANNER

17 Pre-charge-Free, Low-Power Content-Addressable Memory TANNER

18 A Low-Voltage Radiation-Hardened 13T SRAM Bitcell for Ultralow Power Space Applications

TANNER

19 A Process-Tolerant, Low-Voltage, Inverter-Based OTA for Continuous-Time, ADC

TANNER

20 Low-Power ECG-Based Processor for Predicting Ventricular Arrhythmia

VHDL

21 Low-Cost High-Performance VLSI Architecture for

Montgomery Modular Multiplication

VHDL/ Verilog

22 A New Parallel VLSI Architecture for Real-Time Electrical Capacitance Tomography

VHDL

23 High-Speed and Energy-Efficient Carry Skip Adder

Operating Under a Wide Range of Supply Voltage Levels VHDL

24 Graph-Based Transistor Network Generation Method for MICROWIND

S3 INFOTECH +91 988 48 48 198



Super gate Design

25 Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic

VHDL

26 A High-Performance FIR Filter Architecture for Fixed and

Reconfigurable Applications VHDL

27 In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers

VHDL

28 MACS: A Highly Customizable Low-Latency Communication Architecture

VHDL

29 A Computation and Energy Reduction Technique for HEVC Discrete Cosine Transform

Verilog

30 Low-Power System for Detection of Symptomatic Patterns in Audio Biological Signals

VHDL

31 Hybrid LUT/Multiplexer FPGA Logic Architectures TANNER/

VHDL

32 A Low-Cost Low-Power Ring Oscillator-Based Truly Random Number Generator for Encryption on Smart Cards

TANNER

33 A Method to Design Single Error Correction Codes With Fast Decoding for a Subset of Critical Bits

VHDL

34 Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops

TANNER

35 Concept, Design, and Implementation of Reconfigurable CORDIC

VHDL

36 Code Compression for Embedded Systems

Using Separated Dictionaries VHDL

37 Source Code Error Detection in High-Level

Synthesis Functional Verification C, VHDL

38 Low-Power FPGA Design Using

Verilog HDL

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Memoization-Based Approximate Computing

40 A Combined Deblocking Filter and SAO

Hardware Architecture for HEVC Verilog HDL

41 Input-Based Dynamic Reconfiguration of

Approximate Arithmetic Units for Video Encoding

VHDL

VLSI IEEE TRANSACTION - COMPLETED PROJECT

2015

Sno. TOPIC TECH.,

1 Seizure Prediction using Hilbert Huang Transform on Field Programmable Gate Array

Verilog

2 Dual Use of Power Lines for Design-for-Testability—A CMOS Receiver Design

TANNER

3 Design of a Network of Digital Sensor Macros for Extracting Power Supply Noise Profile in SoCs

VHDL

4 Design and FPGA Implementation of Reconfigurable Linear-Phase Digital Filter withWide Cutoff Frequency Range and

NarrowTransition Bandwidth

VHDL

5 VLSI IMPLEMENTATION OF EFFICIENT IMAGE WATERMARKING ALGORITHM

VHDL

6 Obfuscating DSP Circuits via High-Level Transformations

VHDL

7 Partially Parallel Encoder Architecture for Long Polar Codes

VHDL

S3 INFOTECH +91 988 48 48 198



8 Fully Reused VLSI Architecture ofFM0/Manchester Encoding Using SOLSTechnique for DSRC Applications

VHDL

9 Algorithm and Architecture for a Low-PowerContent-Addressable Memory Basedon Sparse Clustered Networks

VHDL

10 A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications

VHDL

11 Design and Low-Complexity Implementation of Matrix–Vector Multiplierfor Iterative Methods in Communication

Systems

VHDL

12 Low-Power and Area-Efficient Shift Register Using Pulsed Latches

TANNER

13 A Low-Power Architecture for the Designof a One-Dimensional Median Filter

VHDL

14 Reverse Converter Design via Parallel-Prefix Adders: Novel Components,Methodology, and Implementations

VHDL

15 Implementation of Sub-threshold AdiabaticLogic for Ultralow-Power Application

MICROWIND

16 Quaternary Logic Lookup Table in Standard CMOS VHDL/

MICROWIND

17 An Efficient Constant Multiplier ArchitectureBased on Vertical-Horizontal Binary CommonSub-expression

Elimination Algorithm forReconfigurable FIR Filter Synthesis

VHDL

18 A High-Throughput VLSI Architecture for Hard andSoft SC-FDMA MIMO Detectors

VHDL

19 Novel Block-Formulation and Area-Delay-EfficientReconfigurable Interpolation Filter Architecture

forMulti-Standard SDR Applications

VHDL

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20 Fully Pipelined Low-Cost and High-Quality Color Demosaicking VLSI Design for Real-Time Video Applications

VHDL

21 Lossless and Reversible Data Hiding in Encrypted Images with Public Key Cryptography

VHDL

22 A Low-Complexity Multiple Error CorrectingArchitecture Using Novel Cross ParityCodes Over GF(2m)

VHDL

23 Aging-Aware Reliable Multiplier Design WithAdaptive Hold Logic

Verilog

24 Byte-Reconfigurable LDPC Codec DesignWith Application to High-Performance ECC ofNAND Flash Memory Systems

VHDL

25 Secrecy Rate Optimizations for a MIMO SecrecyChannel With a Cooperative Jammer

VHDL

26 Pre-Encoded MultipliersBased on Non-Redundant Radix-4Signed-Digit Encoding

VHDL

vlsi projects completed list 2016-2017

Education