COURSE STRUCTURE AND SYLLABI

FOR

M.Tech

VLSI Design

(Electronics and Communication Engineering) 2015-2017

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

CENTURION UNIVERSITY OF TECHNOLOGY & MANAGEMENT

School of Engineering & Technology, Paralakhemundi.

M.Tech [VLSI Design]

Semester-ISubject Code

Course Title L T P Credit

MTVL1101

Analog VLSI Circuits 3 1 0 4

MTVD1102

Semiconductor Device Modeling

3 1 0 4

Elective-I 3 1 0 4VDPE 1213

Microsystems-Principle And Design

MTVL 1117

Architecture Design of ICs

MTVL 1116

Optimization Techniques and Soft Computing Applications

MTVL 1115

MEMS

Elective-II 3 1 0 4VLMT 1105

Introduction To Nano-Electronics

MTVD 1202

CAD for VLSI

MTVL 1118

VLSI and Image Processing

VLMT 1104

CMOS RF Circuit Design

Elective-III 3 1 0 4VDPE 1113

Reliability And Testing Of IC Design

MTVL 1119

Digital VLSI Testing

VDPE 1211

ASIC and SoC Design

MTVL1120

VLSI Design Lab-1 0 0 3 2

VDPT1108

Seminar-1 2

Total 24

Semester-IISubject Code

Course TitleL T P Credit

VLMT1202

Digital VLSI Design3 1 0 4

MTVD1201

VLSI Technology3 1 0 4

Elective-I 3 1 0 4MTVL1212

Mixed Signal IC design

VDPE1112

VLSI Physical Design

VDPE1204

Real Time Systems And Software

Elective-II 3 1 0 4VLMT1201

VLSI Signal Processing

VDPE1212

Emerging topics in IC design

VDPE1201

Analog and Mixed Signal Testing

Elective-III 3 1 0 4VLMT 1204

HDL & High Level Synthesis

VDPE1203

VLSI and MEMS Packaging

MTVL1213

VLSI Subsystem Design

MTVL1214

VLSI Design Lab-II 0 0 3 2

VDPT1208

Seminar-II 2

Total 24

Semester-IIISubject Code

Course Title Credit

MTVD2101 Low Power VLSI Design

3-1-0 4

MTVD2102 Embedded Systems Design

3-1-0 4

MTVD2103 Soft computing and its application to engineering research

MTVL2111 Advanced Digital VLSI Design

VLCV2108 Comprehensive Viva-Voce

2

VDPT2107 Thesis Part-I 10

Total Semester Credit

20

Semester-IVSubject Code

Course Title Credit

VDPT2201 Thesis Part-II 20

Total Semester Credit

20

TOTAL CUMULATIVE CREDITS( 4 SEMESTERS) ------------ 88

First SemesterAnalog VLSI Circuit (L-T-P:3-1-0)

[MTVL 1101]MODULE – I (16 hours)Introduction:The MOS Transistor, I-V Characteristics, Equivalent Circuits, NoiseResistor, Capacitors and Switches:Integrated Resistors, Integrated Capacitors, Analog Switches, Layout of SwitchesBasic Building Blocks:Inverter with Active Load, Cascode, Cascode with Cascode Load, Source Follower, Threshold Independent Level Shift, Improved Output Stages

MODULE – II (16 hours)Current and Voltage Sources:Basic and Cascode Current Mirrors, Current References, Voltage Biasing, Voltage References, bandgap reference,CMOS Operational Amplifiers:General Issues, Performance Characteristics, Basic Architecture, Two Stages Amplifier, cascode opamp, Frequency Response and Compensation, Slew Rate

MODULE – III (16 hours)Operational Amplifiers and OTAsDesign of Two Stage OTAs: Guidelines, Single Stage Schemes, Class AB Amplifiers, Fully Differential Op-Amps, Micro-Power OTAs, Noise Analysis, LayoutCMOS Comparators:Performance Characteristics, General Design Issues, Offset Compensation, Latches, Simple comparator, Switch-based comparator, Latch-based comparator.Oscillator: Ring oscillator, LC oscillator, Voltage control oscillator.

Textbooks:1. Behzad Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001.

ISBN: 0-07-238032-2. 2. Franco Maloberti, Analog Design for CMOS VLSI Systems, Kluwer Academic

Publishers, 2001. ISBN: 0-7923-7550-5.Reference Books:

1. Paul R. Gray, Paul J. Hurst, Stephen H. Lewis, and Robert G. Meyer, Analysis and Design of Analog Integrated Circuit, John Wiley & Sons, Inc., 4th edn., 2000. ISBN: 0-471-32168-0.

2. Phillip E. Allen and Douglas R. Holberg, CMOS Analog Circuit Design, Oxford University Press, 2nd edn., 2002. ISBN: 0-19-511644-5

3. Johan H. Huijsing, Operational Amplifiers–Theory and Design, Kluwer. ISBN: 0792372840

Semiconductor Device Modelling (L-T-P:3–1–0)[MTVD 1102]

MODULE – I (16 hours)Semiconductor Electronics Review:Elements of Semiconductor Physics, Physical Operation of a PN Junction, MOS Junction,MS JunctionPN–Junction Diode and Schottky Diode:DC Current-Voltage Characteristics, Static Model, Large-Signal Model, Small-Signal Model,Schottky Diode and its Implementation in SPICE2, Temperature and Area Effects on the DiodeModel Parameters, SPICE3, HSPICE and PSPICE ModelsBipolar Junction Transistor (BJT):Transistor Convention and Symbols, Ebers-Moll Static Model, Ebers-Moll Large-Signal Model, Ebers-Moll Small-Signal Model, Gummel-Poon Static Model, Gummel-Poon Large-Signal Model, Gummel-Poon Small-Signal Model, Temperature and Area Effects on the BJT Model Parameters, Power BJT, Model, SPICE3, HSPICE and PSPICE ModelsMODULE – II (16 hours)Junction Field-Effect Transistor (JFET):Static Model, Large-Signal Model and its Implementation in SPICE2, Small-Signal Model and itsImplementation in SPICE2, Temperature and Area Effects on the JFET Model Parameters,SPICE3, HSPICE and PSPICE ModelsMetal-Oxide-Semiconductor Transistor (MOST):Structure and Operating Regions of the MOST, LEVEL1 Static Model, LEVEL2 Static Model, LEVEL1and LEVEL2 Large-Signal Model, LEVEL3 Static Model, LEVEL3 Large-Signal Model, The Effect ofSeries Resistances, Small-Signal Models, The Effect of Temperature, BSIM1, BSIM2, SPICE3,HSPICE and PSPICE ModelsMODULE – III (16 hours)BJT Parameter Measurements:Input and Model Parameters, Parameter MeasurementsMOST Parameter Measurements:LEVEL1 Model Parameters, LEVEL2 Model (Long-Channel) Parameters, LEVEL2 Model (Short-Channel) Parameters, LEVEL3 Model Parameters, Measurements of Capacitance, BSIM ModelParameter Extraction, EKV ModelNoise and Distortions:Noise sources, Flicker noise, thermal noise, DistortionMetal-Semiconductor Field-Effect Transistor (MESFET), Ion-Sensitive Field-Effect Transistor

Textbooks:1. Paolo Antognetti and Giuseppe Massobrio, Semiconductor Device Modeling with SPICE, 2nd

edn., McGraw-Hill, New York, 1993, ISBN 0071349553 (paperback) or 007 0024693 (hardback).

Recommended Reading:1. Richard S. Muller, Theodore I. Kamins, and Mansun Chan, Device Electronics forIntegrated Circuits, 3rd edn., John Wiley and Sons, New York, 2003. ISBN: 0-471-59398-2.

2. H. Craig Casey, Devices for Integrated Circuits: Silicon and III-V CompoundSemiconductors, John Wiley, New York, 1999.3. Dieter K. Schroder, Semiconductor Material and Device Characterization, John Wiley andSons, New York, 1990.

Microsystems- Principle And Design (L-T-P:3-1-0)[VDPE 1213]

MODULE – I (16 hours) Introduction:Microfabrication disciplines, Substrates, Materials, Surfaces and interfaces, Processes, Lateral dimensions, Vertical dimensions, Devices, MOS transistor, Cleanliness and yield Micro-metrology and Materials Characterization:Microscopy and visualization, Lateral and vertical dimensions, Electrical measurements, Physical and chemical analyses, XRD (X-ray diffraction), TXRF (total reflection X-ray fluorescence), SIMS (secondary ion mass spectrometry), Auger electron spectroscopy (AES), XPS (X-ray photoelectron spectroscopy)/ESCA, RBS (Rutherford backscattering spectrometry), EMPA (electron microprobe analysis) / EDX (energy dispersive X-ray analysis), Analysis area and depth, Practical issues with micro-metrology.Simulation of Microfabrication Processes:Types of simulation, 1D simulation, 2D simulation, 3D simulationMODULE – II (16 hours)Processes for MicromachiningBasic Process Tools, Epitaxy, Oxidation, Sputter Deposition, Evaporation, Chemical-Vapor Deposition, Spin-On Methods, Lithography, Etching, Advanced Process Tools, Anodic Bonding, Silicon Direct Bonding, Grinding, Polishing and Chemical-Mechanical Polishing, Sol-Gel Deposition Methods, Electroplating and Molding, Supercritical Drying, Self-Assembled Mono-layers, SU-8 Photosensitive Epoxy, Photosensitive Glass, EFAB, Non-lithographic Micro-fabrication Technologies, Ultra-precision Mechanical Machining, Laser Machining, Electro-discharge Machining, Screen Printing, Micro-contact Printing/Soft Lithography, Nano-imprint Lithography, Hot Embossing, Ultrasonic Machining, Combining the Tools—Examples of Commercial Processes, Polysilicon Surface Micromachining, Combining Silicon Fusion Bonding with Reactive Ion Etching, DRIE of SOI Wafers, Single Crystal Reactive Etching and MetallizationMODULE – III (16 hours)MEM Structures and Systems in Industrial and Automotive Applications:General Design Methodology, Techniques for Sensing and Actuation, Common Sensing Methods, Common Actuation Methods, Passive Micromachined Mechanical Structures, Fluid Nozzles, Hinge Mechanisms, Sensors and Analysis Systems, Pressure Sensors, High-Temperature Pressure Sensors, Mass Flow Sensors, Acceleration Sensors, Angular Rate Sensors and Gyroscopes, Carbon Monoxide Gas Sensor, Actuators and Actuated Microsystems, Thermal Inkjet Heads, Micromachined Valves, Micropumps.

Text Books:1. Sami Franssila, Introduction to Micro-fabrication, John Wiley & Sons Ltd, 2004, ISBN

0-470-85105-8 (HB), ISBN 0-470-85106-6 (PB)2. NadimMaluf, Kirt, WilliamAn Introduction to Microelectro-mechanical Systems

Engineering Second Edition, 2004. ISBN 1-58053-590-93. P. Rai-Choudhury, Recent Advances in MEMS/MOEMS Technologies, SPIE Press,

2000. 4. S.M. Sze, Semiconductor Sensors, Wiley-Interscience Publishers, 1994.

MTVL1117 ARCITECTURE DESIGN OF ICs (L-T-P: 3-1-0)

MODULE-1 [16 Hours]System, Subsystem, VLSI Design Flow.Architectural Design-combinational, sequential, asynchronous, synchronous, purely synchronous.Resistance Transfer level- fan Out, Clock Skew,Synchronous Counter, Incrementer Circuit, Decrementer Circuit, Up-Down Counter.Design of Combinational Circuits, Gate Optimization, Critical path Delay- set up and Hold time.Design with critical path delay. Design of Multiply with integer, divide by integer circuits, 2x, xa

circuits

MODULE-2 [16 Hours]Mapping of Algorithm into architecture.Logical Optimization.Digital Structure- Data path, Control path. 2 Level , 3 Level Nesting.Number Representation, Left- right Shifter Circuit.Pipelining- Critical Path, Clock frequency, throughput, latency.Real Time System.

MODULE-3 [16 Hours]Power management- Calculation of Static and dynamic power, Short Circuit power, leakage power.Adder-Ripple carry adder, Adder with carry look ahed generator, Conditional Sum adder,Multiplier- Braun’s multiplier, Baugh-Wooly Multiplier, Matrix Multiplier, Systolic Array, Wave Front array.Testing- Faults, Design for testability, Built in Self Test, Fault Tolerant structure.CORDIC Architecture, Vectoring Mode, Hyperbolic Coordinates, Linear Coordinator, applications.

BOOKS

1. Digital Integrated Circuits: A Design Perspecive, J. M. Rabaey, Anantha Chandrakasan and Borivoje Nikolic, PHI/Pearson

2. CMOS VLSI Design: A circuits and Systems Perspective, West, Harris and Banerjee, Pearson.

3. Digital Integrated Circuit Design, from VLSI Architecture to CMOS Fabrication, Hubert Keislin, Cambridge University Press.

4. M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing, Kluwer Academic Publishers.

5. M. Abramovici, M. A. Breuer and A. D. Friedman, Digital Systems Testing and Testable Design, Wiley-IEEE Press.

6. Keshab K. Parhi. VLSI Digital Signal Processing Systems, Wiley-Inter Sciences, 19997. Anantha P. Chandrakasan and Robert W. Brodersen, Low Power Digital CMOS Design,

Kluwer Academic Publishers. 8. Kaushik Roy and Sharat C. Prasad, Low-Power CMOS VLSI Design, Wiley-

Interscience.9. Book Chapters, Journal research papers

MTVL1116 Optimization Techniques and Soft Computing Applications (L-T-P: 3-1-0 4)Module-1 (16 Hrs)Optimization: Optimal problem formulation, single variable optimization algorithms: exhaustive search method, golden section search method, Newton-Raphson method and other methods. Multivariable optimization algorithms: direct search methods, gradient-based methods and other methods. Constrained optimization. Local and global optimization. Single objective and multi-objective optimization.

Module-2 (16 Hrs)Integer programming, Geometric programming, simulated annealing. Evolutionary Computingand Swarm Intelligence: Genetic algorithm, particle swarm optimization, Bacterial Foraging Optimization and other biologically inspired algorithms.

Module-3 (16 Hrs)Artificial Neural Network: Introduction, Typical applications of ANNs : Classification, Clustering, Vector Quantization, Pattern Recognition, Function Approximation, Forecasting, Control, Optimization; NN model, NN architecture, Single-layer networks; Perceptron-Linear separability, Training algorithm, Limitations; Multi-layer networks-Architecture, Back Propagation Algorithm (BTA) and other training algorithms, Applications. Feed-forward networks, Radial-Basis-Function (RBF) and adaptive NN. Introduction to fuzzy logic.

BOOKS1. Optimization for Engineering Design: Algorithms and Examples, Kalyanmoy Deb, PHI2. D. E. Goldberg, Genetic Algorithms in search, Optimization and machine learning, 1989. 3. E. Bonabeau, M. Dorigo and G. Theraulaz, Swarm Intelligence : From natural to

Artificial Systems4. R. C. Eberhart, Y. Sai and J. Kennedy, Swarm Intelligence, The Morgan Kaufmann

Series in artificial Intelligence, 2001. 5. K. Mehrotra, C.K. Mohan and Sanjay Ranka, Elements of Artificial Neural Networks,

MIT Press, 1997 - [Indian Reprint Penram International Publishing (India), 1997]6. Simon Haykin, Neural Networks - A Comprehensive Foundation, Pearson7. Martin T. Hagan, Howard B. Demuth, Mark H. Beale; Neural Network Design; Thomson

2002

8. A Cichocki and R. Unbehauen, Neural Networks for Optimization and Signal Processing, John Wiley and Sons, 1993.

9. J. M. Zurada, Introduction to Artificial Neural Networks, (Indian edition) Jaico Publishers, Mumbai, 1997.

MTVL1115 MEMS (L-T-P: 3-1-0 4) Module-1(16 hrs)An introduction to MEMS; Evolution of microsensors & MEMS; Materials & microelectronic technologies for MEMS; fabrication process; Micromachining – surface and bulk micromachining: basic process flow, release, stiction, material choices, residual stress, stringers and planarization, wet etch-based, dissolved wafer process, SOI MEMS, Scream, Hexsil MEMS;

Module-2 (16 hrs)Micromachined microsensors : mechanical, inertial, thermal; Micromachined microactuators; Integrated smart sensors and MEMS; Interface electronics for MEMS; Electromechanical transducers: Piezoelectric transducers, Electrostrictive transducers, Magnetostrictive transducers, Electrostatic actuators, Electromagnetic transducers, Electrodynamic transducers, Electrothermal actuators, comparison of electrothermal actuation process, Microsensing for MEMS: Piezoresistive sensing, Capacitive sensing, Piezoelectric sensing, Resonant sensing, Surface Acoustic Wave sensors.

Module-3(16 hrs)MEMS Micromachined passive elements: pros and cons, MEMS Inductors: self and mutual inductance, micromachined inductors, reduction of stray capacitance, improvement of quality factor, folded inductors, modeling and design issues of planar inductors, variable inductor and polymer based inductor. MEMS Capacitors: MEMS gap tuning capacitor, MEMS area tuning capacitor, Dielectric Tunable capacitors.Microsensors & MEMS applications; MEMS for RF applications (RF MEMS); MEMS for Biomedical applications (BioMEMS); Microfluidics & their applications; Bonding & packaging of MEMS; MEMS packaging: Role of MEMS packaging, Types of MEMS packaging, flip-chip and multichip module packaging, RF MEMS packaging issues,

Books1. Microsystem Design, Stephen D. Senturia2. Micromachined Transducers Sourcebook, Gregory T. Kovacs 3. MEMS and Microsystems: Design and Manufacture-Tai-Ran Hsu, 1st Ed., Tata

McGraw-Hill, 2002.4. RF MEMS: Theory, Design, and Technology-Gabriel M. Rebeiz, 1st Ed., John Wiley & Sons, 2003. 5. RF MEMS & Their Applications-V. K. Varadan, K. J. Vinoy and K. A. Jose, 1st Ed., John

Wiley & Sons, 2003.

6. S.M. Sze, VLSI Technology, 2nd

ed., McGraw-Hill Publishing company, NY, 1988

7. Sorab K. Ghandhi, VLSI Fabrication Principles – Silicon and Gallium Arsenide, 2nd

ed., John Wiley and Sons, Inc., NY, 1994.

Introduction To Nano-Electronics (L-T-P:3-1-0)[VLMT 1105]

MODULE – I (16 hours)Introduction to Nanoelectronics: The “top-down” approach, The “bottom-up” approach, Nanoelectronis and nanotechnology potential.Classical Particles, Classical Waves and Classical Quantum Particles: Comparison of classicaland quantum systems, Origin of quantum mechanics, Light as a wave and light as a particle, Electrons as particles and electron as waves, Wavepackets and uncertainty.Quantum Mechanics of Electrons: General postulates of quantum mechanics, Time-independentSchrodinger’s equation, Analogies between quantum mechanics and classical electromagnetics, Probabilistic current density, Multiple particle systems, Spin and angular momentum.Free and Confined Electrons: Free electrons, The free electron gas theory of metals, Electronsconfined to a bounded region of space and quantum numbers, Fermi level and chemical potential, Partially confined electrons – Finite potential wells, Electrons confined to atoms – The hydrogen atom and the periodic table, Quantum dots wires and wells.

MODULE – II (16 hours)

Electrons Subject to a Periodic Potential – Band Theory of Solids: Crystalline materials,Electrons in a periodic potential, Kronig-Penney model of band structure, Band theory of solid – Doping in Semiconductors, Interacting systems model, The effect of an electric field on energy bands, Band structures of some semiconductors, Electronic bond transitions –interaction of electromagnetic energy and materials, Graphene and carbon nanotubes.Tunnel Junctions and Applications of Tunneling: Tunneling through a potential barrier, Potentialenergy profiles for material interfaces, Applications of tunneling – Field emission, Gate-oxide tunneling and hot electron effects in MOSFETs, Scanning tunneling microscope, Double barrier tunneling and the resonant tunneling diode.Coulomb Blockade and the Single-Electron Transistor: Coulomb blockade–Coulomb blockade inananocapacitor, Tunnel junctions, Tunnel junction excited by a current source, Coulomb blockade in a quantum dot circuit, The single electron transistor, Other SET and FET structures – Carbon nanotube transistor, Semiconductor nanowire FETs and SETs, Molecular SETs and molecular electronics.

MODULE – III (16 hours)

Particle Statistics and Density of States: Density of states in lower dimensions, Density of states in a semiconductor, Classical and quantum statistics – Carrier concentration in materials, The importance of the Fermi electrons, Equilibrium carrier concentration and the Fermi level in semiconductor.Models of Semiconductor Quantum Wells, Quantum Wires and Quantum Dots:

Semiconductorheterostructures and quantum wells, Quantum wires and nanowires, Quantum dots and nanoparticles, Fabrication techniques for nanostructures – Lithography, Nanoimprint lithography, Split-gate technology, Self-assembly.Nanowires, Ballistic Transport and Spin Transport: Classical and semi-classical transport–Classical theory of conduction – free electron gas model, Semi-classical theory of electrical conduction – Fermi gas model, Classical resistance and conductance, Conductivity of metallic nanowires – the influence of wire radius, Ballistic transport – Electron collisions and length scales, Ballistic transport model, Quantum resistance and conductance, Origin of quantum resistance, Carbon nanotubes and nanowires, Transport of spin and spintronics – the transport of spin, Sprintonic devices and applications. Text Books:

1. George W. Hanson, Fundamentals of Nanoelectronics, Pearson Education, 2009, ISBN: 978-81-317-2679-2.

Recommended Reading: 1. Vladimir V. Mitin, Viatcheslav A. Kochelap and Michael A. Stroscio, Introduction to

NanoelectronicsScience, Nanotechnology, Engineering, and Applications, Cambridge University Press, 2008, ISBN: 978-0-521-88172-2

2. M. Kuno, Introduction to Nanoscience and Nanotechnology: A Workbook, http://nd.edu/~mkuno/Class_downloads/Chem647_nano_text.pdf

3. G.L. Hornyak, H.F. Tibbals, JoydeepDutta, and J.J. Moore,Introduction to Nanoscience& Nanotechnology, CRC Press, 2008 ISBN: 9781420047790 ISBN 10: 1420047795.

4. Jeremy Ramsden, Essentials of Nanotechnology, BOOKBOON.com, ISBN 978-87-7681-418

MTVD 1202 CAD FOR VLSI CIRCUITS (3-1-0)

Module-1(16 hrs)

VLSI DESIGN METHODOLOGIES Introduction to VLSI Design methodologies - Review of Data structures and algorithms -Review of VLSI Design automation tools - Algorithmic Graph Theory and Computational Complexity – Tractable and Intractable problems - general purpose methods for combinatorial optimization.

DESIGN RULESLayout Compaction - Design rules - problem formulation - algorithms for constraint graph compaction

Module-2 (16 hrs)

DESIGN RULES – placement and partitioning - Circuit representation - Placement algorithms –circuit partitioning algorithm – KL Algorithm

FLOOR PLANNING

Floor planning concepts - shape functions and floorplan sizing - Types of local routing problems -Area routing - channel routing - global routing - algorithms for global routing.

Module-3 (16 hrs)

SIMULATION Simulation - Gate-level modeling and simulation - Switch-level modeling and simulation -Combinational Logic Synthesis - Binary Decision Diagrams - Two Level Logic Synthesis.Formal verification

MODELING AND SYNTHESISHigh level Synthesis - Hardware models - Internal representation - Allocation - assignment andscheduling - Simple scheduling algorithm - Assignment problem - High level transformations.

REFERENCES1. S.H. Gerez, "Algorithms for VLSI Design Automation", John Wiley & Sons, 2002.2. N.A. Sherwani, "Algorithms for VLSI Physical Design Automation", Kluwer Academic Publishers, 20023. Sadiq M. and Sait Habib Youssef, VLSI Physical Design Automation: Theory and Practic, World Scientific Publishing4. Michael Smith, Application Specific Integrated Circuit, Addison-Wesley, 1997

MTVL1118 VLSI AND IMAGE PROCESSING (L-T-P: 3-1-0)

MODULE-I (16 hrs)

Introduction, Image processing algorithms, Image processing tasks, Industrial handling and inspection, Range imaging and robot vision, Biomedical image processing. Low-level image processing operations: Classification of low level operations, Examples of low level operations, Discussion on the requirements for low-level operations. Description of some intermediate level operations: Recognition based on the matching of line segment graphs, The A* algorithm applied on path finding, Signed Euclidian distance transform, Region growing applied on segmentation of range images .

MODULE-II: (16 hrs)

Image processing architectures: Classifications of architectures. Uni- and Multi-processors, RISC architectures, Vector processor architectures, Digital Signal Processors. MIMD systems: The Ncube architecture, The Transputer architecture. SIMD systems: The CLIP4 (SPA/LPA) The Connection Machine (SPA/Ncube), The PICAP-3 and the Centipede (LPA), The CLIP7a (LPA). Pipelines: The Warp, The Cyto HSS, The PAPS system and Febris chip, The Sarnoff Pyramid chip, The NEC IMPP. Morphology based image processing: Cellular logic processing-Introduction, Mathematical Morphology, Cellular Logic Operations, Thinning variants,

MODULE-III: (16 hrs)

Conditions for multi-dimensional thinning: Introduction, Definition of an N dimensional binary image, image edge and image element, Connectivity of image elements and neighborhood in an N dimensional image, The structure of objects in N dimensional images, Foreground and background connectivity in XN, Connectivity of basic objects in an N dimensional image, The geometry of basic objects, Detection of basic objects in images, Detection of compound objects in images, Thinning as conditional erosion, Logic minimization and logic operations on mask sets, Thinning examples in 3-D, Parallel or sequential thinning and recursive neighbourhoods. Pipelined low level image processing: Devices for cellular logic processing, Square Processor, Arrays Pyramids, Linear Processor Arrays, Pipelines. A design method for special architectures.

Text Book:

1. Morphological Image Processing: Architecture and VLSI design by Pieter Jonker, Springer-Verlag, 1993

Reference Books

2. VLSI for pattern recognition and image processing, King Sun Fu, Springer-Verlag, 20123. VLSI Image Processing, Raymond J. Offen, McGraw-Hill.

CMOS RF CIRCUIT DESIGN (L-T-P: 3-1-0)[VLMT 1104]

MODULE-I (16 hours)Introduction: Introduction to RF Design and Wireless Technology, Design and Applications, Complexity and Choice of Technology.Basic Concepts in RF Design, Nonlinearly and Time Variance, Inter symbol Interference Characteristics ,Conversion of Gains and Distortion Characteristics of passive IC components : Resistors, Capacitors, Inductors, Transformers, Interconnect at RF and high frequencies, Skin effectBJT and MOSFET Behavior at RF Frequencies: BJT and MOSFET Behavior at RF Frequencies, Modeling of the Transistors,Noise Performance and Limitations of Devices, Integrated Parasitic Elements at High Frequencies and their Monolithic Implementation.MODULE-II (16 hours)High-frequency Amplifier Design: Zeros as bandwidth enhancers, Shunt-series amplifier,Bandwidth enhancement with fTdoublers, Tuned amplifiers, Neutralization and unilateralization,Cascaded amplifiers, AM-PM conversion.Voltage Reference: Review of diode behavior, Diodes and Bipolar Transistors in CMOS technology, Supply-independent bias circuits, Bandgap voltage reference, Constant-gmbias.Noise: Thermal noise, Short noise, Flicker noise, Popcorn noise, Classical two-port noise theory,Examples of noise calculations.MODULE-III (16 hours)RF Circuits Design andRF Testing: Overview of RF Filter Design, Active RF Components & Modeling, Matching and Biasing Networks. Basic Blocks in RF Systems and Their VLSI

Implementation, RF Testing for Heterodyne, Homodyne, Image Reject, Direct IF And Sub Sampled ReceiversLow-Noise Amplifier (LNA) Design: Derivation of intrinsic MOSFET two-port noise parameters, LNA topologies – Power match Vs. Noise match, Power-constrained noise optimization, Design Example, Linearity and large signal performance, Spurious-free dynamic range.Mixers: Mixer fundamentals, Design of Mixers at GHz Frequency Range, Non-linear systems as linear mixers, Multiplier-based mixers, Subsampling mixers, Diode-ring mixers.

Text Book: 1. Thomas H. Lee, Design of CMOS RF Integrated Circuits, Cambridge University press, 1998

Reference Books: 1. B. Razavi, RF Microelectronics, PHI, 1998 2. R. Jacob Baker, H.W. Li, D.E. Boyce, CMOS Circuit Design, Layout and Simulation, PHI, 1998 3. Y.P. Tsividis, Mixed Analog and Digital Devices and Technology, TMH, 1996 4. E.N. Farag and M.I. Elmasry, Mixed Signal VLSI Wireless Design: Circuits &Systems,Kluwer, 1999.

Reliability And Testing Of IC Design (L-T-P: 3-1-0)[VDPE 1113]

MODULE – I (16 hours)

Basic Concepts, Quality and Reliability Assurance of Complex Equipments and Systems:Introduction, Basic Concepts, Basic Tasks and Rules for Quality and Reliability Assurance of Complex Equipments and SystemsProbability Theory, Stochastic Process and Mathematical Statistics for Reliability Analysis:Concept of Probability, Random Variables and Random Vectors, Distribution Functions used in Reliability Analysis, Limit Theorems, Renewal Processes, Regenerative and Semi-Regenerative Processes, Markov and Semi-Markov Processes, Non-regenerative Stochastic processes, Empirical Methods in Mathematical Statistics, Parameter Estimation, Testing Statistical HypothesesReliability Analysis During the Design and Development Phases:Introduction, Predicted Reliability of Equipments and Systems with Simple Structure, Reliability of Systems with Complex Structure, Reliability Allocation, Mechanical Reliability, Drift Failure, Failure Mode Analyses, Reliability Aspects in Design Reviews

MODULE – II (16 hours)

Qualification Tests for Components and Assemblies:Basic Selection Criteria for Electronic Components, Qualification Tests for Complex Electronic Components, Failure Modes, Failure Mechanisms, and Failure Analysis of Electronic Components, Qualification Tests for Electronic AssembliesMaintainability Analysis:Maintenance and Maintainability, Maintenance Concepts, Maintainability Aspects in Design reviews, Predicted Maintainability, Basic Models for Spare Part Provisioning, Cost ConsiderationsDesign Guidelines for Reliability, Maintainability and Software Quality:Design Guidelines for Reliability, Design Guidelines for Maintainability, Design Guidelines for Software Quality

MODULE – III (16 hours)

Reliability and Availability of Repairable Systems – II:Introduction and General Assumptions, One-Item Structure, Systems with Redundancy, 1-out-of-2 Redundancy, k-out-of-n Redundancy, Simple Series-Parallel Structures, Approximate Expressions for Large Series-Parallel Structures, Systems with Complex Structures, Computer-Aided Reliability and Availability ComputationsStatistical Quality Control and Reliability Tests:Statistical Quality Control, Statistical Reliability Tests, Statistical Maintainability Tests, Accelerated Testing, Goodness-of-fit Tests, Statistical Analysis of General Reliability DataQuality and Reliability Assurance During the Production Phase:Basic Activities, Testing and Screening of Electronic Components, Test and Screening Strategies, Economic Aspects, Reliability Growth

Text Books:

1. Alessandro Birolini, Reliability Engineering Theory and Practice, 4th Edn., Springer (India) Pvt. Ltd., 2006, ISBN: 8181284518

Reference Books:

1. P.K. Lala, Digital Circuit Testing and Testability, Academic Press, 1997 2. M.T.C. Lee, High-Level Test Synthesis of Digital VLSI Circuits, Artech, 1997 3. P. Mazumdar and K. Chakreborty, Testing & Testable Design of High Density Random

AccessMemories, Kluwer, 1996

MTVL1119 Digital VLSI Testing (L-T-P: 3-1-0 4) Module1 (16)Introduction to VLSI testing, test process and automatic test equipment, test economics and product quality, test economics. Physical faults and their modeling, Fault equivalence and dominance; fault collapsing. Fault simulation: parallel, deductive and concurrent techniques; critical path tracing.Module-2 (16 Hrs)Testability measure: controllability and observability measure for both combinational and sequential circuits. Test generation for combinational circuits: Boolean difference, D-algorithm, PODEM, etc. Exhaustive, random and weighted test pattern generation; aliasing and its effect on fault coverage. Test pattern generation for sequential circuits.Module-3 (16 Hrs)Design-for-Testability: ad-hoc and structures techniques, scan path and LSSD, Full, partial, Random-Access scan. Built-in self-test (BIST) techniques. Memory Testing: permanent, intermittent and pattern-sensitive faults; test generation Boundary scan. Other advanced topics in testing.

Text Books1. M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing, Kluwer

Academic Publishers. 2. M. Abramovici, M. A. Breuer and A. D. Friedman, Digital Systems Testing and

Testable Design, Wiley-IEEE Press.Reference Books

3. N. K. Jha and S. Gupta, Testing of Digital Systems, Cambridge University Press. 4. VLSI Test Principles and Architectures; Wang, Wu and Wen; Elsevier.5. P. H. Bardell, W. H. McAnney and J. Savir, Built-in Test for VLSI:

Pseudorandom Techniques, Wiley Interscience. 6. P. K. Lala, Fault Tolerant and Fault Testable Hardware Design, Prentice-Hall. 7. A. Krstic and K-T Cheng, Delay Fault Testing for VLSI Circuits, Kluwer

Academic Publishers. 8. A. Osseiran (Ed.), Analog and Mixed Signal Boundary Scan, Kluwer Academic

Publishers.

VDPE 1211 ASIC and SoC Design (3 – 1 – 0)

MODULE – I (16 hours)

Introduction: Voice over IP SOC, Intellectual Property, SOC Design Challenges, DesignMethodology.Overview of ASICs: Introduction, Methodology and Design Flow, FPGA to ASIC Conversion,Verification.

MODULE – II (16 hours)SOC Design and Verification: Introduction, Design for Integration, SOC Verification, Set-Top-Box SOC, Set-Top-Box SOC Example. Summary. References.

Physical Design: Introduction, Overview of Physical Design Flow, Some Tips and Guidelines for Physical Design, Modern Physical Design Techniques.

MODULE – III (16 hours)Low-Power Design: Introduction, Power Dissipation, Low-Power Design Techniques andMethodologies, Low-Power Design Tools, Tips and Guidelines for Low-Power Design.

Low-Power Design Tools: PowerTheater, PowerTheater Analyst, PowerTheater Designer.

Open Core Protocol (OCP): Highlights, Capabilities, Advantages, Key Features.

Phase Locked Loops (PLLs): PLL Basics, PLL Ideal Behavior, PLL Errors.

Text Books:1. Farzad Nekoogar and Faranak Nekoogar, From ASICs to SOCs: A Practical Approach, Pearson Education, 2003, ISBN-10: 0-13-033857-5, ISBN-13: 978-0-13-033857-0

Recommended Reading:2. Michael Smith, Application Specific Integrated Circuit, Addison-Wesley, 1997, ISBN:02015002213. Jari Nurmi, Processor Design: System-On-Chip Computing for ASICs and FPGAs,Springer, 1st edition, 2007, ISBN: 1402055293 4. Douglas J. Smith, HDL Chip Design – a practical guide for designing, synthesizing andsimulating ASICs and FPGAs using VHDL or Verilog, Doone Publications, 2000, ISBN: 0965193438

VLSI Design Lab-1 (L-T-P: 0-0-2[MTVL 1120]

The following experiments need to be carried out using EDA Tool (SPICE):1. Study of NMOS and PMOS characteristics. Extraction of device model parameters.2. Layout and circuit simulation of inverter.3. Study of static and transient behavior of CMOS inverter.4. Design of different current mirror circuits5. Design of different common source amplifier6. Design of different current sources7. Design of Voltage Reference circuits8. Design of differential amplifiers9. Design of CMOS Operational amplifier 10. Design of comparators: General comparator and Latched comparator11. Design of Flash type ADC, SAR ADC12. Design of Voltage Controlled Oscillators: Ring type VCO and Current starved VCO13. Design of Switch capacitor filter14. Design of Low Noise Amplifier

SECOND SEMESTER DIGITAL VLSI DESIGN (L-T-P:3-1-0)[VLMT 1202]

Module-I (16 hrs)Introduction to MOSFETs: MOS transistor theory, Fabrication process and Modeling (Designer’s View -point). MOS Inverter: Static and Switching Characteristics; MOS Capacitor; Resistivity of Various Layers, Symbolic and Physical Layout Systems -- MOS Layers, Stick/Layout Diagrams; Issues of Scaling. Combinational MOS Logic Circuits: Pass Transistors, Transmission Gates; Primitive Logic Gates; Complex Logic Circuits, ratioed logic-saturated load, pseudo-NMOS logic, transistor sizing in static CMOS logic.

Module-II (16hrs)Logical effort: delay estimation and delay minimization. Dynamic Logic Circuits; Sequential MOS Logic Circuits: Latches and Flip-flops, Clocking Issues, Rules for Clocking. Performance Analysis.CMOS Subsystem Design; Data Path and Array Subsystems: Addition / Subtraction, Comparators, Counters, Coding, Multiplication and Division.

Module-III (16 hrs)SRAM, DRAM, ROM, Serial Access Memory, Context Addressable Memory. flash memories, low-power memory.

Essential Reading: 1. J.M Rabey, A. Chandrakasan and B.Nicolic, Digital Integrated Circuits: A design Prespective, Second Edition, Pearson/PH, 2003 ( Cheap Edition)

Supplementary Reading: 1. J.P Uyemura, Introduction to VLSI Circuits and Systems, Wiley, 2001 2. W. Wolf, Modern VLSI Design: Systems-on Chip Design, Third Edition, Pearson/PH,2002 (Cheap Edition) 3. R. L. Geiger, P.E. Allen and N.R. Strader, VLSI Techniques for Analog and Digital Circuits, McGraw-Hill, 1990

VLSI Technology (L-T-P:3-1-0)[MTVD 1201]

MODULE – I (16 hrs) Introduction:Moore’s Law and material processing, Defects in crystals, Eutectic phase diagram, Solid solubility, Homogeneous nucleation, Heterogeneous Nucleation, Growth processesCrystal Growth:Necking and dislocation free CZ crystal growth, Segregation of impurities along length and diameter, Defects in CZ crystals, FZ Crystal growth Epitaxy:Vapour phase epitaxy, LPE, MBE, CVD deposition of Polysilicon, SILOX ProcessDiffusion:

Constant & limited source diffusion, Concentration dependent diffusion, Field assisted diffusion, Junction depth, Open tube and closed tube diffusion, Diffusion sources.

MODULE – II (16 hrs) Ion Implantation:Basic process, Ion Implantation Systems, Ion penetration and profile, Ion Implantation Damage, AnnealingOxidation:Purpose, Dry and wet oxidation, Deal-Grove model, Oxidation system, Properties of oxides –Masking and charges in oxidesDeposition Processes:Fundamentals of vacuum systems, Vacuum evaporation of thin films, DC and RF Sputtering of thin films, Interconnects, Contacts and dielectrics in IC Fabrication, Deposition of Silicon Nitride, Silicides and insulating layersLithography:Pattern generation and mask making, Optical Lithography – Contact, Proximity and ProjectionPrinting, Photoresists – Negative, Positive, Lift-off process, Electron beam and X-ray lithographic techniques.

MODULE – III (16 hrs)Etching:Wet Etching, Isotropic and Anisotropic Etching, Plasma Etching, Reactive Ion Beam Etching.IC Process Integration:Bipolar Transistor Fabrication, Isolation techniques, P-MOS, N-MOS and C-MOS processes, IC Fabrication Process Integration, IC Process Yield and ReliabilityMEMS Fabrication Processes:Micro machining, Bulk Micro machining, Surface Micro machining, Deep RIE, Advanced Lithography, HEXIL & SCREAM Process, Polymer molding and LIGA ProcessText Books:1. S.K. Gandhi, VLSI Fabrication Principles: Silicon and Gallium Arsenide, Wiley India Pvt. Ltd., New Delhi, 2nd edn. (1994), ISBN: 0471580058.2. Marc J. Madou, Fundamentals of Microfabrication, CRC Press (2002), ISBN: 0849308267

MTVL1212 Mixed Signal IC Design (L-T-P: 3-1-0 4) Module-1 (16 hrs)Introduction to Mixed-signal design; Data converters: Introduction and characterization of ADC and DAC, Block diagram of SAR ADC, Design of SAR ADC, Working principle and architecture of a folding-and-interpolation ADC, Design of sample and hold amplifier, Design of folding amplifier and interpolation network.Module-2 (16)Working principle, various architecture and design of different high speed ADCs (e.g. flash ADC, pipeline ADC and others) and high resolution ADCs (e.g. sigma-delta converters), Working principle and various architecture of different high speed and high resolution DAC, Phase locked loop: Simple PLL, Building blocks in PLL, Locking characteristic of PLL and Design of PLL; non-ideal effects in PLLs, Charge-Pump. PLL based frequency synthesizer, Application and block diagram of a DLL,

Module-3 (16 hrs)Design of a multiphase generator; Switched-Capacitor Circuits: switched-capacitor amplifiers, switched-capacitor integrator. Filters: Continuous time filter, Low pass, high pass and band pass active filter, Design of switched-capacitor filter, Design of Gm-C filter, Design of decimation filter.Implementation of system on a chip and the associated issue: Precautionary measure for integrating analog and digital modules within an IC, Signal integrity, floor planning and physical design of mixed signal IC design.

Text Books 1. CMOS mixed-signal circuit design by R. Jacob Baker, Wiley India, IEEE press, 1st edition, 2009. 2. Design of analog CMOS integrated circuits by Behzad Razavi, McGraw-Hill, 1st edition, 2011.

Reference Book 1. CMOS circuit design, layout and simulation by R. Jacob Baker, second edition, IEEE press, Wiley India, 2011. 2. CMOS Integrated ADCs and DACs by Rudy V. dePlassche, Springer, Indian edition, 2nd edition, 2007. 3. Electronic Filter Design Handbook by Arthur B. Williams, McGraw-Hill, 1981. 4. Design of analog filters by R. Schauman, Oxford university Press, 1st edition, 2010 5. An introduction to mixed-signal IC test and measurement by M. Burns et al., Oxford university press, first Indian edition, 1st edition, 2009.

VLSI Physical Design (L-T-P: 3-1-0)[VDPE 1112]

MODULE – I (16 hrs) Introduction to VLSI Physical Design Automation:VLSI Design Cycle, Physical Design Cycle, Design Styles, System Packaging Styles, HistoricalPerspectives, Existing Design ToolsDesign and Fabrication of VLSI Devices:Fabrication Materials, Transistor Fundamentals, Fabrication of VLSI Circuits, Design Rules, Layout of Basic DevicesFabrication Process and its Impact on Physical Design:Scaling Methods, Status of Fabrication Process, Issues Related to the Fabrication Process, Future of Fabrication Process, Solutions for Interconnect Issues, Tools for Process DevelopmentMODULE – II (16 hrs)Review of VLSI Design automation tools:Algorithmic and system design, Structural and logic design, Transistor level design,layout design,verification methods, Design management methods.Data Structure and Basic Algorithms:Basic Terminology, Complexity Issues and NP-hardness, Basic Algorithms, Basic Data Structures, Graph Algorithm for Physical DesignPartitioning:

Problem Formulation, Classification of Partitioning Algorithms, Group Migration Algorithm, Simulated Annealing and EvolutionMODULE – III (16 hrs)Floor Planning: Floor planning concepts, shape functions , floorplan sizing , Constraints based floor planning, integer programming based floor planning,chip planning Placement:Circuit representation,Wire length estimation,types of placement problems,Constructive placement algorithm,iterative improvement algorithm.Routing:Types of local routing problems,Arearouting,channelrouting,introduction to global routing.Text Books:1. S.H. Gerez, "Algorithms for VLSI Design Automation", John Wiley & Sons, 2002.2. N.A. Sherwani, "Algorithms for VLSI Physical Design Automation", Kluwer Academic Publishers

Real Time Systems And Software (L-T-P:3-1-0)[VDPE 1204]

Module I (16 hrs) Introduction: Definition, Issues in Real Time Computing, Structure of a Real Time System. Task Classes Characterizing Real Time Systems and Tasks: Introduction, Performance measures for real time systems: Traditional performance measures, Performability, Cost functions and hard Deadlines Task Assignment and Scheduling: Introduction , Classical Uniprocessor scheduling algorithms: Rate Monotonic, EDF algorithm, Task assignment, Fault tolerant Scheduling

Module II (16 hrs) Real Time Databases: Basic definitions, Real time Vs General Purpose databases, Main Memory databases, concurrency control issues, databases for hard real time systems

Module III (16 hrs)Real Time Communication: Introduction, Archtectural Issues, Protocols: Contention based protocols,Token based protocols, Deadlines based protocols, Stop and Go Multihop protocol, The polled bus protocol, Hierarchical round robin protocol. References:1. "Real Time Systems"-Liu Pearson Education 2. "Real ?Time Systems"-C. M. Krishna and Kang G. Shin

VLSI SIGNAL PROCESSING (L-T-P: 3-1-0)[VLMT 1201]

MODULE-I (16 hours)Introduction to DSP System:Typical DSP algorithms, DSP application demands and scaled CMOS technology, Representation of DSP algorithms.Iteration Bound:Data-flow graph representations, Loop bound and iterartion bound, Algorithms for computing iteration bound, Iteration bound of multirate data-flow graphsPipeling and Parallel Processing: Introduction, Pipeling of FIR Digital Filters, Parallel Processing. Pipelining and Parallel Processing for Low Power.Retiming: Introduction, Definition and Properties, Solving System of Inequalities, Retiming Techniques.MODULE-II (16 hours)Unfolding: Introduction an Algorithms for Unfolding, Properties of Unfolding, Critical Path, Unfolding and Retiming Application of Unfolding.Folding: Introduction to Folding Transformation, Register Minimization Techniques, Register Minimization in Folded Architectures, Folding in Multirate Systems.MODULE-III (16 hours)Systolic Architecture Design: Introduction, Systolic Array Design Methodology, FIR Systolic Arrays, Selection of Scheduling Vector, Matrix Multiplication and 2D Systolic Array Design, Systolic Design for Space Representations Containing Delays. Fast Convolution: Introduction, Cook Toom Algorithm, Winogard Algorithm, Iterated Convolution, Cyclic Convolution, Design of Fast Convolution Algorithm by Inspection.

Text Books:

1.Keshab K. Parhi. VLSI Digital Signal Processing Systems, Wiley-Inter Sciences, 1999

Reference Books::

1. Richard J, Higgins, Digital Signal Processing in VLSI, Prentice Hall, ISBN-10:013212887X, ISBN-13: 97801321288722. Mohammed Ismail, Terri, Fiez, Analog VLSI Signal and Information Processing, McGraw Hill, 1994.3. Kung. S.Y., H.J. While house T.Kailath, VLSI and Modern singal processing, Prentice Hall, 1985.4. Jose E. France, YannisTsividls, Design of Analog Digital VLSI Circuits for Telecommunications and Signal Processing‟ Prentice Hall, 1994.

VDPE 1212 Emerging Topics in IC Design (3 – 1 – 0)MODULE – I (16 hours)Review of MOS circuits: MOS and CMOS static plots, switches, comparison between CMOS and BI- CMOS.MESFETS: MESFET and MODFET operations, quantitative description of MESFETS.MIS structures and MOSFETS: MIS systems in equilibrium, under bias, small signal operation of MESFETS and MOSFETS.

MODULE – II (16 hours)Short channel effects and challenges to CMOS: Short channel effects, scaling theory, processing challenges to further CMOS miniaturizationBeyond CMOS: Evolutionary advances beyond CMOS, carbon Nano tubes, conventional vs. tactile computing, computing, molecular and biological computing Mole electronics-molecular Diode and diode- diode logic .Defect tolerant computing,Super buffers, Bi-CMOS and Steering Logic: Introduction, RC delay lines, super buffers- An NMOS super buffer, tri state super buffer and pad drivers, CMOS super buffers, Dynamic ratio less inverters, large capacitive loads, pass logic, designing of transistor logic, General functional blocks - NMOS and CMOS functional blocks.

MODULE – III (16 hours)Special circuit layouts and technology mapping: Introduction, Talley circuits, NAND-NAND, NORNOR, and AOI Logic, NMOS, CMOS Multiplexers, Barrel shifter, Wire routing and module lay out.System design: CMOS design methods, structured design methods, Strategies encompassinghierarchy, regularity, modularity & locality, CMOS Chip design Options, programmable logic,Programmable inter connect, programmable structure, Gate arrays standard cell approach, Fullcustom Design.Text Books:1. Wayne Wolf, Modern VLSI Design, Pearson Education, 2005 Third Edition.2. Kevin F. Brennan, Introduction to Semiconductor Devices, Cambridge University Press, 2005Recommended Reading:1. Eugene D Fabricius “Introduction to VLSI design”, McGraw-Hill International Publications, 19902. Michael Smith, Application Specific Integrated Circuit, Addison-Wesley, 1997, ISBN:0201500221

VDPE 1201 Analogue and Mixed-Signal Testing (3 – 1 – 0)MODULE – I (16 hours)Overview of Mixed-Signal Testing – Mixed-signal circuits, Test and diagnostic equipments, Mixedsignal testing challenges, The Test Specification Process – Device datasheets, Generation of test plan, Components of a test program, DC and Parametric Measurements – Continuity, Leakage currents, Power supply currents, DC references and regulators, Impedance measurements, DC offset measurements, DC gain measurements, DC power supply rejection

ratio, DC common-mode rejection ratio, Comparator DC tests, Voltage search techniques, DC tests for digital circuits, Measurement Accuracy – Terminology, Calibration and checkers, Dealing with measurement errors, Basic data analysis, Tester Hardware – Mixed-signal tester overview, DC resources, Digital subsystem, AC source and measurement, Time measurement system, Computing hardware.

MODULE – II (16 hours)

Sampling Theory – Analog measurements using DSP, Sampling and reconstruction, Repetitivesample sets, Synchronisation of smpling systems, DSP-Based Testing – Advantages of DSP-based testing, Digital signal processing, Discrete-time transforms, The inverse FFT, Analog Channel Testing– Overview, Gain and level tests, Phase tests, Distortion tests, Signal rejection tests, Noise tests,Simulation of analog channel tests, Sampled Channel Testing – Overview, Sampling considerations, Encoding and decoding, Sampled channel tests, Focused Calibrations –Overview, DC calibrations,AC amplitude calibrations, Other Ac calibrations, Error cancellation techniques.

MODULE – III (12 hours)

DAC Testing – Basics of converter testing – intrinsic parameters versus transmission parameters,Comparison of DACs and ADCs, DAC failure mechanism, Basic DC tests, Transfer curve tests,Dynamic DAC tests, DAC architecture – Resistive divider DACs, Binary-weighted DACs, PWM DACs, Sigma-delta DACs, Companded DACs, Hybrid DAC architecture, Tests for common DAC applications– DC references, Audio reconstruction, Data modulation, Video signal generators, ADC Testing – ADC testing versus DAC testing, ADC code edge measurements –Edge code testing versus center code testing, Step search and binary search methods, Servo methods, Linear ramp histogram method, conversion from histograms to code edge transfer curves, Accuracy limitations of histogram testing, Rising ramps versus falling ramps, sinusoidal histogram method, DC tests and transfer curve tests, Dynamic ADC tests, ADC architecture –Successive approximation architecture, Intgrating ADCs (Dual slope and single slope), Flash ADCs, Semiflash ADCs, PDM (sigma-delta) ADCs, Test for common ADC applications – DC measurements, Audio digitization, Data transmission, Video digitization, DIB Design – DIB basics, Printed circuit boards, DIB traces, shields and guards, Transmission lines, Grounding and power distribution, BIB components, Common DIB circuits, Common DIB mistakes, Design for Test (DfT) – Overview of DfT and BIST, Advantages of DfT, Digital scan, Digital BIST, Digital DfT for mixed-signal circuits, Mixed-signal boundary scan and BIST, Adhoc mixed-signal DfT, Subtle forms of analog DfT, IDDQ testing.

Text Books:

1. Mark Burns and Gordon W. Roberts, An Introduction to Mixed-Signal IC Test andMeasurement, Oxford University Press, 2001, ISBN: ISBN-10: 0195699262, ISBN-13: 9780195699265

Recommended Reading:

1. Bapiraju Vinnakota, Analog and Mixed-Signal Test, Prentice Hall PTR, 1998, ISBN-10: 0137863101, ISBN-13: 978-0137863105

2. Prithviraj Kabisatpathy, Alok Barua, Satyabroto Sinha, Fault Diagnosis of AnalogIntegrated Circuits, Springer, 2005, ISBN: 0-387-25742-X. 2. José Luis Huertas, Edited, Test and Design-for-Testability in Mixed-Signal IntegratedCircuits, Kluwer Academic Publishers, 2004, ISBN: 1-4020-7724-6.

HDL & High Level Synthesis (L-T-P:3 – 1 – 0)[VDPE 1202]

Module-I (16 hrs)Introduction:DesignTools:CAD Tool Taxonomy, Editors, Simulators, Simulation System, Simulation Aids, Applications of Simulation, Synthesis Tools, and Introduction to Hardware description languages (HDL), Basics of logic circuit and Boolean algebra.Basic Features of VHDL:Introduction to VHDL - Major Language Constructs, Lexical Description, VHDL Source File, Advanced Features of VHDL, The Formal Nature of VHDL, VHDL 93, Data Types, Data Objects, component, function, package, sub-circuit, concurrent assignment statements, sequential assignment statements, Modelling Combinational and Sequential Logic circuits.

** Instructor will choose only one: HDL language either VHDL or Verilog HDL.

Verilog HDL: Introduction to Verilog HDL, different levels of modeling, basic concepts, Verilog primitives, keywords, operators, data types, Verilog modules and ports; Structural modeling: gate type, design hierarchy, gate delay, propagation delay, logic simulation, design verification and testing, testbench writing; Dataflow-level modeling: continuous assignments, operators and operands, operator types, examples; Behavioral modeling.Module-II (16 hrs) Combinational Logic Circuit Design: Synthesis of combinational circuits, initial design and optimization, encoder, decoder, de-multiplexer circuits, multiplexer circuits and their implementation using VHDL/Verilog, Design of a 4-bit comparator, Design of a 32-bit ALU and a simple processor using VHDL/Verilog.Sequential Logic Circuit Design: Synthesis of sequential circuits, Study of synchronous and asynchronous sequential circuits, Flip flops, Registers, Counters and their design using VHDL/Verilog.Basic concepts of high-level synthesis: partitioning, scheduling, allocation and binding. Technology mapping and Static Timing Analysis.Module-III (16 hrs) State Machine: State Diagram, State Table, State Assignment Table, Finite state machines (FSM), VHDL/Verilog code for Moore type FSM, Serial adder design using FSM, FSM as an Arbiter circuitASICs and the ASIC Design Process: What is an ASIC?, ASIC Circuit Technology, Types of ASICs, The ASIC Design Process, FPGA, FPGA VS ASIC, FPGA Synthesis.

Testing: Logic simulation, fault sources and models, fault simulation, testing process, combinational and sequential circuit testing, testing for stuck at fault, fault simulation, BIST, JTAG.Text Books:1. James R. Armstrong and F. Gail Gray, VHDL Design Representation and Synthesis, Prentice Hall, 2000.2. Fundamentals of Digital Logic with VHDL Design – by Stephen Brown, Tata McGraw Hill, 2002, ISBN: 007047432X.3. Circuit Design with VHDL – by V A Pedroni, Prentice Hall of India Pvt. Ltd., 2005 Edition, ISBN: 8120326830.4. Verilog HDL: A Guide to Digital Design and Synthesis; Samir Palnitkar; 2nd edition, Pearson Education,2011.5. Verilog Digital System Design; Zainalabedin Navabi; 2nd edition, TMH,2012.Reference Books:1. VHDL Programming by example- Perry TMH.2. A VHDL Primer; J. Bhasker; 3rd edition, Pearson ,20023. Verilog HDL Synthesis: A Practical Primer; J. Bhasker;, BSP Publishers, 2008.4. FPGA-Based System Design, Wayne Wolf, 1st edition, Pearson.5. Advanced Digital Design with the Verilog HDL; Michael D. Ciletti; 2009,1st edition,

PHI,20106. K.C.Chang, Digital System Design with VHDL and Synthesis: An Integrated Approach,

Wiley India Pvt. Ltd, New Delhi.

VLSI And MEMS Packaging (L-T-P:3-1-0)[VDPE 1203]

MODULE – I (16 hrs)Introduction: Basics of Electronic Packaging, Packaging Hierarchy in Electronic Systems, Functionsof PackagingElectric Considerations for Electronic Packaging: Electric Field Interference, Magnetic FieldInterference, Noise performance due to passive components - Cabling, Shielding and Grounding/filtering/shielding/screening and surge protection/suppression, noise suppressionThermal Considerations for Electronic Packaging: Heat generation and modes of heat transfer inelectronic components and packages, Selection/Design of Heat Sinks, Ventilation, Forced cooling, Heat pipes for electronic cooling applications, Cooling of power intensive componentsIC Packaging: Integrated Circuit Packages, Solder bumps, Direct Chip Attach, Multi-chip modules.

MODULE – II (16 hrs)

IC Packaging (Continued): Micro via technology, LTCCTesting and Reliability of Electronic Packages: Design for Test, Adhesive and Its

Application,Thermal Management, Testing and Inspection, Package/Enclosure, Electronics Package Reliability and Failure Analysis, Product Safety and Third-Party CertificationPCB Fabrication and Design: PCB technology trends, multi-layer boards, Design CAD tool for PCBdesign, artwork and layout, general rules, design rules for PCB’s for digital circuits, high frequency, analog and mixed signal circuits, power and microwave applications, Surface mount Technology

MODULE – III (16 hrs)

Hybrid Electronic Packaging: Advantages of Hybrid packaging, Hybrid Fabrication Technology:Screen printing, conducting, resistive, dielectric and solder pastes, drying and firing, Hybrid assembliesMEMS Packaging: MEMS Packaging Issues, Die Level Packaging, Wafer Level Packaging, Microassembled caps, Sealing

Text Books:1. Glenn R. Blackwell, The Electronic Packaging Handbook, CRC Press, 2000, ISBN

08493859112. John H. Lau, Electronic Packaging: Design, Materials, Process, and Reliability

McGraw-Hill, 1998, ISBN 0070371350 Reference Books:

1. Clyde F. Coombs, Printed Circuits Handbook, McGraw-Hill, 2001, ISBN 0071350160 2. Rao R. Tummala, Eugene J. Rymaszewski, Alan G. Klopfenstein, (Eds),

MicroelectronicsPackaging Handbook: Technology Drivers, Vol. 1, Kluwer Academic Publishers, SecondEdition, January 1997, ISBN: 0412084317

3. Rao R. Tummala, Eugene J. Rymaszewski, Alan G. Klopfenstein, (Eds), MicroelectronicsPackaging Handbook: Semiconductor Packaging, Vol. 2, Kluwer Academic Publishers,Second Edition, January 1997, ISBN: 0412084414

4. Rao R. Tummala, Eugene J. Rymaszewski, Alan G. Klopfenstein, (Eds), MicroelectronicsPackaging Handbook: Technology, Vol. 3, Kluwer Academic Publishers, Second Edition,January 1997, ISBN: 0412084511 PCB Design & Technology- Waller C. Bosshart, Tata McGraw-Hill

MTVL1213 VLSI Subsystem Design (L-T-P: 3-1-0)

Module 1 (16 hrs)1. Modules in a simple processor: ALUs, ROMS, Registers etc.2. Some common adders: Ripple Carry, Carry Save, Carry Look-ahead adders, Carry Skip adders, Carry Select adders, Manchester Carry chains.3. Multipliers: Parallel Multipliers: Braun Multipliers, Baugh Wooley Multipliers, modified Booths algorithms, Carry Save Multiplier, Tree multipliers. Serial multiplication.

Module 2 (16 hrs)4. Shifter, ALU, comparator, parity generator, Zero/One detector, counter, LFSR design5. Control path design: FSM, PLA

6. Memory Cells and Arrays: SRAM, DRAM, ROM, Serial Access Memory, Content Addressable Memory etc.

Module 3 (16 hrs)7. Clock Distribution and clock skews, 2-phase clock based module designs.8. Floor planning and layout, Impact of long lines.9. Power and testability considerations in chip design8. Low power design issues

Books1. Digital Integrated Circuits: A Design Perspecive, J. M. Rabaey, Anantha

Chandrakasan and Borivoje Nikolic, PHI/Pearson2. CMOS VLSI Design: A circuits and Systems Perspective, West, Harris and

Banerjee, Pearson.3. CMOS Digital Integrated Circuits, Sung-Mo Kang and Yusuf Leblebici, third edition,

TMH 4. Principles of CMOS VLSI Design: A System Perspective, Pearson, Weste and

Eshraghaian 5. Journal papers

VLSI Design Lab-II (L-T-P 0-0-3) [MTVL 1214]

Following experiments will be carried out using Xilinx ISE simulator/Vivado and FPGA Kit:1. Design, simulation and synthesis of Combinational circuit in gate-level2. Design, simulation and synthesis of combinational circuits in dataflow and behavioral

level3. Simulation of sequential circuits: flip-flops and their conversions4. Simulation of sequential circuits: Shift registers and counters5. Design of accumulator and memory6. Finite State Machine design and simulation: sequence detector using Mealy and Moore

model7. Implementation in FPGA8. Global Timing Constraint Lab9. Synthesis Techniques Lab10. Core Generator System Lab11. Chipscope Debug Lab12. Design of a simple Microprocessor Data Path and Control Path

Third semesterLow Power VLSI Design (L-T-P:3-1-0)

[MTVD 2101]

Module-1 (16 hrs)

DEVICE & TECHNOLOGY IMPACT ON LOW POWERNeed for low power VLSI chips, Sources of power dissipation on Digital Integrated circuits. Emerging Low power approaches. Physics of power dissipation in CMOS devices.Dynamic dissipation in CMOS, Transistor sizing & gate oxide thickness, Impact of technology Scaling, Technology & Device innovation.SIMULATION POWER ANALYSIS AND PROBABILISTIC POWER ANALYSIS SPICE circuitsimulators, gate level logic simulation, capacitive power estimation, static state power, gate level capacitance estimation,

Module-2 (16 hrs)

Architecture level analysis, data correlation analysis in DSP systems. Monte Carlo simulation - Random logic signals, probability & frequency, probabilistic power analysis techniques, signal entropy.LOW POWER DESIGNCircuit level: Power consumption in circuits. Flip Flops & Latches design, high capacitance nodes,low power digital cells library.Logic level: Gate reorganization, signal gating, logic encoding, state machine encoding, precomputation logic

Module-3 (16 hrs)

LOW POWER ARCHITECTURE & SYSTEMS, LOW POWER CLOCK DISTRIBUTIONPower & performance management, switching activity reduction, parallel architecture with voltage reduction, flow graph transformation, low power arithmetic components, low power memory design- Power dissipation in clock distribution, single driver Vs distributed buffers, Zero skew Vs tolerable skew,chip and package co-design of clock networkALGORITHM AND ARCHITECTURAL LEVEL METHODOLOGIESIntroduction, design flow, algorithmic level analysis and optimization, Architectural level estimation and synthesis.

REFERENCES:

1. Gary K. Yeap, Farid N. Najm, “Low power VLSI design and technology”, World Scientific Publishing Ltd., 1996.

2. DimitriosSoudris, Christian Piguet, Costas Goutis,” Designing CMOS circuits for low power”,Kluwer Academic Publishers,2002

3. Kaushik Roy and Sharat C. Prasad,"Low-Power CMOS VLSI Circuit Design" ,Wiley-

Interscience, 2000. 4. Chandrakasan, R. Brodersen , “CMOS Low Power Digital Design”, Kluwer Academic

Publications. 1995. 5. Rabaey, M. Pedram, “Low Power Design Methodologies”, Kluwer Academic

Publications. 1996. 6. Christian Piguet, “Low-power CMOS circuits: technology, logic design and CAD tools”,

CRC Press, Taylor & Francis Group, 2006

MTVL 2111 High Speed Digital VLSI Design (L-T-P 3-1-0 4)Module-1(16 hrs)High speed adders: Carry select adder, square root carry select adder, Manchester carry-chain, carry bypass adder, carry-save adder, Kogge-Stone adder and others. Multipliers: array multiplier, carry save multiplier, Wallace tree multiplier, Dada tree adder, Booth’s multiplier and others; compressors, delay optimization of adders and multipliers, barrel and logarithmic shifters, area-time tradeoff, power consumption issues, Optimization for speed, low-power design, high-speed logic.Module-2 (16 hrs)PLA, personality matrix of a PLA, PLA folding, extended personality matrix, multilevel minimization, multilevel synthesis, Weinberger array. Design automation tools, partitioning: constructive and iterative partitioning, Karnighan-Lin algorithm, ratio-cut algorithm, placement, floor planning, pin assignments, global routing, Lee’s algorithm, detailed routing, channel routing, clock and power routing algorithms.Module-3 (16 hrs)

Clocking and interconnect issues, vias, crosstalk, system noise, complexity management, Signal integrity issues, High speed interconnects. Clock, clock skew, clock distribution and routing, clock buffering, gated clock and clock tree. Design of buffers and I/O Pad.

Books6. Digital Integrated Circuits: A Design Perspecive, J. M. Rabaey, Anantha

Chandrakasan and Borivoje Nikolic, PHI/Pearson7. CMOS VLSI Design: A circuits and Systems Perspective, West, Harris and

Banerjee, Pearson.8. CMOS Digital Integrated Circuits, Sung-Mo Kang and Yusuf Leblebici, third edition,

TMH 9. Principles of CMOS VLSI Design: A System Perspective, Pearson, Weste and

Eshraghaian 10. Journal papers

Embedded Systems Design (L-T-P:3-1-0)[MTVD 2102]

Module I (16 hrs) Introduction: An Embedded system, Processor in the system, Other hardware units, Software embedded into a system, Exemplary Embedded System-on-Chip (SOC) and VLSI circuit Devices and Device Drivers: I/O Devices, Timer and counting Devices, Serial communication using IC, CAN and advanced I/O buses between the networked multiple devices, Host system or computer parallel communication between networked I/O multiple devices using ISA, PCI, PCI-X and advanced buses, Device Drivers, Parallel port device drivers in a system, Serial port device drivers in a system, Interrupt servicing (Handling) mechanism

Module II (16 hrs)

Software and Programming Concepts: Processor selection for an embedded system, memory selection for an embedded system, Embedded programming in C++, Embedded programming in JAVA, Unified modeling language (UML), Multiple processes and application, Problem of sharing data by multiple tasks and routines, Inter process communication Real Time Operating System: Operating system services, I/O subsystem, Network operating system, Real time and embedded system, Need of well tested and debugged Real time operating system (RTOS), Introduction to C/OS-II Case Studies of Programming with RTOS: Automatic Vending machine, Adaptive Cruise Control System for a Car, Smart Card

Module III (16 hrs)

Hardware and Software Co-design: Embedded system project management, embedded system design and co-design issues in system development process, Design cycle in development phase for an embedded system, Use of software tools for development of an embedded system, Issues in embedded system design

Text Books: 1. Embedded Systems – Architecture, Programming and Design - by Raj Kamal, Tata McGraw Hill, 2003, ISBN:00704947032. Languages for Digital Embedded Systems - by Stephen A. Edwards, Kluwer, 2000, ISBN:.

Reference Books: 1. Embedded Microprocessor Systems: Real World Design- by Stuart R. Ball, Butterworth-Heinemann Publishers, 3rd Edition, 2002, ISBN:0750675349.

2. The Art of Programming Embedded Systems - by Jack G. Ganssle, Academic Press, 1992, ISBN:0122748808

Soft Computing And Its Application To Engineering Research (L-T-P:3-1-0) [MTVD 2103]

Module I (16 hrs)Fundamental Concepts: Introduction to Artificial Neural Networks (ANN). Learning Process: error–correction learning, Hebbian learning, competitive learning, Boltzmann learning, the credit- assignment problem, supervised learning, and other learning techniques. Single neuron/ Perceptron networks: training methodology, typical application to linearly separable problems.

Module II (16 hrs)Multilayer Perceptron: Back propagation algorithm, virtues and limitation of BP algorithm, modifications to back-propagation. Radial-basis function Networks – interpolation problem, Covers theorem, regularization networks, applications. Recurrent Networks.Introduction to Fuzzy systems, Membership function, Fuzzy relational operati on, fuzzy IF THEN rules, Sugeno and Mamdani type systems, Adaptive Neuro -Fuzzy Sytems, Training Methods

Module III (16 hrs)Application of ANN and Fuzzy Systems To Non-Stationary Time Series Prediction; Pattern Classification; Control; Communication Engineering; System Identification And Pattern Classification. ANN modeling of devices and circuits.

Text Books:1. S. Haykin, Neural Networks - A Comprehensive Foundation; Pearson Education, India (The

book is also published by Prentice Hall of India), 200. 2. Martin T. Hagan, Howard B. Demuth, Mark H. Beale; Neural Network Design; (ISBN: 0 -

9717321-0-8); Thomson 20023. Jang, Sun and Mizutani; Neuro-Fuzzy and Soft-Computing – A computational approach to

learning and machine intelligence; Prentice Hall of India

Reference Books:1. Satish Kumar; Neural Networks: A Classroom approach, Tata McGraw Hill, 2004, ISBN:

9780070482920