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Department of Electronics and Communication Engineering, VBITDepartment of Electronics and Communication Engineering, VBIT

UNIT - IV

SUBSYSTEM DESIGN

P.VIDYA SAGAR ( ASSOCIATE PROFESSOR)

VLSI


CONTENTS

DATA PATH SUBSYSTEMS: Subsystem Design, Shifters, Adders, ALUs, Multipliers,

Parity generators, Comparators, Zero/One Detectors, Counters.

ARRAY SUBSYSTEMS:

SRAM, DRAM, ROM, Serial Access Memories, Content Addressable Memory.

2VIDYA SAGAR P

Department of Electronics and Communication Engineering, VBIT

Outline

UNIT IV

DATA PATH SUBSYSTEMS

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Shifters, Adders

ALUs

Multipliers

Parity generators

Comparators

Zero/One Detectors

Counters


Multiplication

– Example:

– M x N-bit multiplication

– Produce N M-bit partial products

– Sum these to produce M+N-bit product

1100 : 1210

0101 : 510

1100

0000

1100

0000

00111100 : 6010

multiplier

multiplicand

partial

products

product

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General Form

– Multiplicand: Y = (yM-1, yM-2, …, y1, y0)

– Multiplier: X = (xN-1, xN-2, …, x1, x0)

– Product:1 1 1 1

0 0 0 0

2 2 2M N N M

j i i j

j i i j

j i i j

P y x x y

x0y

5x

0y

4x

0y

3x

0y

2x

0y

1x

0y

0

y5

y4

y3

y2

y1

y0

x5

x4

x3

x2

x1

x0

x1y

5x

1y

4x

1y

3x

1y

2x

1y

1x

1y

0

x2y

5x

2y

4x

2y

3x

2y

2x

2y

1x

2y

0

x3y

5x

3y

4x

3y

3x

3y

2x

3y

1x

3y

0

x4y

5x

4y

4x

4y

3x

4y

2x

4y

1x

4y

0

x5y

5x

5y

4x

5y

3x

5y

2x

5y

1x

5y

0

p0

p1

p2

p3

p4

p5

p6

p7

p8

p9

p10

p11

multiplier

multiplicand

partial

products

product

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Dot Diagram

– Each dot represents a bit

partial productsm

ultip

lier x

x0

x15

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A 4 × 4 Unsigned Array Multiplier

skew array

for rectangular

layout

X3 X2 X1 X0

× Y3 Y2 Y1 Y0

X3Y0 X2Y0 X1Y0 X0Y0

X3Y1 X2Y1 X1Y1 X0Y1

X3Y2 X2Y2 X1Y2 X0Y2

X3Y3 X2Y3 X1Y3 X0Y3

P7 P6 P5 P4 P3 P2 P1 P0

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Array Multiplier

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Array Multiplier y0

y1

y2

y3

x0

x1

x2

x3

p0

p1

p2

p3

p4

p5

p6

p7

B

ASin Cin

SoutCout

BA

CinCout

Sout

Sin

=

CSA

Array

CPA

critical path BA

Sout

Cout CinCout

Sout

=Cin

BA

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Rectangular Array

– Squash array to fit rectangular floorplan

y0

y1

y2

y3

x0

x1

x2

x3

p0

p1

p2

p3

p4

p5

p6

p7

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Department of Electronics and Communication Engineering, VBITDepartment of Electronics and Communication Engineering, VBIT11VIDYA SAGAR P


Wallace Tree

– Reduces the number of partial products

– Built from carry-save adders:

– Three inputs: a, b, c

– Two outputs: y, z such that y + z = a + b + c

– Carry-save equations:

– yi = ai bi ci

– zi+1 = aibi + bici + ciai

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Wallace Tree Structure

FA FA FA

a2 b2 c2a1 b1

c1 a0 b0 c0

s0s1s2

carry-ripple

adder

FA FA FA

a2 b2 c2a1 b1

c1 a0 b0 c0

y0

carry-save

adder

z1y1z2y2z3

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Wallace Tree Operation

– n additions are reduced to (2n/3) additions after each level

– Sum of inputs = Sum of outputs

– Can apply the reduction hierarchically

– More efficient design uses 4-2 adders to reduce n additions to (n/2) additions after each

level

– Need final adder to add the last two numbers

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Signed Multiplication

– Signed number representation

–

– Signed n×n multiplication

– (1110)2 × (0011)2 = (1010)2 (-2) × 3 = (-6)

– No difference from unsigned multiplication if the result has the same bit-width as the

input

– But what if we want the result to be 2n bit?

– Use sign-bit extension

– Needs 2n × 2n array multiplier

2

0

1

1 22n

i

i

i

n

n xxX

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Baugh-Wooley Multiplier: Principle

2

0

1

11

2

0

2

0

22

11 2)(22n

i

ni

inin

n

i

n

j

ji

ji

n

nn xyyxyxyxXY

ii xx 1 ii yy 1

1

11

22

1111 2)(2)( n

nn

n

nnnn yxyxyxX Y

2

0

1

11

2

0

2

0

2)(2n

i

ni

inin

n

i

n

j

ji

ji xyyxyx

1

11

22

1111

12 2)(2)(2 n

nn

n

nnnn

n yxyxyxX Y

2

0

1

11

2

0

2

0

2)(2n

i

ni

inin

n

i

n

j

ji

ji xyyxyx

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Two’s Complement Array Multiplication

Modified Baugh-Wooley two’s complement

multiplier

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Baugh-Wooley Multiplier: Structure

+

a

b

Cin

Cout Sum

x3

+ x0y1

x0y2

P1+

x0y0

x0y3+

y3+

+

0

x1y1

x1y2+

x1y0

x1y3+

+

P2

P3P4

0

P0+

0

x2y1

x2y2+

x2y0

x2y3+

+

x3y1

x3y2

x3y0

P5P6P7

1

y3

x3y3+

+ +

x3

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Fewer Partial Products

– Array multiplier requires N partial products

– If we looked at groups of r bits, we could form N/r partial products.

– Faster and smaller?

– Called radix-2r encoding

– Ex: r = 2: look at pairs of bits

– Form partial products of 0, Y, 2Y, 3Y

– First three are easy, but 3Y requires adder

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Booth Multiplier

– Utilize Booth encoding scheme

– Booth encoding scheme

Handles signed multiplication

Reduce the number of partial products by half

Small area and fast

Encoding scheme cannot be applied hierarchically

– Often used as the first stage partial products reduction

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Booth Encoding: Principle

– Two’s-complement form of multiplier y

–

–

– Consider first two terms

–

– By looking at three bits of y, we can determine whether to add x, 2x to partial

product.

...222 3

3

2

2

1

1

n

n

n

n

n

n yyyY

. . .2)(2)(2)( 3

34

2

23

1

12

n

nn

n

nn

n

nn yyyyyyY

. . .2)2(2)2( 4

543

2

321

n

nnn

n

nnn XyyyXyyyX Y

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Booth Encoding

– Instead of 3Y, try –Y, then increment next partial product to add 4Y

– Similarly, for 2Y, try –2Y + 4Y in next partial product

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Booth Hardware

– Booth encoder generates control lines for each PP

– Booth selectors choose PP bits

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Sign Extension

– Partial products can be negative

– Require sign extension, which is cumbersome

– High fanout on most significant bit

mu

ltiplie

r x

x0

x15

0

00

x-1

x16

x17

ssssssssssssssss

ssssssssssssss

ssssssssssss

ssssssssss

ssssssss

ssssss

ssss

ss

PP0

PP1

PP2

PP3

PP4

PP5

PP6

PP7

PP8

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To begin

– When using Booth's Algorithm:

– You will need twice as many bits in your product as you

have in your original two operands.

– Decide which operand will be the multiplier and which will be the multiplicand

– Convert both operands to two's complement representation using X bits

– X must be at least one more bit than is required for the binary representation of the

numerically larger operand

– Begin with a product that consists of the multiplier with an additional X leading zero bits

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Example

– In the week by week, there is an example of multiplying 2 x (-5)

– For our example, let's reverse the operation, and multiply (-5) x 2

– The numerically larger operand (5) would require 3 bits to represent in binary (101). So

we must use AT LEAST 4 bits to represent the operands, to allow for the sign bit.

– Let's use 5-bit 2's complement:

– -5 is 11011 (multiplier)

– 2 is 00010 (multiplicand)

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Beginning Product

– The multiplier is:

11011

– Add 5 leading zeros to the multiplier to get the beginning product:

00000 11011

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Step 1 for each pass

– Use the LSB (least significant bit) and the previous LSB to

determine the arithmetic action.

– If it is the FIRST pass, use0 as the previous LSB.

– Possible arithmetic actions:

– 00 no arithmetic operation

– 01 add multiplicand to left half of product

– 10 subtract multiplicand from left half of product

– 11 no arithmetic operation

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Step 2 for each pass

– Perform an arithmetic right shift (ASR) on the entire product.

– NOTE: For X-bit operands, Booth's algorithm requires X

passes.

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Example

– Let's continue with our example of multiplying (-5) x 2

– Remember:

– -5 is 11011 (multiplier)

– 2 is 00010 (multiplicand)

– And we added 5 leading zeros to the multiplier to get the beginning product:

00000 11011

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Example continued

– Initial Product and previous LSB

00000 11011 0

(Note: Since this is the first pass, we use 0 for the previous LSB)

– Pass 1, Step 1: Examine the last 2 bits

00000 11011 0

The last two bits are 10, so we need to:

subtract the multiplicand from left half of product

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Example: Pass 1 continued

– Pass 1, Step 1: Arithmetic action

(1) 00000 (left half of product)

-00010 (mulitplicand)

11110 (uses a phantom borrow)

– Place result into left half of product

11110 11011 0

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– Pass 1, Step 2: ASR (arithmetic shift right)

– Before ASR

11110 11011 0

– After ASR

11111 01101 1

(left-most bit was 1, so a 1 was shifted in on the left)

– Pass 1 is complete.

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Example: Pass 2

– Current Product and previous LSB

11111 01101 1


11111 01101 1

The last two bits are 11, so we do NOT need to perform an arithmetic action --

just proceed to step 2.

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– Before ASR

11111 01101 1

– After ASR

11111 10110 1



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Example: Pass 3


11111 10110 1


11111 10110 1


add the multiplicand to the left half of the product

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+00010 (mulitplicand)

00001 (drop the leftmost carry)


00001 10110 1

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– Before ASR

00001 10110 1

– After ASR

00000 11011 0



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Example: Pass 4


00000 11011 0


00000 11011 0


subtract the multiplicand from the left half of the product

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-00010 (mulitplicand)

11110 (uses a phantom borrow)


11110 11011 0

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– Before ASR

11110 11011 0

– After ASR

11111 01101 1



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Example: Pass 5


11111 01101 1


11111 01101 1

The last two bits are 11, so we do NOT need to perform an arithmetic action --

just proceed to step 2.

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– Before ASR

11111 01101 1

– After ASR

11111 10110 1



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Final Product

– We have completed 5 passes on the 5-bit operands, so we are done.

– Dropping the previous LSB, the resulting final product is:

11111 10110

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Verification

– To confirm we have the correct answer, convert the 2's complement final product back to

decimal.

– Final product: 11111 10110

– Decimal value: -10which is the CORRECT product of:

(-5) x 2

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Comparators

0’s detector: A = 00…000

1’s detector: A = 11…111

Equality comparator: A = B

Magnitude comparator: A < B

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1’s & 0’s Detectors

1’s detector: N-input AND gate

0’s detector: NOTs + 1’s detector (N-input NOR)

A0

A1

A2

A3

A4

A5

A6

A7

allones

A0

A1

A2

A3

allzeros

allones

A1

A2

A3

A4

A5

A6

A7

A0

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Equality Comparator

Check if each bit is equal (XNOR, aka equality gate)

1’s detect on bitwise equality

A[0]B[0]

A = B

A[1]B[1]

A[2]B[2]

A[3]B[3]

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Magnitude Comparator

Compute B – A and look at sign

B – A = B + ~A + 1

For unsigned numbers, carry out is sign bit

A0

B0

A1

B1

A2

B2

A3

B3

A = BZ

C

A B

N A B

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Signed vs. Unsigned

For signed numbers, comparison is

harder

C: carry out

Z: zero (all bits of B – A are 0)

N: negative (MSB of result)

V: overflow (inputs had different signs,

output sign B)

S: N xor V (sign of result)

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Shifters

Logical Shift:

Shifts number left or right and fills with 0’s

1011 LSR 1 = 0101 1011 LSL1 = 0110

Arithmetic Shift:

Shifts number left or right. Rt shift sign extends

1011 ASR1 = 1101 1011 ASL1 = 0110

Rotate:

Shifts number left or right and fills with lost bits

1011 ROR1 = 1101 1011 ROL1 = 0111

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Funnel Shifter

A funnel shifter can do all six types of shifts

Selects N-bit field Y from 2N–1-bit input

Shift by k bits (0 k < N)

Logically involves N N:1 multiplexers

Is the most general kind of shifter

Can do all the other shifts.

Concatenates two n-bit words together and then

selects any contiguous n-bit subfield.

If A=B get a barrel shifter

If A = sign bit, get arithmetic shifts

And it does byte inserts too.

Can implement this shifter using a cross-bar switch, where the inputs are vertical and

the output are horizontal

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Funnel Shifter Operation

– Computing N-k requires an adder

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Simplified Funnel Shifter

– Optimize down to 2N-1 bit input

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Logarithmic Funnel Shifter

Log N stages of 2-input muxes

No select decoding needed

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Barrel Shifter

– Barrel shifters perform right rotations using wrap-around wires.

– Left rotations are right rotations by N – k = k + 1 bits.

– Shifts are rotations with the end bits masked off.

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4-Bit Barrel Shifter

• A rotate is a shift in which the bits shifted out are inserted into the positions vacated

• The circuit rotates its contents left from 0 to 3 positions depending on Selector S.

Note that a left rotation by three (3)

positions is the same as a right

rotation by one position in this 4 bit

barrel shifter

57


Logarithmic Barrel

Shifter

Right shift only

Right/Left shift Right/Left Shift & Rotate

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ADDERS

– Single-bit Addition

– Carry-Ripple Adder

– Carry-Skip Adder

– Carry-Lookahead Adder

– Carry-Select Adder

– Carry Save Adder

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Single-Bit Addition

Half Adder Full Adder

A B Cout S

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

A B C Cou

t

S

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

A B

S

Cout

A B

C

S

Cout

out

S A B

C A B

out ( , , )

S A B C

C MAJ A B C

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PGK

– For a full adder, define what happens to carries

(in terms of A and B)

– Generate: Cout = 1 independent of C

– G = A • B

– Propagate: Cout = C

– P = A B

– Kill: Cout = 0 independent of C

– K = ~A • ~B

62 VIDYA SAGAR P


Full Adder Design

– Brute force implementation from eqns

out ( , , )

S A B C

C MAJ A B C

ABC

S

Cout

MA

J

ABC

A

B BB

A

CS

C

CC

B BB

A A

A B

C

B

A

CBA A B C

Cout

C

A

A

BB

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Carry Propagate Adders

– N-bit adder called CPA

– Each sum bit depends on all previous carries

– How do we compute all these carries quickly?

+

BN...1

AN...1

SN...1

Cin

Cout

11111

1111

+0000

0000

A4...1

carries

B4...1

S4...1

Cin

Cout

00000

1111

+0000

1111

Cin

Cout

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Carry-Ripple Adder

– Simplest design: cascade full adders

– Critical path goes from Cin to Cout

– Design full adder to have fast carry delay

Cin

Cout

B1

A1

B2

A2

B3

A3

B4

A4

S1

S2

S3

S4

C1

C2

C3

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Generate / Propagate

– Equations often factored into G and P

– Generate and propagate for groups spanning

ci+1 = Gi + Pi.ci

si = Pi ⊕ ci

Where Gi = ai.bi

Pi = (ai⊕ bi)

0:00:00inGCP0:00:00inGCP

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PG Logic

S1

B1

A1

P1

G1

G0:0

S2

B2

P2

G2

G1:0

A2

S3

B3

A3

P3

G3

G2:0

S4

B4

P4

G4

G3:0

A4

Cin

G0

P0

1: Bitwise PG logic

2: Group PG logic

3: Sum logicC

0C

1C

2C

3

Cout

C4

67 VIDYA SAGAR P


Carry-Skip Adder

– Carry-ripple is slow through all N stages

– Carry-skip allows carry to skip over groups of n bits

– Decision based on n-bit propagate signal

Cin

+

S4:1

P4:1

A4:1

B4:1

+

S8:5

P8:5

A8:5

B8:5

+

S12:9

P12:9

A12:9

B12:9

+

S16:13

P16:13

A16:13

B16:13

Cout

C4

1

0

C8

1

0

C12

1

0

1

0

68 VIDYA SAGAR P


Carry-Select Adder

– Trick for critical paths dependent on late input X

– Precompute two possible outputs for X = 0, 1

– Select proper output when X arrives

– Carry-select adder precomputes n-bit sums

– For both possible carries into n-bit group

Cin+

A4:1

B4:1

S4:1

C4

+

+

01

A8:5

B8:5

S8:5

C8

+

+

01

A12:9

B12:9

S12:9

C12

+

+

01

A16:13

B16:13

S16:13

Cout

0

1

0

1

0

1

70 VIDYA SAGAR P


Carry Save Addition

– The carry-save adder block is the same circuit as the full adder

The name “carry-save” arises from the fact that we save the carry-out word instead

using it immediately to calculate a final sum.

Z4

Y4

X4

S4

C4

Z3

Y3

X3

S3

C3

Z2

Y2

X2

S2

C2

Z1

Y1

X1

S1

C1

XN...1

YN...1

ZN...1

SN...1

CN...1

n-bit CSA

71 VIDYA SAGAR P


Counters

Counters can be implemented using the adder/subtractor circuits and registers (or

equivalently, D flip-flops)

The simplest counter circuits can be built using T flip-flops because the toggle feature is

naturally suited for the implementation of the counting operation. Counters are available in

two categories.

1.Asynchronous(Ripple counters) Asynchronous counters, also known as ripple counters,

are not clocked by a common pulse and hence every ip- op in the counter changes at

different times.

EX:- Binary ripple counters, BCD ripple counters

2.Synchronous counters A synchronous counter however, has an internal clock, and the

external event is used to produce a pulse which is synchronized with this internal clock.

E.X.:- Binary counter, Up-down Binary counter, BCD Binary counter, Ring counter, Johnson

Counter.

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A 3-bit up-counter.

A 3-bit down-counter

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A 4bit synchronous up counter

synchronous counter using adders and registers

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A linear-feedback shift register (LFSR) consists of N registers configured as a shift register.The input to the shift register comes from the XOR of particular bits of the register, asshown in Figure for a 3-bit LFSR. On reset, the registers must be initialized to anonzero value (e.g., all 1s). The pattern of outputs for the LFSR is shown in Table

Linear-Feedback Shift Registers

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Array Sub Systems

76

SRAM

DRAM

ROM

Serial Access Memories

Content Addressable Memory

VIDYA SAGAR P

Department of Electronics and Communication Engineering, VBIT VIDYA SAGAR P77

Memory Arrays

Random Access Memory Serial Access Memory Content Addressable Memory

(CAM)

Read/Write Memory

(RAM)

(Volatile)

Read Only Memory

(ROM)

(Nonvolatile)

Static RAM

(SRAM)

Dynamic RAM

(DRAM)

Shift Registers Queues

First In

First Out

(FIFO)

Last In

First Out

(LIFO)

Serial In

Parallel Out

(SIPO)

Parallel In

Serial Out

(PISO)

Mask ROM Programmable

ROM

(PROM)

Erasable

Programmable

ROM

(EPROM)

Electrically

Erasable

Programmable

ROM

(EEPROM)

Flash ROM


Read Only Memory CLASSIFICATION

Mask Programmed ROMs -Data is written during chip fabrication using a photo mask

Fused ROMs -Data is written by blowing the fuse electrically, hence cannot be modified later

Programmable Read Only Memories (PROMs) :Data is written after chip fabrication

Erasable PROMs -Complete block is erased using UV light which is penetrated through glass

window

Electrically Erasable PROMs -8 bit data is erased at a time, hence slower

Flash - Programmed using high electrical voltage. Erases data in blocks hence faster

VIDYA SAGAR P78


Memory Architecture

Stores large number of bits

m x n: m words of n bits each

k = Log2(m) address input signals

or m = 2k words

e.g., 4,096 x 8 memory:

32,768 bits

12 address input signals

8 input/output data signals

Memory access

r/w: selects read or write

enable: read or write only when asserted

multiport: multiple accesses to different locations simultaneously

m × n memory

…

…

n bits per word

mw

ord

s

enable

2k × n read and write memory

A0

…

r/w

…

Q0Qn-1

Ak-1

memory external view

VIDYA SAGAR P79


Semiconductor Memory Types (Cont.)

RAM: the stored data is volatile

DRAM

A capacitor to store data, and a transistor to access the capacitor

Need refresh operation

Low cost, and high density it is used for main memory

SRAM

Consists of a latch

Don’t need the refresh operation

High speed and low power consumption it is mainly used for cache memoryand memory in hand-held devices

VIDYA SAGAR P80


ROM: “Read-Only” Memory

Nonvolatile

Can be read from but not written to, by a processor in an

microcomputer system

Traditionally written to, “programmed”, before inserting

to microcomputer system

Uses

Store software program for general-purpose processor

Store constant data (parameters) needed by system

Implement combinational circuits (e.g., decoders)

2k × n ROM

…

Q0Qn-1

A0

…

enable

Ak-1

External view

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Example: 8 x 4 ROM

Horizontal lines = words

Vertical lines = data

Lines connected only at circles

Decoder sets word 2’s line to 1 if address input is

010

Data lines Q3 and Q1 are set to 1 because there is a

“programmed” connection with word 2’s line

Word 2 is not connected with data lines Q2 and Q0

Output is 1010

8 × 4 ROM

3×8decoder

Q0Q3

A0

enable

A2

word 0word 1

A1

Q2 Q1

programmable connection

word line

data line

word 2

Internal view

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Memory – ROM

ROM Arrays

There are two basic types of ROM arrays

1) NOR-based ROM

2) NAND-based ROM

NOR-based ROM: All Column Lines are pulled-up using a PMOS transistor (or resistor)

The Row Lines are connected to the gates of NMOS transistors at the intersection of

Row and Column Lines

The presence or absence of the NMOS transistors dictates whether a 1 or a 0 is stored

If the NMOS transistor is present, it will pull down the Column Line when its gate is

driven high by the Row Line.

If the NMOS transistor is absent, the Column Line will not be pulled down,so it will remain

pulled up by the PMOS’s.

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Memory – ROM

NOR-based ROM

In order to Read from the

array, the Row line is

asserted and the desired

Column line is observed

a NOR-based ROM is

similar to a Hex Keypad

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Memory – ROM

NAND-based ROM

NAND-based ROM is a different array architecture

it uses a depletion-load NMOS as the pull-up transistor

the Column NMOS’s are connected in series with the

column lines (i.e. a NAND configuration)

If an NMOS exists in the Column line and the Row line

is asserted, the NMOS will pull the Column Line down

and represent a stored ’0’

If an NMOS is absent on the Column line and the

Row line is asserted, the Column Line will remain

pulled high by the depletion NMOS and represent

a stored ‘1’

since all of the NMOS’s are in series, in order to Read

from a Row, all other Rows much be turned ON

- this means in order to distinguish the Row we are asserting,

we write a ‘0’ to it

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Memory – ROM NAND-based ROM- In this configuration, if an NMOS is

present, it will represent a “stored 1” since in order to

address its location, the Row line is driven to a ‘0’ and the

NMOS not turned on. This leaves the Column line pulled

HIGH.

- if an NMOS is absent, it will represent a “stored 0”

since all of the other Row NMOS’s are turned on

and will pull the Column Line LOW

- this gives the opposite behavior as in a NOR-based ROM

NOR NAND

NMOS present 0 1

NMOS absent 1 0

- it also gives a complementary addressing scheme

NOR NAND

Address Row Line by driving: 1 0

All other Row Lines driven to: 0 1

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Mask-programmed ROM

Connections “programmed” at fabrication

set of masks

Lowest write ability

only once

Highest storage permanence

bits never change unless damaged

Typically used for final design of high-volume systems

spread out NRE (non-recurrent engineering) cost for

a low unit cost

VIDYA SAGAR P87

Department of Electronics and Communication Engineering, VBIT.

(d)

(a)

(b)source drain

+15V

source drain

0V

(c)source drain

floating gate

5-30 min

EPROM: Erasable programmable ROM Programmable component is a MOS transistor

Transistor has “floating” gate surrounded by an insulator

(a) Negative charges form a channel between source and drain storing

a logic 1

(b) Large positive voltage at gate causes negative charges to move out

of channel and get trapped in floating gate storing a logic 0

(c) (Erase) Shining UV rays on surface of floating-gate causes negative

charges to return to channel from floating gate restoring the logic 1

(d) An EPROM package showing quartz window through which UV

light can pass

Better write ability

can be erased and reprogrammed thousands of times

Reduced storage permanence

program lasts about 10 years but is susceptible to radiation and

electric noise,Typically used during design developmentVIDYA SAGAR P

88


Sample EPROM components

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Sample EPROM programmers

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EEPROM: Electrically erasable programmable ROM

Programmed and erased electronically

typically by using higher than normal voltage

can program and erase individual words

Better write ability

can be in-system programmable with built-in circuit to provide higher than normal voltage

built-in memory controller commonly used to hide details from memory user

writes very slow due to erasing and programming

“busy” pin indicates to processor EEPROM still writing

can be erased and programmed tens of thousands of times

Similar storage permanence to EPROM (about 10 years)

Far more convenient than EPROMs, but more expensive

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FLASH

Extension of EEPROM

Same floating gate principle

Same write ability and storage permanence

Fast erase

Large blocks of memory erased at once, rather than one word at a time

Blocks typically several thousand bytes large

Writes to single words may be slower

Entire block must be read, word updated, then entire block written back

Used with embedded microcomputer systems storing large data items in nonvolatile memory

e.g., digital cameras, MP3, cell phones

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Serial Access Memories

Serial access memories do not use an address

Shift Registers

Serial In Parallel Out (SIPO)

Parallel In Serial Out (PISO)

Queues (FIFO, LIFO)

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Shift Register

– Shift registers store and delay data

– Simple design: cascade of registers

– Watch your hold times!

clk

Din Dout8

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Serial In Parallel Out

– 1-bit shift register reads in serial data

– After N steps, presents N-bit parallel output

clk

P0 P1 P2 P3

Sin

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Parallel In Serial Out

– Load all N bits in parallel when shift = 0

– Then shift one bit out per cycle

clkshift/load

P0 P1 P2 P3

Sout

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FIFO, LIFO Queues

– First In First Out (FIFO)

– Initialize read and write pointers to first element

– Queue is EMPTY

– On write, increment write pointer

– If write almost catches read, Queue is FULL

– On read, increment read pointer

– Last In First Out (LIFO)

– Also called a stack

– Use a single stack pointer for read and write

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SRAM

bit

write

write_b

read

read_b

SRAM memory cell

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6T SRAM Cell

Cell size accounts for most of array size

Reduce cell size at expense of complexity

6T SRAM Cell

Used in most commercial chips

Data stored in cross-coupled inverters

Read:

Precharge bit, bit_b

Raise wordline

Write:

Drive data onto bit, bit_b

Raise wordline

bit bit_b

word

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SRAM Read

Precharge both bitlines high

Then turn on wordline

One of the two bitlines will be pulled down by the cell

Ex: A = 0, A_b = 1

bit discharges, bit_b stays high

But A bumps up slightly

Read stability

A must not flip

N1 >> N2

bit bit_b

N1

N2P1

A

P2

N3

N4

A_b

word

0.0

0.5

1.0

1.5

0 100 200 300 400 500 600

time (ps)

word bit

A

A_b bit_b

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SRAM Write

Drive one bitline high, the other low

Then turn on wordline

Bitlines overpower cell with new value

Ex: A = 0, A_b = 1, bit = 1, bit_b = 0

Force A_b low, then A rises high

Writability

Must overpower feedback inverter

N2 >> P1

time (ps)

word

A

A_b

bit_b

0.0

0.5

1.0

1.5

0 100 200 300 400 500 600 700

bit bit_b

N1

N2P1

A

P2

N3

N4

A_b

word

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DRAM

DRAM store their contents as charge on a capacitor rather than in a feedback loop.

The cell must be periodically read and refreshed so that its contents do not leak away.

Like SRAM accessed by asserting wordline to connect the capacitor to the bitline.

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DRAM READ

On read the bitline is precharged to Vdd/2.

When wordline rises the capacitor shares its charge with the bitline causing a voltage

change that can be sensed.

some DRAMs drive the wordline to Vddp=Vdd+Vt to avoid degraded level when writing a ‘1’.

DRAM capacitor must be physically small as possible to achieve good density.

According to charge-sharing equation the voltage swing on bitline during readout is

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Content Addressable Memories

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CAMs

– Extension of ordinary memory (e.g. SRAM)

– Read and write memory as usual

– Also match to see which words contain a key

CAM

adr data/key

matchread

write

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What is CAM?

Content Addressable Memory is a special kind of memory!

Read operation in traditional memory:

Input is address location of the content that we are interested in it.

Output is the content of that address.

In CAM it is the reverse:

Input is associated with something stored in the memory.

Output is location where the associated content is stored. 1 0 1 X X

0 1 1 0 X

0 1 1 X X

1 0 0 1 1

0 1 1 0 1

0 0

0 1

1 0

1 1

0 1

Content Addressable

Memory

1 0 1 X X

0 1 1 0 X

0 1 1 X X

1 0 0 1 1

0 1

0 0

0 1

1 0

1 1

0 1 1 0 X

Traditional Memory

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Simplified CAM Block Diagram

The input to the system is the search word.

The search word is broadcast on the search lines.

Match line indicates if there were a match btw. the search and stored word.

Encoder specifies the match location.

If multiple matches, a priority encoder selects the first match.

Hit signal specifies if there is no match.

The length of the search word is long ranging from 36 to 144 bits.

Table size ranges: a few hundred to 32K.

Address space : 7 to 15 bits.

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Type of CAMs

Binary CAM (BCAM) only stores 0s and 1s

Applications: MAC table consultation. Layer 2 security related VPN

segregation.

Ternary CAM (TCAM) stores 0s, 1s and don’t cares.

Application: when we need wilds cards such as, layer 3 and 4 classification

for QoS and CoS purposes. IP routing (longest prefix matching).

Available sizes: 1Mb, 2Mb, 4.7Mb, 9.4Mb, and 18.8Mb.

CAM entries are structured as multiples of 36 bits rather than 32 bits.

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CAM Advantages

They associate the input (comparand) with their memory contents in one clock

cycle.

They are configurable in multiple formats of width and depth of search data

that allows searches to be conducted in parallel.

CAM can be cascaded to increase the size of lookup tables that they can store.

We can add new entries into their table to learn what they don’t know before.

They are one of the appropriate solutions for higher speeds.

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CAM Disadvantages

They cost several hundred of dollars per CAM even in large quantities.

They occupy a relatively large footprint on a card.

They consume excessive power.

Generic system engineering problems:

Interface with network processor.

Simultaneous table update and looking up requests.

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Thank you………………

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