chapter 1 introduction to vlsi...department of electronics and communication engineering 1 design of...

Department of Electronics and Communication Engineering

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DESIGN OF LOW POWER TRUE SINGLE-PHASE CLOCKING FLIP FLOPS

CHAPTER 1

INTRODUCTION TO VLSI

1.1 INTRODUCTION TO VLSI

Very large-scale integration (VLSI) is the process of integrating or embedding

hundreds of thousands of transistors on a single silicon semiconductor microchip. VLSI

technology was conceived in the late 1970s when advanced level computer processor

microchips were under development. The microprocessor is a VLSI device. Before the

introduction of VLSI technology, most ICs had a limited set of functions they could

perform. An electronic circuit might consist of a CPU, ROM, RAM and other glue

logic. VLSI lets IC designers add all of these into one chip.

Microprocessors are essential to many of the products we use every day such as

TVs, cars, radios, home appliances and of course, computers. Transistors are the main

components of microprocessors. At their most basic level, transistors may seem simple.

But their development actually required many years of painstaking research. Before

transistors, computers relied on slow, inefficient vacuum tubes and mechanical

switches to process information. In 1958, engineers managed to put two transistors onto

a Silicon crystal and create the first integrated circuit, which subsequently led to the

first microprocessor.

Invention of transistor was the driving factor of growth in the VLSI

Technology. Before we get to know about the VLSI Technology, let us have a basic

knowledge of Electronics evolution. Electronics deals with Circuits which involve

various active and passive components. These circuits are used in various electronic

devices and are called electronic circuits. Originally the components used in electronic

circuits like diode were made up of vacuum tubes and were called discrete components.

Later when the Solid State Device (SSD) was invented, the components were made up

of semiconductors. Vacuum tubes had the disadvantage of its size, power requirement

and reliability.

1.1.1 HISTORY OF VLSI

During the mid-1920s, several inventors attempted devices that were intended

to control current in solid-state diodes and convert them into triodes. Success had to

wait until after World War II (WWII), during which the attempt to improve silicon and

http://en.wikipedia.org/wiki/Microprocessor

http://en.wikipedia.org/wiki/Electronic_circuit

http://en.wikipedia.org/wiki/Central_processing_unit

http://en.wikipedia.org/wiki/Read-only_memory

http://en.wikipedia.org/wiki/Random_Access_Memory

http://en.wikipedia.org/wiki/Glue_logic

http://en.wikipedia.org/wiki/Glue_logic

http://www.techulator.com/articles/Electronics.aspx

http://www.techulator.com/articles/SSD.aspx


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germanium crystals for use as radar detectors led to improvements in fabrication and in

the understanding of quantum mechanical states of carriers in semiconductors. Then

scientists who had been diverted to radar development returned to solid-state device

development. With the invention of transistors at Bell Labs in 1947, the field of

electronics shifted from vacuum tubes to solid-state devices.

With the small and effect transistor at their hands, electrical engineers of the

1950s saw the possibilities of constructing far more advanced circuits. As the

complexity of circuits grew, problems arise.

One problem was the size of the circuit. A complex circuit, like a computer, was

dependent on speed. If the components of the computer were too large or the wires

interconnecting them too long, the electric signals couldn't travel fast enough through

the circuit, thus making the computer too slow to be effective.

Jack Kilby at Texas Instruments found a solution to this problem in 1958.

Kilby's idea was to make all the components and the chip out of the same block

(monolith) of semiconductor material. Kilby presented his idea to his superiors, and

was allowed to build a test version of his circuit. In September 1958, he had his first

integrated circuit ready. Although the first integrated circuit was crude and had some

problems, the idea was groundbreaking. By making all the parts out of the same block

of material and adding the metal needed to connect them as a layer on top of it, there

was no need for discrete components. No more wires and components had to be

assembled manually. The circuits could be made smaller, and the manufacturing

process could be automated. From here, the idea of integrating all components on a

single silicon wafer came into existence, which led to development in small-scale

integration (SSI) in the early 1960s, medium-scale integration (MSI) in the late 1960s,

and then large-scale integration (LSI) as well as VLSI in the 1970s and 1980s, with tens

of thousands of transistors on a single chip (later hundreds of thousands, then

millions, and now billions (109)).

1.1.2 DEVELOPMENT

The first semiconductor chips held two transistors each. Subsequent advances

added more transistors, and as a consequence, more individual functions or systems

were integrated over time. The first integrated circuits held only a few devices,

perhaps as many as ten diodes, transistors, resistors and capacitors, making it possible

http://en.wikipedia.org/wiki/Jack_Kilby

http://en.wikipedia.org/wiki/Texas_Instruments

http://en.wikipedia.org/wiki/Diode

http://en.wikipedia.org/wiki/Transistor

http://en.wikipedia.org/wiki/Resistor

http://en.wikipedia.org/wiki/Capacitor


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to fabricate one or more logic gates on a single device. Now known as small-scale

integration (SSI), improvements in this technique led to devices with hundreds of logic

gates, known as medium-scale integration (MSI). Further improvements led to large-

scale integration (LSI), i.e. systems with at least a thousand logic gates. Current

technology has moved far past this mark and today's microprocessors have many

millions of gates and billions of individual transistors.

At one time, there was an effort to name and calibrate various levels of large-

scale integration above VLSI. Terms like ultra-large-scale integration (ULSI) were

used. But the huge number of gates and transistors available on common devices has

rendered such fine distinctions moot. Terms suggesting greater than VLSI levels of

integration are no longer in widespread use.

As of early 2008, billion-transistor processors are commercially available. This

became more common place as semiconductor fabrication advanced from the then-

current generation of 65 nm processes. Current designs, unlike the earliest devices,

use extensive design automation and automated logic synthesis to layout the

transistors, enabling higher levels of complexity in the resulting logic functionality.

Certain high-performance logic blocks like the SRAM (static random-access memory)

cell, are still designed by hand to ensure the highest efficiency. VLSI technology may

be moving toward further radical miniaturization with introduction

of NEMS technology.

http://en.wikipedia.org/wiki/Logic_gate

http://en.wikipedia.org/wiki/Integrated_circuit#SSI.2C_MSI_and_LSI





http://en.wikipedia.org/wiki/Microprocessor

http://en.wikipedia.org/wiki/Integrated_circuit#ULSI.2C_WSI.2C_SOC_and_3D-IC

http://en.wikipedia.org/wiki/65_nanometer

http://en.wikipedia.org/wiki/Electronic_Design_Automation

http://en.wikipedia.org/wiki/Logic_synthesis

http://en.wikipedia.org/wiki/Integrated_circuit_layout

http://en.wikipedia.org/wiki/Static_random-access_memory

http://en.wikipedia.org/wiki/Nanoelectromechanical_systems


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CHAPTER 2

INTRODUCTION TO CADENCE

2.1 INTRODUCTION TO CADENCE TOOL

This manual is intended to introduce microelectronic designers to the Cadence

Design Environment, and to describe all the steps necessary for running the Cadence

tools at the Klipsch School of Electrical and Computer Engineering. Cadence is an

Electronic Design Automation (EDA) environment that allows integrating in a single

framework different applications and tools (both proprietary and from other vendors),

allowing to support all the stages of IC design and verification from a single

environment. These tools are completely general, supporting different fabrication

technologies. When a particular technology is selected, a set of configuration and

technology-related files are employed for customizing the Cadence environment. This

set of files is commonly referred as a design kit. It is not the objective of this manual to

provide an in-depth coverage of all the applications and tools available in Cadence.

Instead, a detailed introduction to those required for an analog designer, from the

conception of the circuit to its physical implementation, is provided. References to other

manuals and information sources with a deeper treatment of these and other Cadence

tools are also provided.

2.2 LIBRARY CREATION AND SELECTION OF TECHNOLOGY

It is recommended that you use a library to store related cell views; e.g.: use a

library to hold all the cell views for a single project (that can involve complete chip

design). In our example, we are going to create a new library for our design.

a) Select File -> New -> Library. A new window appears.

b) Enter a library name, e.g., Project.

c) Enter the absolute path name if you want the library created somewhere else

than the working directory.

d) Choose the Attach to an existing techfile option.

e) Choose your technology: 90nm.


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2.3 TRANSISTOR LEVEL SCHEMATIC

The traditional method for capturing (i.e. describing) your transistor-level or

gate-level design is via the Composer schematic editor. Schematic editors provide

simple, intuitive means to draw, to place and to connect individual components that

make up your design. The resulting schematic drawing must accurately describe the

main electrical properties of all components and their interconnections. Also included

in the schematic are the power supply and ground connections, as well as all "pins"

for the input and output signals of your circuit. This information is crucial for generating

the corresponding netlist, which is used in later stages of the design. The generation of

a complete circuit schematic is therefore the first important step of the former design

flow. Usually, some properties of the components (e.g. transistor dimensions) and/or

the interconnections between the devices are subsequently modified as a result of

iterative optimization steps. These later modifications and improvements on the circuit

structure must also be accurately reflected in the most current version of the

corresponding schematic. Now you are going to create the OTA schematic. From the

CIW or from the Library Manager window,

a) Select the library name that you just created, e.g., Project.

b) Select File -> New -> Cellview.

c) Enter a cell name, for instance.

d) Choose Schematic as the Tool. View name should be schematic.

e) Click OK.

An empty blank Composer - schematic window should open. In this window

you will create your schematic. To create it, you can employ the window top menus or

left icons (or also short keys). This multiple access to actions is common to all the

Cadence tools. A detail information concerning the use of the schematic editor can be

obtained by selecting Help from this window.

• Create components: by selecting the Instance icon and browsing in the pop-

up window through the different libraries. Most components (transistors, R, L,

C, sources, rail terminals, etc.) are in the Analog library. When you create an

instance of a certain component (e.g., transistor, R, C, etc.) a window appears

where you can select the properties of this element.


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Note that for transistors, the model is automatically set according to the

technology you have selected, and that some parameters (drain and source area and

perimeter, etc) are automatically calculated.

NOTE: There are three-terminal (NMOS & PMOS) and four-terminal (NMOS &

PMOS) MOS devices available. The three-terminal devices have a hidden fourth (bulk)

terminal, which is connected by default to “gnd” for NMOS and “Vdd” for PMOS. This

means that you need to have nets named "Vdd!" and "gnd!" somewhere in your

schematic. (The easiest way to do this is to drop in the Vdd and gnd pins from Analog).

If you don't have these nets in your schematic somewhere, you'll get complaints about

unknown nets either in the netlist. (You can also change the bulk node in the three-

terminal device if you want to. Just select the device in the schematic, and bring up the

"Edit Object Properties" form (Edit->Object->Properties...). Change the "Bulk node

connection" field to whichever net you want.

• Wire components: select the Wire (narrow) icon, click to the first terminal

and drag until the other terminal, then click again.

In complex designs, for avoiding excessive wiring, labels can be employed.

When two wire ends are labeled with the same name, they are effectively connected.

Labels are created, e.g., with the Label icon.

• Set instance properties: you can modify at any time the properties of a certain

component instance (resistance value, transistor dimensions, etc), e.g., by

selecting the instance (click on it) and then clicking on the Properties icon.

You can also change a group of instances of the same component

simultaneously, by first selecting this group, then clicking in Properties and

modify the parameters, selecting Apply to > All selected. Most of the

commands in Composer will start a mode and as long as you do not choose a

new mode (by clicking an icon, pressing a short key or selecting a menu item)

you will remain in that mode. To quit from any mode and return to the default

selection mode, the "Esc" key can be used.

2.4 SIMULATION

After the transistor-level description of a circuit is completed using the

Schematic Editor, the Electrical performance and the functionality of the circuit must

be verified using a Simulation tool. The detailed transistor-level simulation of your


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design will be the first in-depth validation of its operation. Hence, it is extremely

important to complete this step before proceeding with the subsequent design

optimization steps. Based on simulation results, the designer usually modifies Some of

the device properties (such as transistor width-to-length ratio) in order to optimize the

Performance. The initial simulation phase also serves to detect some of the design errors

that may have been created during the schematic entry step. It is quite common to

discover errors such as a missing connection or an unintended crossing of two signals

in the schematic. Some of these errors (e.g., floating nodes) can be detected even before

simulation, by pressing the Check and Save icon in the schematic window. The second

simulation phase will follow the "extraction" of a mask layout (post-layout simulation),

to accurately assess the electrical performance of the completed design. Like in other

simulation environments, it is the netlist text file extracted from the schematic (or

layout) what is actually simulated.

2.5 SELECTING THE ANALYSIS

Several analyses can be performed (DC, AC, transient, etc.). For selecting the

required analysis, Choose Analysis > Choose (or the corresponding icon) and complete

the settings in the window that appears.

Example: Transient analysis, choose 'tran', ‘conservative’ and then type in the total

time you wish to run (ex. 100n ). Currents cannot be plotted by default. If you are

interested in viewing currents in your circuit, choose: Output > Save all ....> Select

all DC/transient terminal currents (for DC and transient analyses) or Select all AC

terminal currents (for AC analysis).

2.6 RUNNING THE SIMULATION

When the former steps are performed, simulation can start. Click the Green

Traffic Light Icon (bottom right corner of the simulation window) or choose Run >

Simulation to run the simulation. If you want to interrupt the simulation at any instant,

click the Red Traffic Light Icon or choose Run > Interrupt.


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2.7 PLOTTING THE SIMULATION RESULTS

There are different ways of plotting the results of a simulation. Here we are

going to use the Calculator tool. After running the simulation, choose Tools >

Calculator. A calculator window Appears. With this tool we can maximum and

minimum calculation, etc).

• Use as a normal calculator for making calculations among other things.

• Plot in a waveform window the different currents and voltages.

• Print (to a printer or a file) the selected waveforms.


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CHAPTER 3

INTRODUCTION TO FLIP FLOPS

3.1 IMPORTANCE OF FLIP FLOP

In electronics, a flip-flop or latch is a circuit that has two stable states and can

be used to store state information. A flip-flop is a bistable multivibrator. The circuit

can be made to change state by signals applied to one or more control inputs and will

have one or two outputs. It is the basic storage element in sequential logic. Flip-flops

and latches are fundamental building blocks of digital electronics systems used in

computers, communications, and many other types of systems.

Flip-flops and latches are used as data storage elements. A flip-flop is a device

which stores a single bit (binary digit) of data; one of its two states represents a one and

the other represents a zero. Such data storage can be used for storage of state, and such

a circuit is described as sequential logic in electronics. When used in a finite-state

machine, the output and next state depends not only on its current input, but also on its

current state (and hence, previous inputs). It can also be used for counting of pulses,

and for synchronizing variably-timed input signals to some reference timing signal.

Flip-flops can be either simple (transparent or opaque) or clocked (synchronous

or edge-triggered). Although the term flip-flop has historically referred generically to

both simple and clocked circuits, in modern usage it is common to reserve the term flip-

flop exclusively for discussing clocked circuits; the simple ones are commonly called

latches.

Using this terminology, a latch is level-sensitive, whereas a flip-flop is edge-

sensitive. That is, when a latch is enabled it becomes transparent, while a flip flop's

output only changes on a single type (positive going or negative going) of clock edge.

Flip flop is formed using logic gates, which are in turn made of transistors. Flip

flop are basic building blocks in the memory of electronic devices. Each flip flop can

store one bit of data. Flip flops have two stable states and hence they are bistable

multivibrators.

The two stable states are High (logic 1) and Low (logic 0). The term flip – flop

is used as they can switch between the states under the influence of a control signal

(clock or enable) i.e. they can ‘flip’ to one state and ‘flop’ back to other state. Flip –

flops are a binary storage device because they can store binary data (0 or 1). Flip – flops

https://en.wikipedia.org/wiki/Electronics

https://en.wikipedia.org/wiki/Bistable_multivibrator

https://en.wikipedia.org/wiki/Sequential_logic

https://en.wikipedia.org/wiki/Bit

https://en.wikipedia.org/wiki/Finite-state_machine

https://en.wikipedia.org/wiki/Finite-state_machine


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are edge sensitive or edge triggered devices i.e. they are sensitive to the transition rather

than the duration or width of the clock signal.

• Flip – flops are a binary storage device because they can store binary data (0 or

1).

• Flip – flops are edge sensitive or edge triggered devices i.e. they are sensitive

to the transition rather than the duration or width of the clock signal.

• They are also known as signal change sensitive devices which mean that the

change in the level of clock signal will bring change in output of the flip flop.

• A Flip – flop works depending on clock pulses.

• Flip flops are also used to control the digital circuit’s functionality. They can

change the operation of a digital circuit depending on the state.

FF designs evolve constantly with the advances of new process technology as

well as the target applications, e.g. high speed, low power, and low voltage.

These are also called as sequential logic circuits. Also know these before

learning about flip flops.

• Sequential Logic circuits.

• Latches

3.2 SEQUENTIAL LOGIC CIRCUITS

A Sequential logic circuits is a form of binary circuit; its design employs one

or more inputs and one or more outputs, whose states are related to some definite rules

that depends on previous states. Both the inputs and outputs can reach either of the two

states: logic 0 (low) or logic 1 (high). In these circuits their output depends, not only on

the combination of the logic states at its inputs, but moreover on the logic states that

existed previously. In other words their output depends on a SEQUENCE of the events

occurring at the circuit inputs. Examples of such circuits include clocks, flip-flops, bi-

stables, counters, memories, and register.

3.3 LATCH

Latch is an electronic logic circuit with two stable states i.e. it is a bistable

multivibrator. Latch has a feedback path to retain the information. Hence a latch can be

a memory device. Latch can store one bit of information as long as the device is

https://www.electronicshub.org/sequential-circuits-basics/

https://www.electronicshub.org/latches/

https://www.elprocus.com/different-types-of-digital-logic-circuits/


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powered on. When enable is asserted, latch immediately changes the stored information

when the input is changed i.e. they are level triggered devices. It continuously samples

the inputs when the enable signal is on.

Latch circuits can work in two states depending on the triggering signal being

high or low: Active – High or Active – Low.

• In case of Active – High latch circuits, normally both the inputs are low. The

circuit is triggered by a momentary high on either of the inputs.

• In case of Active – Low latch circuits, normally both the inputs are high. The

circuit is triggered by a momentary low on either of the inputs.

3.4 BASIC FLIP FLOPS

3.4.1 D FLIP-FLOP

Figure 3.1 D Flip Flop

Simple SR flip-flop requires two inputs, one to “set” the output and one to

“reset” the output. By connecting an inverter (NOT gate) to the SR flip-flop we can

“set” and “reset” the flip-flop using just one input as now the two input signals are

complements of each other. This complement avoids the ambiguity inherent in the SR

latch when both inputs are low, since that state is no longer possible. Thus, this single

input is called the “data” input. If this data input is held high the flip flop would be “set”

and when it is low the flip flop would change and become “reset”. However, this would

be rather pointless since the output of the flip flop would always change on every pulse

applied to this data input. To avoid this an additional input called the “clock” or

“enable” input is used to isolate the data input from the flip flop’s latching circuitry of


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after the desired data has been stored. The effect is that D input condition is only copied

to the output Q when the clock input is active. This then forms the basis of another

sequential device called a D Flip Flop.

The “D flip flop” will store and output whatever logic level is applied to its data

terminal so long as the clock input is HIGH. Once the clock input goes low the “set”

and “reset” inputs of the flip-flop are both held at logic level “1” so it will not change

state and store whatever data was present on its output before the clock transition

occurred. The output is “latched” at either logic “0” or logic “1”.

3.4.2 SR LATCH

A bistable multivibrator has two stable states, as indicated by the prefix bi in its

name. Typically, one state is referred to as set and the other as reset. The simplest

bistable device, therefore, is known as a set-reset, or S-R, latch. To create an S-R latch,

we can wire two NOR gates in such a way that the output of one feeds back to the input

of another, and vice versa. The Q and not-Q outputs are supposed to be in opposite

states. I say “supposed to” because making both the S and R inputs equal to 1 results in

both Q and not-Q being 0. For this reason, having both S and R equal to 1 is called

an invalid or illegal state for the S-R multivibrator. Otherwise, making S=1 and R=0

“sets” the multivibrator so that Q=1 and not-Q=0.

Figure 3.2 SR Latch

Conversely, making R=1 and S=0 “resets” the multivibrator in the opposite

state. When S and R are both equal to 0, the multivibrator’s outputs “latch” in their

prior states.

https://www.allaboutcircuits.com/textbook/digital/chpt-3/gate-universality/


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3.4.3 SET RESET FLIP FLOP

A synchronous SR latch (sometimes clocked SR flip-flop) can be made by

adding a second level of NAND gates to the inverted SR latch (or a second level of

AND gates to the direct SR latch). The extra NAND gates further invert the inputs so

the simple SR latch becomes a gated SR latch (and a simple SR latch would transform

into a gated SR latch with inverted enable).

With E high (enable true), the signals can pass through the input gates to the

encapsulated latch; all signal combinations except for (0,0) hold then immediately

reproduce on the (Q,Qbar) output, i.e. the latch is transparent.

With E low (enable false) the latch is closed and remains in the state it was left

the last time E was high.

The enable input is sometimes a clock signal, but more often a read or write

strobe. When the enable input is a clock signal, the latch is said to be level-sensitive (to

the level of the clock signal), as opposed to edge-sensitive like flip-flops.

Figure 3.3 SR Flip Flop

3.4.4 JK FLIP FLOP

The J-K flip-flop is the most versatile of the basic flip-flops. It has the input-

following character of the clocked D flip-flop but has two inputs, traditionally labeled

J and K. If J and K are different then the output Q takes the value of J at the next clock

edge. The inputs are labeled J and K in honor of the inventor of the device, Jack Kilby.

https://en.wikipedia.org/wiki/Clock_signal

http://hyperphysics.phy-astr.gsu.edu/hbase/Electronic/flipflop.html#c1

http://hyperphysics.phy-astr.gsu.edu/hbase/Electronic/dflipflop.html#c3


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If J and K are both low then no change occurs. If J and K are both high at the

clock edge then the output will toggle from one state to the other. It can perform the

functions of the set/reset flip-flop and has the advantage that there are no ambiguous

states. It can also act as a T flip-flop to accomplish toggling action if J and K are tied

together. The major applications of JK flip-flop are Shift registers, storage registers,

counters and control circuits. JK flip- flop has a toggling nature. This has been an added

advantage. Hence, they are mostly used in counters and PWM generation, etc. Here we

are using NAND gates for demonstrating the JK flip flop.

Figure 3.4 JK Flip Flop

Whenever the clock signal is LOW, the input is never going to affect the output

state. The clock has to be high for the inputs to get active. Thus, JK flip-flop is a

controlled Bi-stable latch where the clock signal is the control signal.

http://hyperphysics.phy-astr.gsu.edu/hbase/Electronic/setreset.html#c1

http://hyperphysics.phy-astr.gsu.edu/hbase/Electronic/tflipflop.html#c1


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CHAPTER 4

EXISTING FLIP FLOPS

4.1 MASTER SLAVE FLIP FLOP

The Master-Slave Flip-Flop is basically two gated SR flip-flops connected

together in a series configuration with the slave having an inverted clock pulse. The

outputs from Q and Q from the “Slave” flip-flop are fed back to the inputs of the

“Master” with the outputs of the “Master” flip flop being connected to the two inputs

of the “Slave” flip flop. This feedback configuration from the slave’s output to the

master’s input gives the characteristic toggle of the JK flip flop.

The input signals J and K are connected to the gated “master” SR flip flop which

“locks” the input condition while the clock (clk) input is “HIGH” at logic level “1”. As

the clock input of the “slave” flip flop is the inverse (complement) of the “master” clock

input, the “slave” SR flip flop does not toggle. The outputs from the “master” flip flop

are only “seen” by the gated “slave” flip flop when the clock input goes “LOW” to logic

level “0”.

When the clock is “LOW”, the outputs from the “master” flip flop are latched

and any additional changes to its inputs are ignored. The gated “slave” flip flop now

responds to the state of its inputs passed over by the “master” section

Figure 4.1 Master Slave Flip Flop

Then on the “Low-to-High” transition of the clock pulse the inputs of and the


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“master” flip flop are fed through to the gated inputs of the “slave” flip flop and on the

“High-to-Low” transition the same inputs are reflected on the output of the “slave”

making this type of flip flop edge or pulse-triggered.

Then, the circuit accepts input data when the clock signal is “HIGH”, and passes

the data to the output on the falling-edge of the clock signal. In other words, the Master

Slave JK Flip flop is a “Synchronous” device as it only passes data with the timing of

the clock signal.

4.2 Master Slave Using D Flip Flop

The basic D-type flip flop can be improved further by adding a second SR flip-

flop to its output that is activated on the complementary clock signal to produce a

“Master-Slave D-type flip flop”. On the leading edge of the clock signal (LOW-to-

HIGH) the first stage, the “master” latches the input condition at D, while the output

stage is deactivated.

On the trailing edge of the clock signal (HIGH-to-LOW) the second “slave”

stage is now activated, latching on to the output from the first master circuit. Then the

output stage appears to be triggered on the negative edge of the clock pulse. “Master-

Slave D-type flip flops” can be constructed by the cascading together of two latches

with opposite clock phases.

Figure 4.2 Master Slave Flip Flop Using D Flip Flop


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We can see from above that on the leading edge of the clock pulse the master

flip-flop will be loading data from the data D input, therefore the master is “on”. with

the trailing edge of the clock pulse the slave flip-flop is loading data, i.e. the slave is

“on” then there will always be one flip-flop “on” and the other “off” but never both the

master and slave “on” at the same time. Therefore, the output Q acquires the value of D,

only when one complete pulse, i.e, 0-1-0 is applied to the clock input.

Both outputs to be at logic “1”, over-riding the feedback latching action and

whichever input goes to logic level “1” first will lose control, while the other input still

at logic “0” controls the resulting state of the latch.

But in order to prevent this from happening an inverter can be connected

between the “set” and the “reset” inputs to produce another type of flip flop circuit

known as a Data Latch, Delay flip flop, D-type Bistable, D-type Flip Flop or just

simply a D Flip Flop as it is more generally called.

The D Flip Flop is by far the most important of the clocked flip-flops as it

ensures that ensures that inputs S and R are never equal to one at the same time. The

D-type flip flop are constructed from a gated SR flip-flop with an inverter added

between the S and the R inputs to allow for a single D (Data) input.

Then this single data input, labelled “D” and is used in place of the “Set” signal,

and the inverter is used to generate the complementary “Reset” input thereby making a

level-sensitive D-type flip-flop from a level-sensitive SR-latch as now S = D and R =

not D.

4.3 D LATCH USING MUX

Figure 4.3 D Latch Using MUX


18


Multiplexing is the generic term used to describe the operation of sending one

or more analogue or digital signals over a common transmission line at different times

or speeds and as such, the device we use to do just that is called a Multiplexer.

The multiplexer, shortened to “MUX” is a combinational logic circuit designed

to switch one of several input lines through to a single common output line by the

application of a control signal. Multiplexers operate like very fast acting multiple

position rotary switches connecting or controlling multiple input lines called “channels”

one at a time to the output.

Multiplexers, or MUX’s, can be either digital circuits made from high speed

logic gates used to switch digital or binary data or they can be analogue types using

transistors, mosfet’s or relays to switch one of the voltage or current inputs through to

a single output.

4.3.1 TOPOLOGICALLY COMPRESSED FLIP FLOP USING D

LATCH MUX

The master latch is totally different from the traditional FF design. It uses two

stage same type latch to control master and slave latch by only single clock signal so

that the circuit is simplified by merge the MOS transistors. The master latch adopts the

configuration of a MUX with feedback and can be implemented with two AND-OR-

Invert (AOI) gates and an inverter. The latch is transparent when the clock signal CK

is 0. The inputs pass through the AOI gates and the output of the inverter; that is, node

is always complementary to the input data. When CK turns 1, the contribution from the

input data is blocked and remains unchanged because of a closed path formed by the

upper AOI and the inverter.

Figure 4.4 TCFF using D Latch MUX


19


The slave latch also comprises two AOI gates and an inverter. The

complementary inputs from the master latch are fed to AND terms, which are also

controlled by the clock signal, of the two AOI gates. Only one phase of the clock signal

is used in this design.

4.4 SET RESET MASTER SLAVE FLIP FLOP

A SR flip-flop is used in clocked sequential logic circuits to store one bit of

data. It is similar in function to a gated SR latch but with one major difference: where

the gated latch can have its data set and reset many times whilst the gate input is 1, the

flip-flop can only have the data set or reset once during a clock cycle.

The latch is said to be transparent as the outputs see the inputs when the gate

input is 1. This transparency can be a problem in sequential logic circuits driven by a

clock input if we want at most one circuit state transition per clock period. To

imagine a latch connected to another circuit which in turn is connected to the latch's set

or reset inputs, and let the clock signal be connected to the latch's gate input. During

each clock cycle, the changes in the latch's inputs are fed directly to the rest of the

circuit which is fed back directly to the latch's inputs. This has the potential to give

several state changes within a single clock period. The basic idea of the flip-flop is the

removal of this transparency which stops the latch's inputs feeding back through the

circuit in a single clock cycle. This would give us a sequential circuit which can make

at most one state change per clock period.

The type of SR flip-flop described here is a master-slave SR flip-flop. It is built

from two gated SR latches: one a master, and the other a slave. The master takes the

flip-flops inputs: S (set), R (reset), and CK (clock). The clock input is fed to the latch's

gate input. The slave takes the master's outputs as inputs (Q to S), and the

complement of the flip-flop's clock input.

The slave's outputs are the flip-flop's outputs. This difference in clock inputs

between the two latches disconnects them and eliminates the transparency between of

the flip-flop's inputs and outputs.

The schematic of a master-slave SR flip-flop as two inputs S and R are used to

set and reset the data respectively. The clock input CK is used to control both the master

and slave latches making sure only one of the latches can set its data at any given time.

http://barrywatson.se/dd/dd_sequential_logic.html

http://barrywatson.se/dd/dd_sr_latch_gated.html


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When CK has the value 1, the master latch can set its data and the slave latch

cannot. When CK has the value 0, the slave can set its data and the master cannot. From

this description we see that the flip-flop is level-triggered. The output Q are the

flip-flop's stored data and the complement of the flip-flop's stored data respectively.

Figure 4.5 Set Reset Master Slave Flip Flop

The operation has to be analyzed with the 4 inputs combinations together with

the 2 possible previous states.

• When S = 0 and R = 0: If we assume Q = 1 and Q' = 0 as initial condition, then

output Q after input is applied would be Q = (R + Q')' = 1 and Q' = (S + Q)' =

0. Assuming Q = 0 and Q' = 1 as initial condition, then output Q after the input

applied would be Q = (R + Q')' = 0 and Q' = (S + Q)' = 1. So it is clear that when

both S and R inputs are LOW, the output is retained as before the application of

inputs. (i.e. there is no state change).




applied would be Q = (R + Q')' = 1 and Q' = (S + Q)' = 0. So in simple words

when S is HIGH and R is LOW, output Q is HIGH.




applied would be Q = (R + Q')' = 0 and Q' = (S + Q)' = 1. So in simple words

when S is LOW and R is HIGH, output Q is LOW.


21


• When S = 1 and R =1: No matter what state Q and Q' are in, application of 1

at input of NOR gate always results in 0 at output of NOR gate, which results

in both Q and Q' set to LOW (i.e. Q = Q'). LOW in both the outputs basically is

wrong, so this case is invalid.


22


CHAPTER 5

PROPOSED WORK

5.1 TRANSMISSION GATE FLIP-FLOP

A transmission-gate-based FF (TGFF) is arguably the most widely used FF

currently. One possible drawback of this design is the excessive work load on the clock

signal where complementary signals are required. The consequence is the presence of

a considerable dynamic power even when the data switching activity is low. Recently,

true single-phase clocking (TSPC) FF designs have been developed with the objective

of lowering the clock signal loading. This is usually achieved through circuit

simplification.

Figure 5.1 Transmission Gate Flip-Flop

A transmission gate (TG) is similar to a relay that can conduct in both

directions or block by a control signal with almost any voltage potential. It is

a CMOS-based switch, in which PMOS passes a strong 1 but poor 0, and NMOS

passes strong 0 but poor 1. Both PMOS and NMOS work simultaneously. A classic

master–slave-type TGFF design is shown in Fig, indicating that it comprises two TG-

based latch designs. Inverters I1 and I2 are used to generate complementary clock

signals. This design suffers from a high capacitive clock loading problem (a total of 12

transistors driven by the clock), which indicates a sustained power consumption even

when the input remains static. This problem also occurs in conventional SRFF designs.


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5.2 SET RESET LATCH BASED FLIP-FLOP

Cross-coupled set– reset (SR) latches are used in lieu of the TG-based latch to

support single-clock-phase operations. Degenerate or topologically compressed SR

latches are adopted to lower the circuit complexity. In this paper, we present a novel

SR latch- based FF (SRFF) design comprising both static-CMOS logic and

complementary pass-transistor logic (CPL). This design follows the principle of TSPC

operations to alleviate the clock signal loading. Both logic structure reduction and

transistor optimization schemes are applied to optimize the design.

The simplest way to make any basic single bit set-reset SR flip-flop is to connect

together a pair of cross-coupled 2-input NAND gates as shown, to form a Set-Reset

bistable also known as an active low SR NAND gate Latch, so that there is feedback

from each output to one of the other NAND gate inputs. This device consists of two

inputs, one called the Set, S and the other called the Reset, R with two corresponding

outputs Q and its inverse or complement Qbar.

Figure 5.2 Set Reset Flip Flop

If the input R is at logic level “0” (R = 0) and input S is at logic level “1” (S =

1), the NAND gate has at least one of its inputs at logic “0” therefore, its output Q must

be at a logic level “1” (NAND Gate principles). Output Q is also fed back to input “A”

and so both inputs to NAND gate X are at logic level “1”, and therefore its

output Q must be at logic level “0”. If the reset input R changes state, and goes HIGH

to logic “1” with S remaining HIGH also at logic level “1”, NAND gate Y inputs are


24


now R = “1” and B = “0”. Since one of its inputs is still at logic level “0” the output

at Q still remains HIGH at logic level “1” and there is no change of state. Therefore,

the flip-flop circuit is said to be “Latched” or “Set” with Q = “1” and Q = “0”. In this

second stable state, Q is at logic level “0”, (not Q = “0”) its inverse output at Q is at

logic level “1”, (Q = “1”), and is given by R = “1” and S = “0”. As gate has one of its

inputs at logic “0” its output Q must equal logic level “1” (again NAND gate

principles). Output Q is fed back to input “B”, so both inputs to NAND gate Y are at

logic “1”, therefore, Q = “0”. If the set input, S now changes state to logic “1” with

input R remaining at logic “1”, output Q still remains LOW at logic level “0” and there

is no change of state. Therefore, the flip-flop circuits “Reset” state has also been

latched.

5.3 ADAPTIVE COUPLING FLIP FLOP

To overcome the power consumption problem, two FF designs employing an

adaptive coupling (ac) technique and a topologically compressed scheme have been

proposed. Fig. below shows the ac FF design.

Figure 5.3 Adaptive Coupling Flip Flop

Unlike conventional TGFF designs, this design uses a differential latch structure

with pass-transistor logic to achieve TSPC operation. The TGs are replaced with either

n- or p-type pass transistors. To overcome the impact of process variations on the master

latch, a pair of level restoring circuits is inserted into the cross coupled paths of the

master latch. In this design, only four MOS transistors (two PMOS and two NMOS)


25


are driven by the clock signal, and the transistor count is lowered to 22. A lighter clock

loading in addition to the circuit simplification of the FF design can lower the power

consumption significantly. In this design, the data contention problem in the slave latch

deteriorates as the data switching activity increases, and the advantages of power saving

are thus diminished. The level restoring circuit pair of the master latch results in a longer

setup time. Moreover, this design suffers from a power leaking problem when certain

input and internal node combinations occur.

5.4 SENSE AMPLIFIER BASED FLIP FLOP

The SAFF consists of the SA in the first stage and the slave set-reset (SR) latch

in the second stage as shown in Fig. Thus SAFF is a flip-flop where the SA stage

provides a negative pulse on one of the inputs to the slave latch: S bar or R bar (but not

both), depending whether the output Q is to be set or reset. It senses the true and

complementary differential inputs. The SA stage produces monotonic transitions from

one to zero logic level on one of the outputs, following the leading clock edge. Any

subsequent change of the data during the active clock interval will not affect the output

of the SA. The SR latch captures the transition and holds the state until the next leading

edge of the clock arrives. After the clock returns to inactive state, both outputs of the

SA stage assume logic one value. Therefore, the whole structure acts as a flip-flop.

When Clk is low, nodes labelled S bar and R bar are pre charged through small

MP1 and MP4 PMOS transistors. The lower limit on the size of these transistors is

determined by their capability to pre charge the nodes in one half of the cycle. The high

state of S bar and R bar keeps MN3 and MN4 on, charging their sources up to VDD -

VtN because there is no path to ground due to the off state of the clocked transistor

MN6. Since either MN1 or MN2 is on, the common node of MN1, MN2 and MN6 is

also pre charged to VDD – VtN. Therefore, prior to the leading clock edge, all the

capacitances in the differential tree are pre charged.

The SA stage is triggered on the leading edge of the clock. If D is high, node S

bar is discharged through the path MN3, MN1, MN6, turning MN4 off and MP3 on. If

D bar is high, node R bar is discharged through the path MN3, MN2, MN6 turning

MN3 off and MP2 on. After this initial change, further changes of data inputs will not

affect the state of the S bar and R bar nodes. The inputs are decoupled from the outputs

of the SA forming the base for the flip-flop operation of the circuit. The output of the


26


SA, which is forced low at the leading edge of the clock, becomes floating low if the

data changes during the high clock pulse. The additional transistor MN5 allows static

operation, providing a path to ground even after the data is changed. This prevents the

potential charging of the low output of the SA stage, due to the leakage currents. Those

currents cannot be neglected in low-power designs where the Vt is lowered in order to

boost the performance affected by the scaling of the supply voltage.

Figure 5.4 Sense Amplifier Based Flip Flop

However, the additional transistor MN5 forces the whole differential tree to be

pre charged and discharged in every clock cycle, independent of the state of the data

after the leading edge of the clock. The additional transistor MN5 is minimized, to

prevent a significant increase in delay of the SA stage, due to the simultaneous

discharging of both the direct path capacitive load and the load of the opposite branch.

This flip-flop has differential inputs and is suitable for use with differential and reduced

swing logic. It uses single-phase clock, and has small clock load. Its first stage assures


27


accurate timing, due to its SA topology, which is very important at high operating

frequencies.

The SR latch of the SAFF, shown in Fig, operates as follows: input S bar is a

set and input R bar is a reset input. The low level at both S bar and R bar node is not

permitted and that is guaranteed by the SA stage. The low level at S bar sets the Q

output to high, which in turn forces Q bar to low. Conversely, the low level at R bar

sets the Q bar high, which in turn forces Q to low. Therefore, one of the output signals

will always be delayed with respect to the other. The rising edge always occurs first,

after one gate delay, and the falling edge occurs after two gate delays. Additionally, the

delay of the true output Q, depends on the load on the complementary output Q bar,

and vice versa. This limits the performance of the SAFF.

5.5 EXPLICIT PULSED STATIC FLIP FLOP

For reduced power consumption, an explicit-pulsed, hybrid static flip-flop (ep-

SFF). Sharing the pulse generator is not as effective for the ep-DSFF as for the ep-SFF

since the transistor sizes are larger, therefore if sharing is possible the single edge-

triggered ep-SFF has the lowest energy consumption. These comparisons reflect

only the energy of the flip-flop itself and do not include power in the clock distribution

network.

Figure 5.5 Explicit Pulsed Static Flip Flop

A more efficient dual edge-triggered flip-flop may be realized by replacing the

pulse generator in the single edge-triggered ep-SFF with an explicit dual edge-triggered


28


pulse generator. This pulse generator may be local to each flop or shared among

multiple flops. Because the entire latch is not duplicated, the area overhead for this

technique is much less than for the conventional flip flops. In addition, implementing

features such as scan, reset, or enable for this flip-flop may be easier than for the

duplicated-latch designs since there only exists one path from data input to output.

There are many possible implementations of flip-flops using dual edge-

triggered pulse generators; an energy-efficient dual edge-triggered, explicit pulsed

static hybrid flop. Because the path from data to output of the flip-flop is identical to

the ep-SFF, latency and throughput of dsff are the same as ep-SFF, while the clock

frequency is halved. As a result, power dissipation of ep-DSFF with a local pulse

generator is 21% less than ep-SFF at a target D-Q delay. Sharing the pulse generator is

not as effective for the ep-DSFF as for the ep-SFF since the transistor sizes are larger;,

therefore if sharing is possible the single edge-triggered ep-SFF has the lowest energy

consumption. These comparisons reflect only the energy of the flip-flop itself and do

not include power in the clock distribution network. The ep-SFF have larger energy

consumption than the static flops and are not attractive for a low-performance

application unless the pulse generators are shared. If pulse generators are shared among

groups of flip-flops, it is evident that the energy savings are not as significant. However,

sharing pulse generators introduces additional complexities into the design regarding

pulse distribution and margining for pulse width variation.

5.6 COMPLIMENTARY PASS TRANSISTOR LOGIC

pass transistor logic (PTL) describes several logic families used in the design

of integrated circuits. It reduces the count of transistors used to make different logic

gates, by eliminating redundant transistors. Transistors are used as switches to

pass logic levels between nodes of a circuit, instead of as switches connected directly

to supply voltages. This reduces the number of active devices, but has the disadvantage

that the difference of the voltage between high and low logic levels decreases at each

stage. Each transistor in series is less saturated at its output than at its input. If several

devices are chained in series in a logic path, a conventionally constructed gate may be

required to restore the signal voltage to the full value. By contrast, conventional CMOS

logic switches transistors so the output connects to one of the power supply rails, so

logic voltage levels in a sequential chain do not decrease. Simulation of circuits may be

https://en.wikipedia.org/wiki/Logic_family

https://en.wikipedia.org/wiki/Integrated_circuit

https://en.wikipedia.org/wiki/Logic_gate

https://en.wikipedia.org/wiki/Logic_gate

https://en.wikipedia.org/wiki/Logic_level

https://en.wikipedia.org/wiki/CMOS_logic

https://en.wikipedia.org/wiki/CMOS_logic


29


required to ensure adequate performance. Pass transistor logic often uses fewer

transistors, runs faster, and requires less power than the same function implemented

with the same transistors in fully complementary CMOS logic.

The pass transistor is driven by a periodic clock signal and acts as an access

switch to either charge up or charge down the parasitic capacitance Cx, depending on

the input signal Vin. Thus, two possible operations when the clock signal is active (CK

= 1) are the logic "1" transfer (charging up the capacitance Cx to a logic-high level) and

the logic "0" transfer (charging down the capacitance Cx to a logic-low level). In either

case, the output of the depletion load NMOS inverter obviously assumes a logic-low or

a logic-high level, depending upon the voltage.

Some authors use the term "complementary pass transistor logic" to indicate a

style of implementing logic gates that uses transmission gates composed of both NMOS

and PMOS pass transistors. Other authors use the term "complementary pass transistor

logic" (CPL) to indicate a style of implementing logic gates where each gate consists

of a NMOS-only pass transistor network, followed by a CMOS output inverter. To

indicate a style of implementing logic gates using dual-rail encoding. Every CPL gate

has two output wires, both the positive signal and the complementary signal,

eliminating the need for inverters. Complementary pass transistor logic or "Differential

pass transistor logic" refers to a logic family which is designed for certain advantage.

It is common to use this logic family for multiplexers and latch. CPL uses series

transistors to select between possible inverted output values of the logic, the output of

which drives an inverter The CMOS transmission gates consist of NMOS and PMOS

transistor connected in parallel.

Complementary pass-transistor logic consists of complementary inputs/outputs,

a NMOS pass-transistor network, and CMOS output inverters. The circuit function is

implemented as a tree consisting of pull-down and pull-up branches. Since the threshold

voltage drop of NMOS transistor degrades the “high” level of pass-transistor output

nodes, the output signals are restored by CMOS inverters. CPL has traditionally been

applied to the arithmetic building blocks and has been shown to result in high-speed

operation due to its low input capacitance and reduced transistor count.

A general method of Karnaugh map coverage and mapping into circuit

realizations is applied to design logic AND/NAND, OR/NOR, and XOR/XNOR gates

in CPL. The method consists of the implementation of the gates from Karnaugh

https://en.wikipedia.org/wiki/Transmission_gate

https://en.wikipedia.org/wiki/Logic_families

https://en.wikipedia.org/wiki/Multiplexer#Digital_multiplexers

https://en.wikipedia.org/wiki/Inverter_(logic_gate)

https://en.wikipedia.org/wiki/Transmission_gate


30


maps, and further simplifications: complementarity and duality principles that easily

generate entire set of two-input and three-input logic gates.

The rules for Karnaugh map coverage and circuit realization in CPL are given

below:

• Cover Karnaugh-map with largest possible cubes (overlapping allowed).

• Derive the value of a function in each cube in terms of input signals.

• Assign one branch of transistor(s) to each of the cubes and connect all branches

to one common node, which is the output of NMOS pass-transistor network.

The generation of complementary and dual functions is simple, by observing

the basic properties of these gates. The complementary logic function can be obtained

from the same circuit structure by applying the complementarity principle.

Figure 5.6 XOR and XNOR gates using CPL

Complementarity principle

• The same circuit topology, with inverted pass signals, produces the

complementary logic function in CPL.

• The complementarity principle holds in CPL since the pass variables are

directly passed from the inputs to the outputs, so an inversion of the pass

variables gives complementary function.

• The dual logic function can be obtained by applying the duality principle.


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5.7 TOPOLOGICALLY COMPRESSED FLIP FLOP

Fig. shows another SR-latch-based TSPC FF design named topologically

compressed FF (TCFF), obtained through a topologically compressed scheme.

Figure 5.7 MOS Circuit Schematic of TCFF

The master latch adopts the configuration of a MUX with feedback and can be

implemented with two AND-OR-Invert (AOI) gates and an inverter. The latch is

transparent when the clock signal CK is 0. The inputs pass through the AOI gates and

the output of the inverter; that is, node x3 is always complementary to the input data.

When CK turns 1, the contribution from the input data is blocked and x3 remains

unchanged because of a closed path formed by the upper AOI and the inverter. The

slave latch also comprises two AOI gates and an inverter. The complementary inputs

from the master latch are fed to AND terms, which are also controlled by the clock

signal, of the two AOI gates. Only one phase of the clock signal is used in this design.

For N (pull-down) logic, one CK-controlled NMOS transistor can be shared by the two

discharging paths. For P (pull-up) logic, four pairs of PMOS transistors are connected

to VDD, and two of these pairs share identical inputs. Therefore, two PMOS pairs of

the master latch can be eliminated. Notably, nodes x2 and x3 are always complementary

to each other, implying that either the x2- or x3-controlled PMOS transistors will turn

ON. The drain node of the turned ON PMOS transistor corresponds to a virtual VDD.

Through the addition of an extra clock controlled PMOS transistor across the two AOI

gates, the two clock-driven PMOS transistors can be removed without affecting the

function.

The transistor count is reduced from 28 to 21 and only three transistors are

driven directly by the clock signal. All these factors contribute to a significant power


32


saving of the design. This design is fully static, even though both pull-up and pull-down

logic networks are largely simplified.

Figure 5.8 Circuit Optimization Using TCFF

The TCFF design is based on three optimization principles:

• use only a single phased clock.

• Reduce the number of transistors driven by the clock.

• Reduce the total transistor count.

The significant improvement in the power consumption, the timing performance

of the TCFF design is compromised. In particular, the design suffers from a longer

setup time because of a weakened pull-up network in which only two PMOS

transistors are connected to VDD directly. The critical path consists of three PMOS

transistors connected in series. Although this problem can be alleviated by enlarging

the PMOS transistors, the power consumption is negatively impacted.

5.8 LOGIC STRUCTURE REDUCTION FLIP FLOP

The proposed design, named logic structure reduction FF (LRFF), can be

considered as an enhancement of the TCFF design in different performance aspects.

This design is achieved by various optimization measures. The first measure is the logic

reduction for a shorter setup time, the second one is circuit simplification for lowering

the power consumption, and the third one is the elimination of the node floating case to

avoid the static power leaking problem.

The converged discharging path controlled by x2/x3 and CK in the slave latch

is first split into two separate discharging paths, each comprising two NMOS


33


transistors in series and implementing the logic x2·CK·0 and x3·CK·0. If x2 = 1 (or x3

= 1), it is logically equivalent to ¯ x2· CK (or ¯x3 ·CK). Because x2 and x3 are

complementary, ¯ x2 ·CK = x3 ·CK (or ¯ x3 ·CK = x2 ·CK).

Figure 5.9 Discharge Path Of LRFF

As indicated in the small figure this term can be implemented using one pass

transistor with CK as the control signal and x3 (or x2) as the sink of the discharging

current. The converged discharging path in the TCFF design can be split into two

separate paths, each comprising one pass transistor. Because these two pass transistors

operate in a complementary manner, they are considered as CPL, and the transistor

count can thus be reduced by one.

The benefit of this logic structure reduction is twofold. First, it simplifies the

circuit for power saving. Although the pull down delay might be slightly prolonged, it

does not correspond to the worst case timing (in contrast to the pull-up delay). Second,

when node x2 (or x3) is equal to 1, the pass transistor works in conjunction with the

pull-up path formed by PMOS transistors p3/p4 (or p5/p6) to boost the output node of

AOI to 1. This path is considered auxiliary because a “weak 1” can be delivered by an

NMOS pass transistor. This additional current boost, however, improves the worst case

delay when the slave latch is in the transparent mode (CK = 1). A shorter clock-to-Q

(CQ) delay can be obtained. The dotted and solid arrowed lines in Fig 3.10 indicate the

working of these two charging paths to drive node x5 (or x4).

The second logic structure reduction scheme is applied to the second AOI gate

of the master latch. The discharging path of node x2 controlled by CK and x3 discharges


34


only when both signals equal 1. Pass transistor n7 in addition to pull-down transistor

n8 controlled by x4 forms an alternative discharging path for node x2.

Figure 5.10 Proposed Design of LRFF

We can thus remove the original (and redundant) path to simplify the circuit.

This measure not only improves the power performance but also reduces the capacitive

load of node x2. A shorter propagation delay can be achieved for the master latch when

operating in the transparent mode, resulting in a shorter setup time of the FF design.

The circuit schematic after the application of the two logic structure reduction

schemes is presented. The total number of transistors is only 19. Only one of the has

single phase of the clock is required, and the fan-out for the clock signal is four (one

PMOS and three NMOS transistors). The proposed LRFF is fully static and can avoid

the case of temporary output node floating. When CPL is introduced, the circuit

complexity of its p-logic network is largely reduced, even though the design is not a

dynamic logic. In conclusion, the proposed design can successfully achieve circuit

complexity reduction and timing parameter enhancement simultaneously.


35


CHAPTER 6

DESIGN AND IMPLEMENTATION OF FLIP FLOPS

This chapter presents the design and implementation of flip flops using

cadence tool 6.1 presents the design of flip flops using logic gates. 6.2 presents the

design and implementation of proposed flip flops using PMOS and NMOS transistors.

6.1 DESIGN OF EXISTING FLIP FLOPS

6.1.1 SCHEMATIC OF TOPOLOGICALLY COMPRESSED FLIP

FLOP USING LOGIC GATES

The TCFF consists of master latch adopts the configuration of a MUX with

feedback and can be implemented with two AND-OR-Invert (AOI) gates and an

inverter. The latch is transparent when the clock signal CK is 0. The inputs pass through

the AOI gates and the output of the inverter; that is, node x3 is always complementary

to the input data. When CK turns 1, the contribution from the input data is blocked and

x3 remains unchanged because of a closed path formed by the upper AOI and the

inverter. The slave latch also comprises two AOI gates and an inverter. The

complementary inputs from the master latch are fed to AND terms, which are also

controlled by the clock signal, of the two AOI gates. Only one phase of the clock signal

is used in this design.

Figure 6.1 Schematic of TCFF using Logic Gates


36


The master latch adopts the configuration of a MUX with feedback and can be

implemented with two AND-OR-Invert (AOI) gates and an inverter. The latch is

transparent when the clock signal CK is 0. The inputs pass through the AOI gates and

the output of the inverter; that is, node x3 is always complementary to the input data.

When CK turns 1, the contribution from the input data is blocked and x3 remains

unchanged because of a closed path formed by the upper AOI and the inverter. The

slave latch also comprises two AOI gates and an inverter. The complementary inputs

from the master latch are fed to AND terms, which are also controlled by the clock

signal, of the two AOI gates. Only one phase of the clock signal is used in this design.

6.1.2 SCHEMATIC OF SET RESET FLIP FLOPS USING LOGIC

GATES

Inverters are used to generate complementary clock signals. This design suffers

from a high capacitive clock loading problem which indicates a sustained power

consumption even when the input remains static. This problem also occurs in

conventional SRFF designs. To overcome the power consumption problem, two FF

designs employing an adaptive coupling technique and a topologically compressed

scheme have been proposed.

Figure 6.2 Schematic of SRFF using Logic Gates

The operation has to be analyzed with the 4 inputs combinations together


37


• When Data=0 and CLK =0

When both the inputs are low, the inverters I1 and I2 will become 1,the AND

gate A1 output will become 0 and A2 output will become1,assume S =0 then

the NOR gate N1 output will become 1 and N2 output will be 0,A3 and A4

will be 0 and assume X=1 then the output of N3 and N4 will be 0 then the

output Q will be high.


When clock turns to 1, the inverters I1 will become 1 and I2 will become 0,the

AND gate A1 output will become 0 and A2 output will become1,assume S =1

then the NOR gate N1 output will become 1 and N2 output will be 0,A3 will

be 1 and A4 will be 0 and assume X=1 then the output of N3 and N4 will be 0

then the output Q will be high.


When data turns to 1, the inverters I1 will become 0 and I2 will become 1,the

AND gate A1 output will become 1 and A2 output will become 0,assume S =0

then the NOR gate N1 output will become 0 and N2 output will be 1,A3 will

be 0 and A4 will be 0 and assume X=1 then the output of N3 will be 0 and N4

will be 1 then the output Q will be low.


When both inputs are high, the inverters I1 will become 0 and I2 will become

0,the AND gate A1 output will become 0 and A2 output will become 0,assume

S =1 then the NOR gate N1 output will become 1 and N2 output will be 0,A3

will be 1 and A4 will be 0 and assume X=1 then the output of N3 will be 0 and

N4 will be 1 then the output Q will be low.

6.2 DESIGN OF PROPOSED FLIP FLOPS

6.2.1 SCHEMATIC OF TRANSMISSION GATE FLIP FLOP

This design uses a differential latch structure with pass-transistor logic to

achieve TSPC operation. The TGs are replaced with either n- or p-type pass transistors.

To overcome the impact of process variations on the master latch, a pair of level

restoring circuits is inserted into the cross coupled paths of the master latch. In this


38


design, only four MOS transistors (two PMOS and two NMOS) are driven by the clock

signal, and the transistor count is lowered to 22. A lighter clock loading in addition to

the circuit simplification of the FF design can lower the power consumption

significantly.

Figure 6.3 Schematic of TGFF



When both inputs are low, the inverter I3 will become 1 then the NMOS

transistor will be in ON state and I4 will become 0 then PMOS will in ON state

and I5 will become 1 and the output Q will be 0.


When CK turns to 1, the inverter I3 will become 1 then the NMOS transistor

will be in ON state and I4 will become 0 then PMOS will in ON state and I5

will become 1 and the output Q will be 0.


When Data turns to 1, the inverter I3 will become 0 then the PMOS transistor

will be in ON state and I4 will become 1 then NMOS will in ON state and I5

will become 0 and the output Q will be 1.


39



When both the inputs are high, the inverter I3 will become 0 then the PMOS

transistor will be in ON state and I4 will become 1 then NMOS will in ON

state and I5 will become 0 and the output Q will be 1.

6.2.2 SCHEMATIC OF SET RESET FLIP FLOP

Figure 6.4 Schematic of SRFF



If both the inputs are low, then the NMOS transistors will be in OFF state except

n3 and PMOS transistors p7 will be in ON state and remaining all transistors

will be in ON state then the x4 value will become 0 and the output Q will be

high.


When Clock turns to 1, then the NMOS transistors will be in OFF state except

n2 and n3 and PMOS transistors p7 will be in OFF state and remaining all

transistors will be in ON state then the x4 value will become 0 and the output Q

will be high.


40



When data turns to 1, then the NMOS transistors n2, n8 will be in OFF state

and PMOS transistors p1 to p6 will be in OFF state and remaining all

transistors will be in ON state then the x4 value will become 1 and the output

Q will be low.


If both the inputs are high, then the NMOS transistors will be in ON state and

PMOS transistors p1 to p6 will be in OFF state and remaining all transistors will

be in ON state then the x4 value will become 1 and the output Q will be low.

6.2.3 SCHEMATIC OF SENSE AMPLIFIER FLIP FLOP

Figure 6.5 Schematic of SAFF



If data is 0 and CK is 0 then all NMOS transistors will be in OFF state and

PMOS transistors Mp1, Mp2, Mp3, Mp4 will be in ON state. After the analysis

of Data and CK signals the S bar and R bar will become VDD and if we assume

Q bar as 1 or 0 then the output will become high.


41



When CK turns to 1, all NMOS transistors will be in OFF state expect Mn6 and

PMOS transistors Mp1, Mp2, Mp3, Mp4 will be in OFF state then the output

will be high.


When Data=1 and Ck=0, all NMOS transistors will be in ON state expect Mn6

and PMOS transistors will be in ON state and the output Q will be High.


When both the inputs are high then the all NMOS transistors will be in ON

state and PMOS transistors will be in OFF state and the output Q will be high.

6.2.4 SCHEMATIC OF ADAPTIVE COUPLING FLIP FLOP

Figure 6.6 Schematic of ACFF



When both the inputs are low, the inverter I1 will become 1 and inverter I2 will

become 0 then the PMOS transistors P3 and P4 will be in ON state and the


42


NMOS transistors will be in OFF state. Due to this, we get a floating problem

in the circuit and the output Q will be totally high.


When CK turns to 1, the inverter I1 will become 1 and inverter I2 will become

0 then the PMOS transistors P3 and P4 will be in OFF state and the NMOS

transistors will be in ON state.


When Data is high, the inverter I1 will become 0 and inverter I2 will become 1

then the PMOS transistors P3 and P4 will be in ON state and the NMOS

transistors will be in OFF state.


When both the inputs are high, the inverter I1 will become 0 and inverter I2 will

become 1 then the PMOS transistors P3 and P4 will be in OFF state and the

NMOS transistors will be in ON state.

6.2.5 SCHEMATIC OF EXPLICIT PULSED STATIC FLIP FLOP

Figure 6.7 Schematic of EPSFF



43



When both inputs are low, the inverter I1 will become 1, I2 will be 0, I3 will

be 1 and the NAND gate output will be 1. The NMOS transistor will be in

OFF state and PMOS transistor will be in ON state and the output Q bar will

be 0.


When CLK turns to 1, the inverter I1 will become 0, I2 will be 1, I3 will be 0

and the NAND gate output will be 1. The NMOS transistor will be in OFF

state and PMOS transistor will be in ON state and the output Q bar will be O.


When Data turns to 1, the inverter I1 will become 1,I2 will be 0,I3 will be 1

and the NAND gate output will be 1.The NMOS transistor will be in ON state

and PMOS transistor will be in OFF state and the output Q bar will be 1.


When both the inputs are high, the inverter I1 will become 0, I2 will be 1,I3

will be 0 and the NAND gate output will be 1.The NMOS transistor will be in

ON state and PMOS transistor will be in OFF state and the output Q bar will

be 1.

6.2.6 SCHEMATIC OF TOPOLOGICALLY COMPRESSED FLIP

FLOP

Figure 6.8 Schematic of TCFF


44




If both the inputs are low, then the NMOS transistors n1, n3, n7, n8, n9, n10

will be in OFF state and PMOS transistors p7 will be in ON state and remaining

all transistors will be in ON state then the x4 value will become 0 and the output

Q will be high.


When the CK turns to 1, then the NMOS transistors n1, n8, n9 will be in OFF

state and PMOS transistors p7 will be in OFF state and remaining all transistors

will be in ON state then the x4 value will become 0 and the output Q will be

high.


When data turns to 1, then the NMOS transistors n2, n3, n5, n6, n7, n10 will be

in OFF state and PMOS transistors p1, p5, p6, p3, p4 will be in OFF state and

remaining all transistors will be in ON state then the x4 value will become 1 and

the output Q will be low.


If both the inputs are high, then the NMOS transistors n2, n5, n6, will be in OFF

state and PMOS transistors p1, p5, p6, p3, p4 will be in OFF state and remaining

all transistors will be in ON state then the x4 value will become 1 and the output

Q will be low.

6.2.7 SCHEMATIC OF LOGIC STRUCTURE REDUCTION FLIP

FLOP

The LRFF consists of 19 transistors which has been reduced by using

complimentary pass transistor logic. LRFF is the enhancement of TCFF the no of

transistor has been reduced from 21 to 19 in logic structure reduction flip flop. The

LRFF has been designed with low power and low delay performance compared to all

other flip flops and by comparing with logic gate flip flop the LRFF has a low power

consumption.


45


Figure 6.9 Schematic of LRFF



If both the inputs are low, then the NMOS transistors n1, n3, n7, n8, n9, n10

will be in OFF state and PMOS transistors p7 will be in ON state and

remaining all transistors will be in ON state then the x4 value will become 0

and the output Q will be high.


When the CK turns to 1, then the NMOS transistors n1, n8, n9 will be in OFF

state and PMOS transistors p7 will be in OFF state and remaining all

transistors will be in ON state then the x4 value will become 0 and the output

Q will be high.


When data turns to 1, then the NMOS transistors n2, n3, n5, n6, n7, n10 will

be in OFF state and PMOS transistors p1, p5, p6, p3, p4 will be in OFF state

and remaining all transistors will be in ON state then the x4 value will become

1 and the output Q will be low.


If both the inputs are high, then the NMOS transistors n2, n5, n6, will be in

OFF state and PMOS transistors p1, p5, p6, p3, p4 will be in OFF state and


46


remaining all transistors will be in ON state then the x4 value will become 1

and the output Q will be low.


47


CHAPTER 7

RESULTS AND DISCUSSIONS

These chapter presents the outputs of all the schematic diagrams which has been

used in the chapter 6. The results and discussions of the existing and proposed design

flip flops using cadence tool.

7.1 OUTPUT WAVEFORM OF TCFF USING LOGIC GATES

Figure 7.1 TCFF Logic Gates Output Waveform


48


The TCFF using logic gates consists of two flip flops, master flip flop and slave

flip flop. In place of master flip flop, we are using MUX based latch. In this design, if

we give data and clock as one combination, we will get the output either 1 or 0 at master

flip flop output. Suppose next if we give another input combination at the inputs we

don’t get the output because it stores the previous value but not current value. So in this

waveform we will get the output as total high.

7.2 OUTPUT WAVEFORM OF SRFF USING LOGIC GATES

Figure 7.2 SRFF Logic Gates Output Waveform

The SRFF using logic gates consists of 3 NOT gates, 4 AND gates, 4 NOR

gates. In the above given waveforms, if we give both inputs are low (Data=0,CK=0)

then the output Q will be high (1).When the inputs Data=low(0) and CK=high(1) then


49


the output Q will be high(1) and if Data=high(1) and CK=low(0) then the output Q will

be low(0).If both the inputs are high(Data=1,Ck=1) then the output Q will be low(0).

7.3 OUTPUT WAVEFORM OF TGFF

Figure 7.3 TGFF Output Waveform

The TGFF flip flop consists of 4 Transmission gates and 8 NOT gates. A TGFF

is the most widely used flip flop currently. In this waveform, the output will be same as

the Data input. If both the inputs are low then the output Q will be low (0). If both inputs

are high then the output will be high (1). When Data=1 and CK=0 then the output Q

will be high (1) and data=0 and CLK=1 then the output Q will be low (0).


50


7.4 OUTPUT WAVEFORM OF SRFF

Figure 7.4 SRFF Output Waveform

The output of SRFF using transistors is shown in above fig 7.4. In the above

given waveforms, if we give both inputs are low (Data=0,CK=0) then the output Q

will be high (1).When the inputs Data=low(0) and CK=high(1) then the output Q will

be high(1) and if Data=high(1) and CK=low(0) then the output Q will be low(0).If both

the inputs are high(Data=1,Ck=1) then the output Q will be low(0).


51


7.5 OUTPUT WAVEFORM OF SAFF

Figure 7.5 SAFF Output Waveform

The SAFF consists of two parts, one is sense amplifier and other part is RS

latch. In this output waveform the total output will be high for four different

combinations. If the both inputs are low or high then the output will be high (1). If one

input is high and other input is low then also the output Q will be high (1).


52


7.6 OUTPUT WAVEFORM OF ACFF

Figure 7.6 ACFF Output Waveform

The ACFF flip flop consists of 2 PMOS transistors, 2 NMOS transistors and 7

NOT gates. To overcome the power consumption problem, we are using this ACFF

design. In this design we have a floating problem so whatever value we stored that will

be the output. If we give both inputs either high or low then the output will be high


53


(1). If Data=1 and CK=0 then the output Q will be high and If data=0 and CK=1 then

the output will be high. In ACFF, if we give any combination the output Q will be high.

7.7 OUTPUT WAVEFORM OF EPSFF

Figure 7.7 EPSFF Output Waveform

The EPSFF consists of one PMOS, one NMOS, 7 NOT gates and one NAND

gate. In the above given waveforms, if we give both inputs are low (Data=0,CK=0) then

the output Q will be high (1).When the inputs Data=low(0) and CK=high(1) then the

output Q will be high(1) and if Data=high(1) and CK=low(0) then the output Q will be

low(0).If both the inputs are high(Data=1,Ck=1) then the output Q will be low(0).


54


7.8 OUTPUT WAVEFORM OF TCFF

Figure 7.8 TCFF Output Waveform

The output of TCFF using transistors is shown in above fig 7.8. In the above

given waveforms, if we give both inputs are low (Data=0,CK=0) then the output Q will

be high (1).When the inputs Data=low(0) and CK=high(1) then the output Q will be

high(1) and if Data=high(1) and CK=low(0) then the output Q will be low(0).If both



55


7.9 OUTPUT WAVEFORM OF LRFF

Figure 7.9 LRFF Output Waveform

The output of LRFF using transistors is shown in above fig 7.9. The proposed

design, named logic structure reduction FF (LRFF), can be considered as an

enhancement of the TCFF design in different performance aspects. In the above given

waveforms, if we give both inputs are low (Data=0,CK=0) then the output Q will be

high (1).When the inputs Data=low(0) and CK=high(1) then the output Q will be

high(1) and if Data=high(1) and CK=low(0) then the output Q will be low(0).If both



56


7.10 RESULTS OF EXISTING FLIP FLOPS AND PROPOSED FLIP

-FLOPS

7.10.1 RESULTS OF EXISTING FLIP FLOPS

FLIP FLOPS POWER

(µW)

DELAY

(pS)

PDP

(10–15)

Topologically Compressed

Flip Flop Using MUX Based

Latch

10.9

122.6

1.336

Set Reset Flip Flop Using

Logic Gates

23.7

10110.0

239.6

Table 7.1 Results of Existing Flip Flops

7.10.2 RESULTS OF PROPOSED FLIP FLOPS

FLIP FLOPS POWER

(µW)

DELAY

(pS)

PDP

(10–15)

TGFF 0.8308 20060.0 16665.84

ACFF 13.04 98.84 1288.87

SRFF 1.022 20.7 269.92

SAFF 0.2526 78.55 19.76

EPSFF 0.679 109.6 74.418

TGFF 0.606 11.15 6.756

LRFF 0.775 38.37 29.4

Table 7.2 Results of Proposed Design


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CHAPTER 8

CONCLUSION

The performance levels of seven FF designs were compared. A low-power true

single-phase clocking flip-flop (FF) design achieved using reducing the power and

delay performance. The design follows a masters lave-type logic structure and features

a hybrid logic design comprising both static CMOS logic and complementary pass-

transistor logic. In this design, a logic structure reduction scheme is employed to reduce

the number of transistors for achieving high power and delay performance. By

comparing both existing design and proposed design the power and delay is reduced in

proposed design. The proposed flip flops are designed and simulated using CMOS

technology. The performance parameters power and delay are examined. Low power

consumption and low delay is obtained using proposed logic.


58


REFERENCES

[1] N. Kawai, “A fully static topologically-compressed 21-transistor flip-flop with 75%

power saving,” IEEE J. Solid-State Circuits, vol. 49, no. 11, pp. 2526–2533, Nov. 2014.

[2] Y. Shizuku, T. Hirose, N. Kuroki, M. Numa, and M. Okada “A 24-transistor static

flip-flop consisting of NOR’s and inverters for low power vlsi,” in Proc. IEEE 12th

NEWCAS, Jun. 2014, pp. 137–140.

[3] https://people.eecs.berkeley.edu/~bora/publications/MEJ00.pdf

[4] http://www.csun.edu/~rd436460/DigitalElectronics/Chapter%205.pdf.

[5] http://msrprojectshyd.com/upload/academicprojects/bc2a359edf4d2303acd204675

269b0601.pdf

[6] M. Matsui, “A 200 MHz 13 mm2/2-D DCT macrocell using sense amplifying

pipeline flip-flop scheme,” IEEE J. Solid-State Circuits, vol. 29, no. 12, pp. 1482–

1490, Dec. 1994.

[7] V. Stojanovic and V. G. Oklobdzija, “Comparative analysis of master slave latches

and flip-flops for high-performance and low-power systems,” IEEE J. Solid-State

Circuits, vol. 34, no. 4, pp. 536–548, Apr. 1999.

[8] C. K. Tech, T. Fujita, H. Hara, and M. Hamada, “A 77% energy-saving 22-transistor

single-phase-clocking D-flip-flop with adaptive-coupling configuration in 40 nm

CMOS,” in ISSCC Dig. Tech. Papers, Feb. 2011, pp. 338–339.

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