vhdl-lab work file

7/24/2019 vhdl-lab work file

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CA ASSIGNMENT-6

BY KANERIA DHAVAL

BARREL SHIFTER

module barrel (

i!u" #$%&i'

i!u" #$%&)*'

i!u" )*i+",Le+"Ri*"'ro"a"e,Le+"Ri*"'ou"!u" re #$%& ou"./

!arame"er 012/

al3a4)5

bei

i+(7)*i+",Le+"Ri*".

ou" 0 i88)*/

el)e i+()*i+",Le+"Ri*".

ou" 0 i99)*/

el)e

bei

:a)e()*.

;i#-@$%&'i#$-2&?$>i#2$%&'i#$@&?/

;i#-$%&'i#$-1&?$>i#1$%&'i#$&?/


2/28

;i#-6$%&'i#$-;&?$>i#;$%&'i#$6&?/

;i#-$%&'i#$-&?$>i#$%&'i#$&?/

;i#-2%$%&'i#$-&?$>i#$%&'i#$2%&?/

;i#-2@$%&'i#$-22&?$>i#22$%&'i#$2@&?/

;i#-2$%&'i#$-21&?$>i#21$%&'i#$2&?/

;i#-26$%&'i#$-2;&?$>i#2;$%&'i#$26&?/

;i#-2$%&'i#$-2&?$>i#2$%&'i#$2&?/

;


3/28

;i#-@2$%&'i#$-@%&?$>i#@%$%&'i#$@2&?/

;i#-@1$%&'i#$-@@&?$>i#@@$%&'i#$@1&?/

;i#-@;$%&'i#$-@&?$>i#@$%&'i#$@;&?/

;i#-@$%&'i#$-@6&?$>i#@6$%&'i#$@&?/

;i#-@$%&'i#$-@&?$>i#@$%&'i#$@&?/

;i#-12$%&'i#$-1%&?$>i#1%$%&'i#$12&?/

de+aul"$

ou"0i/

ed:a)e

ed


4/28

ed

edmodule

"ime):ale 2) 2!)

module barrel,"b F(!arame"er 012.(./

re #$%&i/

re #;$%&)*/

re )*i+",Le+"Ri*"'ro"a"e,Le+"Ri*"/

3ire #$%& ou"/

barrelb)(i(i.')*()*.')*i+",Le+"Ri*"()*i+",Le+"Ri*".'ro"a"e,Le+"Ri*"(ro"a"e,Le+"Ri*".'ou"(ou"../

ii"ial

bei

F2i01@


5/28

F2 )*0;


6/28

Ii"ialie I!u")

i 0 %/

)* 0 %/

)*i+",Le+"Ri*" 0 %/

ro"a"e,Le+"Ri*" 0 %/

ai" 2%% ) +or lobal re)e" "o Ji)*

F2%%/

Add )"imulu) *ere

ed

edmodule


7/28

8 BIT BOOTH MULTIPLIER

module mul"i!lier(!rod' bu)4' m:' m!' :l' )"ar"./

ou"!u" #2;$%& !rod/

ou"!u" bu)4/

i!u" #$%& m:' m!/

i!u" :l' )"ar"/

re #$%& A' ' M/

re ,2/re #$%& :ou"/

3ire #$%& )um' diOere:e/

al3a4) 5(!o)ede :l.

bei

i+ ()"ar". bei A 80 A' ' ,2? 80 >A#&' A' ?/

ed:a)e


8/28

:ou" 80 :ou" P 2


9/28

I!u")

re #$%& m:/

re #$%& m!/

re :l/

re )"ar"/

u"!u")

3ire #2;$%& !rod/

3ire bu)4/

I)"a"ia"e "*e i" der Te)" (T.

mul"i!lier uu" (

!rod(!rod.'

bu)4(bu)4.'

m:(m:.'

m!(m!.'

:l(:l.'

)"ar"()"ar".

./

ii"ial bei

Ii"ialie I!u")

m: 0 %/

m! 0 %/

:l 0%/

)"ar" 0 2/



10/28

Add )"imulu) *ere

F; m: 0 ;/ m! 0 1/ )"ar" 0 2/

F; )"ar" 0 %/

F; m: 0 ;/ m! 0 1/ )"ar" 0 2/

F; )"ar" 0 %/

F% Ji)*/

ed

al3a4) F; :l 0 7:l/

edmodule


11/28

32 BIT FULL ADDER(CARRY RIPPLE ADDER)

module +ulladder,1@bi"(

i!u" #$%& a%'

i!u" #$%& a2'

i!u" #$%& a@'

i!u" #$%& a1'

i!u" #$%& b%'


12/28

i!u" #$%& b2'

i!u" #$%& b@'

i!u" #$%& b1'

ou"!u" #$%& )%'

ou"!u" #$%& )2'

ou"!u" #$%& )@'

ou"!u" #$%& )1'

ou"!u" :ou"'

i!u" :i

./

3ire 32'3@'31/

adder,bi" a(a%'b%':i')%'32./

adder,bi" b(a2'b2'32')2'3@./

adder,bi" :(a@'b@'3@')@'31./

adder,bi" d(a1'b1'31')1':ou"./

edmodule

SB MDLE( BIT LLADDER.

module adder,bi"(

i!u" #$%& a'

i!u" #$%& b'

i!u" :i'

ou"!u" re #$%& )um'

ou"!u" re :ou"

./

al3a4) 5(a'b':i.


13/28

>:ou"')um? 0 aPbP:i/

Edmodule

TEST BENCH

module +ulladder/

I!u")

re #$%& a%/

re #$%& a2/

re #$%& a@/

re #$%& a1/

re #$%& b%/

re #$%& b2/

re #$%& b@/

re #$%& b1/

re :i/

u"!u")

3ire #$%& )%/

3ire #$%& )2/

3ire #$%& )@/

3ire #$%& )1/

3ire :ou"/


+ulladder,1@bi" uu" (

a%(a%.'

a2(a2.'

a@(a@.'


14/28

a1(a1.'

b%(b%.'

b2(b2.'

b@(b@.'

b1(b1.'

)%()%.'

)2()2.'

)@()@.'

)1()1.'

:ou"(:ou".'

:i(:i.

./

ii"ial bei

Ii"ialie I!u")

a% 0 %/

a2 0 %/

a@ 0 %/

a1 0 %/

b% 0 %/

b2 0 %/

b@ 0 %/

b1 0 %/

:i 0 %/


F2%%/

F@%% a%0


15/28

F@%% a%0


16/28

i!u" #12$%& b'

i!u" :i'

ou"!u" re #12$%& )um'

ou"!u" re :ou"

./

al3a4) 5(a'b':i.

>:ou"')um? 0 aPbP:i/

Edmodule

TEST BENCH

module adder1@bi"/

I!u")

re #12$%& a/

re #12$%& b/

re :i/

u"!u")

3ire #12$%& )um/

3ire :ou"/


adder,1@bi" uu" (

a(a.'

b(b.'

:i(:i.'

)um()um.'

:ou"(:ou".


17/28

./

ii"ial bei

Ii"ialie I!u")

a 0 %/

b 0 %/

:i 0 %/


F2%%/

F@%% a01@


18/28

32 BIT CARRY LOOKAHED ADDER

module RARD,1@BIT(

i!u" #$%& a%'

i!u" #$%& a2'

i!u" #$%& a@'

i!u" #$%& a1'

i!u" #$%& b%'

i!u" #$%& b2'

i!u" #$%& b@'

i!u" #$%& b1'

i!u" :i'

ou"!u" #$%& )%'

ou"!u" #$%& )2'

ou"!u" #$%& )@'

ou"!u" #$%& )1'

ou"!u" :ou"

./

3ire 32'3@'31/


19/28

+ulladd a()%'32'a%'b%':i./

+ulladd b()2'3@'a2'b2'32./

+ulladd :()@'31'a@'b@'3@./

+ulladd d()1':ou"'a1'b1'31./

edmodule

TEST BENCH

module +or3ard,1@bi","b/

I!u")

re #$%& a%/

re #$%& a2/

re #$%& a@/

re #$%& a1/

re #$%& b%/

re #$%& b2/

re #$%& b@/

re #$%& b1/

re :i/

u"!u")

3ire #$%& )%/

3ire #$%& )2/

3ire #$%& )@/

3ire #$%& )1/

3ire :ou"/


20/28


RARD,1@BIT uu" (

a%(a%.'

a2(a2.'

a@(a@.'

a1(a1.'

b%(b%.'

b2(b2.'

b@(b@.'

b1(b1.'

:i(:i.'

)%()%.'

)2()2.'

)@()@.'

)1()1.'

:ou"(:ou".

./

ii"ial bei

Ii"ialie I!u")

a% 0 %/

a2 0 %/

a@ 0 %/

a1 0 %/

b% 0 %/

b2 0 %/

b@ 0 %/

b1 0 %/

:i 0 %/


21/28


F2%%/

F@%% a%0


22/28

module mai(

i!u" #$%& a'

i!u" #$%& b'

i!u" #$%& :' i!u" #$%& d'

i!u" #$%& e'

i!u" :l'

i!u" r)"'

ou"!u" #$%& ou"

./

3ire #$%& 32'3@'31'3'3;'36'3'3/

dO d2(a'r)"':l'32./

dO d@(b'r)"':l'3@./

mul m2(32'3@'31./

dO d1(31'r)"':l'3./

add a2(:'3'3;./

dO d(3;'r)"':l'36./

)ub )2(d'36'3./

dO d;(3'r)"':l'3./

)*i+" )@(e'3'ou"./

edmodule

SB MDLE R D

module dO(

i!u" #$%& di'

i!u" r)"'

i!u" :l'


23/28

ou"!u" re #$%& dou"

./

al3a4) 5(!o)ede :l'eede r)".

beii+(Ur)".

dou" 0


24/28

el)e

r@ 0 @


25/28

SBMDLE R SB

module )ub(

i!u" #$%& a' i!u" #$%& b'

ou"!u" re #$%& ou"

./

al3a4) 5(a'b.

ou" 0 a-b/

edmodule

SBMDLE R SHIT

module )*i+"(

i!u" #$%& a'

i!u" #$%& b'

ou"!u" re #$%& ou"

./

al3a4) 5(a'b.

ou" 0 b88a/

edmodule

TESTBENCH

module mai,"b/


26/28

I!u")

re #$%& a/

re #$%& b/re #$%& :/

re #$%& d/

re #$%& e/

re :l/

re r)"/

3ire #$%& ou"/


mai uu" (

a(a.'

b(b.'

:(:.'

d(d.'

e(e.'

:l(:l.'

r)"(r)".'

ou"(ou".

./

al3a4)

F@%% :l 0 7:l/

ii"ial bei

Ii"ialie I!u")

a 0 %/


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b 0 %/

: 0 %/

d 0 %/

e 0 %/:l 0 %/

r)" 0 2/

F@%% r)" 0 %/

F%% r)" 0 2/

F@%% a0


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vhdl-lab work file

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