vhdl file final

VHDL

LAB FILE

SUBMITTED TO SUBMITTED BY

Mr. Sandeep Choudhary Prabhjinder Singh AulakhAssistant Professor 2209139ECE Dept. ECE II

DEPARTMENT OF ELECTRONICS AND COMMUNUNICATION ENGINEERINGSWAMI DEVI DYAL INSTITUTE OF ENGINEERING & TECHNOLOGY

DISTT - PANCHKULA (BARWALA)HARYANA- 134118

INDEX

. .

Sr. no Program Page no Date Remark

1 VHDL code for 2:4 Decoder 3

2 VHDL code for 4:1 Multiplexer 4

3 VHDL code for 1:4 Demultiplexer 6

4 VHDL code for Full Adder 8

5 VHDL code for Half Adder 9

6 VHDL code for Half Subtractor 10

7 VHDL code for D-FF 11

8 VHDL code for T-FF 12

9 VHDL Code for Parity Generator 13

10 VHDL Code for 1 bit comparator 15

11 VHDL code for up-down counter 16

12 VHDL code for AND , OR , NAND and NOT gate

17

2

EXPERIMENT NO. : 1

AIM: To implement VHDL code for 2:4 Decoder.Apparatus used : Xilinx , Modelsim Software.

Code:

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dec is Port ( a : in STD_LOGIC; b : in STD_LOGIC;

e : in STD_LOGIC; z1 : out STD_LOGIC; z2 : out STD_LOGIC; z3 : out STD_LOGIC; z4 : out STD_LOGIC);end dec;

architecture data of dec is signal abar,bbar:STD_LOGIC;begin

z1 <= not (abar and bbar and e); abar <= not a;bbar <= not b;z2 <= not (abar and b and e);z3 <= not (a and bbar and e);z4 <= not (a and b and e);

end data;

Result : 2:4 Decoder using VHDL has been implemented.

RTL SCHEMATICS

3

EXPERIMENT NO. 2

AIM: To implement VHDL code for 4:1 Multiplexer.

Apparatus used : Xilinx , Modelsim Software.

Code:

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity mux is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; d : in STD_LOGIC; s0 : in STD_LOGIC; s1 : in STD_LOGIC; z : out STD_LOGIC);end mux;

architecture Behavioral of mux isbegin

process(a,b,c,d,s0,s1)begin

if s0='0' and s1='0' thenz<=a;

elsif s0='0' and s1='1' thenz<=b;

elsif s0='1' and s1='0' thenz<=c;

elsez<=d;end if;

4

end process;end Behavioral;

Result: 4:1 Multiplexer has been implemented using VHDL code.

RTL SCHEMATICS

4:1 Multiplexer

5

EXPERIMENT NO. : 3

AIM: To implement VHDL code for 1:4 Demultiplexer.


Code:

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity demux is Port ( x : in STD_LOGIC;

s0 : in STD_LOGIC; s1 : in STD_LOGIC;

y0 : out STD_LOGIC; y1 : out STD_LOGIC; y2 : out STD_LOGIC; y3 : out STD_LOGIC);end demux;

architecture Behavioral of demux is

beginprocess(x,s0,s1)

beginif s0='0' and s1='0' then

y0<=x;elsif s0='0' and s1='1' then

y1<=x;elsif s0='1' and s1='0' then

y2<=x;

6

elsey3<=x;

end if;end process;

end Behavioral;

Result: 1:4 Demultiplexer has been implemented using VHDL code.

RTL SCHEMATICS

4:1 Demultiplexer

7

EXPERIMENT NO. : 4

AIM: To implement VHDL code for Full Adder.


Code:


entity FA is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; s : out STD_LOGIC; cr : out STD_LOGIC);end FA;

architecture data of FA is

begins <= a xor b xor c;cr <= (a and b)or(b and c)or(a and c);

end data;

Result : Full adder has been designed using VHDL code.

RTL SCHEMATICS

8

EXPERIMENT NO. : 5

AIM: To implement VHDL code for Half Adder.


Code:


entity HA is Port ( a : in STD_LOGIC; b : in STD_LOGIC; s : out STD_LOGIC; c : out STD_LOGIC);end HA;

architecture data of HA is

begins <= a xor b;c <= a and b;

end data;

RESULT: Half adder implemented using VHDL code.

RTL SCHEMATICS

9

EXPERIMENT NO. : 6

AIM: To implement VHDL code for Half subtractor.


Code:

Library IEEE;Use IEEE.STD_LOGIC_1164.ALL;

Entity halfsubtractor is Port( a: in std_logic; b : in std_logic;

diff : out std_logic;borrow : out std_logic);

end halfsubtractor;

architecture behavioral of halfsubtractor is

begindiff <= a xor b;borrow<= (not a) and b;

end behavioral;

Result: Half subtractor implemented using VHDL code.

RTL SCHEMATICS

10

EXPERIMENT NO. : 7

AIM: To implement VHDL code for D-FF.


Code:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity dff is Port ( d : in STD_LOGIC; clk : in STD_LOGIC; reset : in STD_LOGIC; q : buffer STD_LOGIC);end dff;architecture Behavioral of dff isbegin

process(d,clk)variable temp :STD_LOGIC;

beginif clk='1' and clk'event then

temp := d;else

temp := q;end if;

q<=temp;end process;

end Behavioral;

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Result: D-FF implemented using VHDL

RTL SCHEMATICS

EXPERIMENT NO. : 8

AIM: To implement VHDL code for T-FF.


Code:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity tff is Port ( t : in STD_LOGIC; clk : in STD_LOGIC; q : buffer STD_LOGIC);end tff;architecture behavioral of tff isbegin

process(t,clk)variable temp:STD_LOGIC;

beginif clk='1' and clk'event and t='1' then

temp:= not q;else

temp:= q;end if;

q<=temp;end process;

end behavioral;

Result : T-FF implemented using VHDL code.

12

RTL SCHEMATICS

EXPERIMENT NO. : 9

AIM: To implement VHDL code for Parity Generator.


Code:


entity parity is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; d : in STD_LOGIC; e : in STD_LOGIC; f : in STD_LOGIC; g : in STD_LOGIC; h : in STD_LOGIC; even : buffer STD_LOGIC; odd : out STD_LOGIC);end parity;

architecture DATA of parity issignal i,j,k,l,m,n:STD_LOGIC;

begin

13

i<=a xor b;j<=c xor d;k<=e xor f;l<=g xor h;m<=i xor j;n<=k xor l;even<=m xor n;odd<=not even;

end DATA;

Result: One bit parity generator implemented using VHDL code.

RTL SCHEMATICS

14

One bit Parity generator

EXPERIMENT NO. : 10

AIM : VHDL code for 1 Bit comparator in Behavioral Modeling style


Code:


entity Comparator is Port ( A : in STD_LOGIC; B : in STD_LOGIC; EQL : out STD_LOGIC; LT : out STD_LOGIC; GT : out STD_LOGIC);end Comparator;

architecture Behavioral of Comparator is

begin

15

EQL <= NOT (A xor B);LT <= (not a) and B;GT <= A and (Not B);

end Behavioral;

Result: One bit comparator implemented using VHDL code in Behavioral style.

RTL SCHEMATICS

EXPERIMENT NO. : 11

Aim: To implement Modulo Synchronous Up-Down Counter using VHDL.


Code:library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter is

port(C, CLR, UP_DOWN : in std_logic; Q : out std_logic_vector(3 downto 0));

end counter;architecture archi of counter is

signal tmp: std_logic_vector(3 downto 0); begin

process (C, CLR) begin

if (CLR='1') thentmp <= "0000";

elsif (C'event and C='1') then

16

if (UP_DOWN='1') thentmp <= tmp + 1;

elsetmp <= tmp - 1;

end if;end if;end process;

Q <= tmp;end archi;

Result : Modulo synchronous Up-Down Counter implemented using VHDL.

RTL Schematics

EXPERIMENT : 12

Aim: To implement AND , OR , NAND and NOT gate using VHDL.

apparatus used : Xilinx , Modelsim Software.

Code:

1.1 AND GATE

library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;

entity AND2 isport(A,B : in std_logic;C : out std_logic);

end AND2;architecture archi of AND2 isbegin

C <= A and B;

17

end archi;

Result:

1.2 OR GATE

Code:


entity or1 isport(A,B : in std_logic;C : out std_logic);end or1;

architecture archi of or1 isbegin

C <= A or B;end archi;

Result:

1.3 NAND GATE

Code:library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;

entity nand1 isport(A,B : in std_logic;

18

C : out std_logic);end nand1;

architecture archi of nand1 is

beginC <= A nand B;

end archi;

Result:

1.4 NOT GATE

Code:


entity NOT1 isport(A : in std_logic;B : out std_logic);end NOT1;

architecture archi of NOT1 isbegin

B<= not A;end archi;

Result:

19

RESULT : AND , OR , NAND and NOT gate using VHDL has been implemented.

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vhdl file final

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