vhdl lab manua1l (1)

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DIGITAL SYSTEMS DESIGN USING VHDL

Subject Code: EC 304 Faculty: Ms.SSM

LIST OF EXPERIMENTS

CYCLE – I

1. Logic gates

2. Combinational circuits (comparators, Multiplexers, Decoders, Encoders)

3 Arithmetic circuits,

4. ALU (32-bit)

CYCLE – II

5. All Flip-Flops.

6 Sequential networks (All types counters, control circuits, shift registers, PRBS Generators,

7. DAC

8 7 Segment LED/ LCD Display

CYCLE – III

9 Stepper motor speed and direction control

10 DC Motor speed control

11. Hex keypad

VHDL LAB {PROGRAMMING}

1. Write VHDL code to realize all gates. AND gate

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library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity and1 is Port ( a : in bit;b : in bit;y : out bit);end and1;architecture Behavioral of and1 isbeginy<=a and b;end Behavioral;LOGIC Symbol:

TRUTH Table:

SIMULATION Output:

OR Gatelibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity orgate is Port ( AIN : in STD_LOGIC; BIN : in STD_LOGIC; YOUT : out STD_LOGIC);end orgate;architecture Behavioral of orgate isbeginYOUT <= AIN or BIN;end Behavioral;

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Logic Symbol:

TRUTH Table:

SIMULATION Output:

NOT Gatelibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity notgate is Port ( AIN : in STD_LOGIC; YOUT : out STD_LOGIC);end notgate;architecture Behavioral of notgate isbeginYOUT <= NOT AIN;end Behavioral;Logic Symbol:

Truth Table:AIN YOUT0 11 0

SIMULATION Output:

NOR Gatelibrary IEEE;

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use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity norgate is Port ( AIN : in STD_LOGIC; BIN : in STD_LOGIC; YOUT : out STD_LOGIC);end norgate;architecture Behavioral of norgate isbeginYOUT <= AIN NOR BIN;end Behavioral;

Logic Symbol:

Truth Table:

SIMULATION Output:

NAND Gatelibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity nandgate is Port ( AIN : in STD_LOGIC; BIN : in STD_LOGIC; YOUT : out STD_LOGIC);end nandgate;architecture Behavioral of nandgate isbeginYOUT <= AIN NAND BIN;end Behavioral;

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Logic symbol:

Truth Table:

SIMULATION Output:

XOR Gatelibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity xorgate is Port ( AIN : in STD_LOGIC; BIN : in STD_LOGIC; YOUT : out STD_LOGIC);end xorgate;architecture Behavioral of xorgate isbeginYOUT <= AIN XOR BIN;end Behavioral;Logic symbol:

Truth Table:

SIMULATION Output:

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XNOR Gatelibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity xnorgate is Port ( AIN : in STD_LOGIC; BIN : in STD_LOGIC; YOUT : out STD_LOGIC);end xnorgate;architecture Behavioral of xnorgate isbeginYOUT <= AIN XNOR BIN;end Behavioral;Logic Symbol:

Truth Table:

SIMULATION Output:

ALL Gateslibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity allgates is Port ( a : in BIT; b : in BIT; c,d,e,f,g,h,i: out BIT);end allgates;architecture Behavioral of allgates is

LOGIC

GATES

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beginc <= NOT A_in;d <= B_in NAND A_in;e <= B_in AND A_in;f <= B_in NOR A_in;g <= B_in OR A_in;h <= B_in XNOR A_in;i <= B_in XOR A_in;end Behavioral;Truth Table:

a B c d e f g h i0 0 0 0 1 1 1 0 10 1 0 1 1 1 0 1 01 0 0 1 0 1 0 1 01 1 1 1 0 0 0 0 1

SIMULATION Output:

#PACE: Start of PACE I/O Pin AssignmentsUCF For ALL Gates:NET “a”LOC=”p74”;NET “b”LOC=”p76”;NET “c”LOC=”p84”;NET “d”LOC=”p85”;NET “e”LOC=”p86”;NET “f”LOC=”p87”;NET “g”LOC=”p89”;NET “h”LOC=”p90”;NET “i”LOC=”p92”;

2. Write a VHDL Program For The Following Combinational Designs:Decoder 2 to 4library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

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use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dec is

Port ( sel : in std_logic_vector(1 downto 0);

e:in std_logic;

y : out std_logic_vector(3 downto 0)); sel0

end dec; sel1

y2

architecture Beh of dec is

signal m:std_logic_vector(2 downto 0);

begin

m<= e & sel;

y <="0001" when m="100" else

"0010" when m="101" else

"0100" when m="110" else

"1000" when m="111" else

"0000";

end Beh;

Truth table:E Sel1 Sel0 Y3 Y2 Y1 Y01 0 0 0 0 0 11 0 1 0 0 1 01 1 0 0 1 0 01 1 1 1 0 0 00 X X 0 0 0 0

SIMULATION Output:

UCF File For Decoder:NET "e" LOC = "p74";NET “sel<0>"I”LOC=”p76”;

2 to 4

Decoder

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NET “sel<1>"”LOC=”p77”;NET “Y”LOC=”p84”;NET “Y”LOC=”p85”;NET “Y”LOC=”p86”;NET “Y”LOC=”p87”;

8 to 3 ENCODER Without Prioritylibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity enc_np is Port ( i : in STD_LOGIC_VECTOR (7 downto 0); y : out STD_LOGIC_VECTOR (2 downto 0));end enc_np;architecture Behavioral of enc_np isbeginy<="000" when i="00000001" else "001" when i="00000010" else

"010" when i="00000100" else"011" when i="00001000" else"100" when i="00010000" else"101" when i="00100000" else"110" when i="01000000" else"111" when i="10000000" ;

end Behavioral;Truth Table:i7 i6 i5 i4 i3 i2 i1 i0 Y2 Y1 Y00 0 0 0 0 0 0 1 0 0 00 0 0 0 0 0 1 0 0 0 10 0 0 0 0 1 0 0 0 1 00 0 0 0 1 0 0 0 0 1 10 0 0 1 0 0 0 0 1 0 00 0 1 0 0 0 0 0 1 0 10 1 0 0 0 0 0 0 1 1 01 0 0 0 0 0 0 0 1 1 1X X X X X X X X 0 0 0

Logic Symbol:

SIMULATION Output:

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UCF For 8-3 Encoder:NET “I”LOC=”p74”;NET “I”LOC=”p76”;NET “I”LOC=”p77”;NET “I”LOC=”p79”;NET “I”LOC=”p78”;NET “I”LOC=”p82”;NET “I”LOC=”p80”;NET “I”LOC=”p83”;NET “Y”LOC=”p100”;NET “Y”LOC=”p102”;NET “Y”LOC=”p124”;

Encoder with prioritylibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity Encp is Port ( s : in STD_LOGIC; i : in STD_LOGIC_VECTOR (7 downto 0); y : out STD_LOGIC_VECTOR (2 downto 0));end Encp;architecture Behavioral of Encp isbeginy<="000" when (s & i="0--------") else

"000" when (s & i="100000001") else"001" when (s & i="10000001-") else"010" when (s & i="1000001--") else"011" when (s & i="100001---") else"100" when (s & i="10001----") else"101" when (s & i="1001-----") else"110" when (s & i="101------") else"111" when (s & i="11-------");

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end Behavioral;Truth Table:S i7 i6 i5 i4 i3 i2 i1 i0 Y2 Y1 Y01 X X X X X X X X 1 1 10 1 1 1 1 1 1 1 1 1 1 10 1 1 1 1 1 1 1 0 1 1 10 1 1 1 1 1 1 0 X 1 1 00 1 1 1 1 1 0 X X 1 0 10 1 1 1 1 0 X X X 1 0 00 1 1 1 0 x X X X 0 1 10 1 1 0 X X X X X 0 1 00 1 0 X X X X X X 0 0 10 0 X X X X X X X 0 0 0

SIMULATION Output:

Logic Symbol:

MUX 8 to 1library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity mux8_1 is Port ( s : in STD_LOGIC_VECTOR (2 downto 0); i : in STD_LOGIC_VECTOR (7 downto 0); e : in STD_LOGIC;

y : out STD_LOGIC);end mux8_1;architecture Behavioral of mux8_1 isbeginwith s select

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y<=i(0) and e when "000", i(1) and e when "001",

i(2) and e when "010",i(3) and e when "011",i(4) and e when "100",i(5) and e when "101",i(6) and e when "110",i(7) and e when "111",'0' when others;

end Behavioral;

Truth table:S(2) S(1) S(0) Y0 0 0 i(0)0 0 1 i(1)0 1 0 i(2)0 1 1 i(3)1 0 0 i(4)1 0 1 i(5)1 1 0 i(6)1 1 1 i(7)

Logic Symbol:

SIMULATION Output:

UCF For 8-1 MUX:NET “S”LOC=”p76”;NET “S”LOC=”p77”;NET “S”LOC=”p79”;NET “I”LOC=”p78”;

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NET “I”LOC=”p82”;NET “I”LOC=”p80”; NET “I”LOC=”p83”;NET “I”LOC=”p100”;NET “I”LOC=”p84”;NET “I”LOC=”p85”;NET “I”LOC=”p86”;NET “I”LOC=”p102”;NET “Y”LOC=”p124”;

DEMUX 1 to 4library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity demux1to4 is Port ( i : in STD_LOGIC; s : in STD_LOGIC_VECTOR(1 DOWNTO 0); y : out STD_LOGIC_VECTOR(3 DOWNTO 0));end demux1to4;architecture Behavioral of demux1to4 isbeginprocess(i,s)

begincase s is

when "00" => y(0)<= i;when "01" => y(1)<= i;when "10" => y(2)<= i;when "11" => y(3)<= i;when others => y <= "0000";

end case;end process;

end Behavioral;Logic symbol:

Truth table:S(1) S(0) Y(3) Y(2) Y(1) Y(0)0 0 0 0 0 10 1 0 0 1 01 0 0 1 0 01 1 1 0 0 0

SIMULATION Output:

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UCF For 1-4 DEMUX:NET “I”LOC=”p79”;NET “E”LOC=”p74”;NET “S”LOC=”p77”;NET “S”LOC=”p76”;NET “Y”LOC=”p87”;NET “Y”LOC=”p86”;NET “Y”LOC=”p85”;NET “Y”LOC=”p84”;

BINARY To GRAY:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity b2g is Port ( b : in STD_LOGIC_VECTOR(3 downto 0); g : out STD_LOGIC_VECTOR(3 downto 0));end b2g;architecture Behavioral of b2g isbegin

g(3) <= b(3);g(2) <= b(3) XOR b(2);g(1) <= b(2) XOR b(1);g(0) <= b(1) XOR b(0);

end Behavioral;Logic Symbol:

Truth Table:B3 B2 B1 B0 G3 G2 G1 G00 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 10 0 1 1 0 0 1 00 1 0 0 0 1 1 0

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0 1 0 1 0 1 1 10 1 1 0 0 1 0 10 1 1 1 0 1 0 01 0 0 0 1 1 0 01 0 0 1 1 1 0 11 0 1 0 1 1 1 11 0 1 1 1 1 1 01 1 0 0 1 0 1 01 1 0 1 1 0 1 11 1 1 0 1 0 0 11 1 1 1 1 0 0 0

SIMULATION Output:

UCF FOR BINARY TO GRAY:NET “b<0>"LOC=”p74”; NET “b<0>”LOC=”p76”;NET “b<0>”LOC=”p77”;NET “b<0>”LOC=”p79”;NET “g<0>”LOC=”p84”;NET “g<0>”LOC=”p85”;NET “g<0>”LOC=”p86”; NET “g<0>”LOC=”p87”;Comparator(1 bit)library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL; Black box

entity compr1bit is L Port ( a,b : in std_logic; a L,E,G : out std_logic); Eend compr1bit; b

Garchitecture Behavioral of compr1bit is

begin process(a,b) begin L<=(not a) and b; E<= not( a xor b);

1bit

Comparator

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G<= a and (not b); end process ;end Behavioral;

TruthtableA B L E G0 0 0 1 00 1 1 0 01 0 0 0 11 1 0 1 0

output#PACE: Start of Constraints generated by PACE

#PACE: Start of PACE I/O Pin AssignmentsNET "a" LOC = "p74" ;NET "b" LOC = "p75" ;NET "E" LOC = "p86" ;NET "G" LOC = "p85" ;NET "L" LOC = "p84" ;

Comparator(4 bit)

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity compart4bit is Port ( a,b : in std_logic_vector(3 downto 0); x,y,z : out std_logic); Black boxend compart4bit;

a(3 to 0) xarchitecture Behavioral of compart4bit is

a(3 to 0) y4bit

Comparator

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begin process (a,b)

begin if a > b then x<='1'; elsif a < b then y<='1'; else z<='1'; end if ; end process; end Behavioral;

output Greater than Equal to Less than

UCF FOR COMPARATOR:NET “A<0>”LOC=”p74”;NET “A<1>”LOC=”p76”;NET “A<2>”LOC=”p77”;NET “A<3>”LOC=”p79”;NET “AEB”LOC=”p84”;NET “AGB”LOC=”p85”;NET “ALB”LOC=”p86”;NET “B<0>”LOC=”p78”;NET “B<1>”LOC=”p87”;NET “B<2>”LOC=”p89”;NET “B<3>”LOC=”p90”;

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3. Write a VHDL code for arithmetic circuits: Data flowlibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

Black boxentity fulladr is Port ( a,b,cin : in std_logic; sum,cout : out std_logic);end fulladr;

architecture data of fulladr is

begin sum<=a xor b xor cin; cout<= ( a and b) or ( b and cin) or ( cin and a);end data;

Truth tableINPUTS OUTPUTS

a b cin SUM Cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Sum output Cout (carry) output 4. Write a model for 2 BIT ALU using the conditions mentioned below:

FULL

ADDER

Sum

Cout

a

b

c

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ALU should use combinational logic to calculate an output based on the op-code input. ALU should pass the result to the out buswhen enable line is high and tri-state the out bus when

enable line is low. ALU should decode the input op-code according to the given in example below.

OP-CODE ALU Operation

1 A+B2 A-B3 A Complement4 A*B5 A AND B6 A OR B7 A NAND B8 A XOR B

VHDL Code:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity alu_2bit is Port ( a,b : in STD_LOGIC_VECTOR (1 downto 0); s : in STD_LOGIC_VECTOR (2 downto 0); y : out STD_LOGIC_VECTOR (3 downto 0));end alu_2bit;architecture Behavioral of alu_2bit isbeginprocess(a,b,s)begincase s iswhen "000"=>y<=a+b;when "001"=>y<=a-b;when "010"=>y<=a*b;when "011"=>y<=not a;when "100"=>y<=a and b;when "101"=>y<=a or b;when "110"=>y<=a nand b;when others=>y<=a xor b;end case;end process;end Behavioral;LOGIC Symbol:

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Truth Table:Operation S(2:0) a b Ya+b 000 1111 0000 00001111a-b 001 1110 0010 00001100a or b 010 1111 1000 00001111a and b 011 1001 1000 00001000nota 100 1111 0000 11110000a1*b1 101 1111 1111 11100001a nand b 110 1111 0010 11111101a xor b 111 0000 0100 00000100

UCF File:NET "a[0]" LOC = "p74" ;NET "a[1]" LOC = "p76" ;NET "b[0]" LOC = "p77" ;NET "b[1]" LOC = "p79" ;NET "s[0]" LOC = "p78" ;NET "s[1]" LOC = "p82" ;NET "s[2]" LOC = "p80" ;NET "y[0]" LOC = "p84" ;NET "y[1]" LOC = "p85" ;NET "y[2]" LOC = "p86" ;NET "y[3]" LOC = "p87" ;

5.Develop the VHDL Code for the following flip-flops, SR, D, JK, T .D-Flip Floplibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;entity dflipflop is Port ( clk,d,reset: in STD_LOGIC; q,qbar: buffer STD_LOGIC);end dflipflop;architecture Behavioral of dflipflop isbeginprocess(d,clk)beginif(clk='1') then if(reset='0') then q<=d;

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qbar<=not q; else q<='0';

qbar<='1';end if;

elseq<='0';qbar<='1';end if;end process;end Behavioral;Logic Symbol

Truth Table:reset Clk D Q Qb1 1 1 0 10 1 1 1 00 1 0 0 1

0 0 X 0 1

SIMULATION Output:

SR Flip Floplibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;

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use IEEE.STD_LOGIC_UNSIGNED.ALL;entity SR_flipflop is Port ( s,r : in STD_LOGIC; q,qb : buffer STD_LOGIC; clk : in STD_LOGIC);end SR_flipflop;architecture Behavioral of SR_flipflop isbeginprocess(clk,s,r)beginif(clk ' event and clk='1') thenif (s='0' and r='0')thenq<=q;elsif(s='0' and r='1')thenq<='0';elsif (s='1' and r='0')thenq<='1';elsif (s='1' and r='1')thenq<='0';end if;end if;qb<=not q;end process;end Behavioral;

Logic Symbol:

Truth Table:Clk S R Q QbX X X 0 11 0 0 Qb Qbprevious 1 0 1 0 11 1 0 1 01 1 1 1 1

SIMULATION Output:

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JK Flip Flop:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity JK_flipflop is Port ( j,k,clk : in STD_LOGIC; q,qb: buffer STD_LOGIC);end JK_flipflop;

architecture Behavioral of JK_flipflop is

beginprocess(j,k,clk)beginif clk='1' and clk' event thencase ('j'&'k')iswhen"00"=>q<=q;when"01"=>q<=j;when"10"=>q<=k;when others=>q<=not q;end case;end if;end process;qb<= not q;end Behavioral;

LOGIC Symbol:

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Truth Table:Clk J K Q Qb1 0 0 Previous state1 0 1 0 11 1 0 1 01 1 1 Qb QNo+ve egde - - Previous state- - - 0 1

SIMULATION Output:

T flip flopVHDL code:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity t is Port ( clk,t : in STD_LOGIC; q : inout STD_LOGIC; qbar : out STD_LOGIC);end t;architecture Behavioral of t isbeginprocess(clk)beginif(clk'event and clk='1')then

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if(t='1')thenq<=not q;elseq<=q;end if;end if;end process;qbar<=not q;end Behavioral;

LOGIC Symbol:

Truth Table:T Clk q0 1 q1 1 qbX No +ve edge Previous stateX X 0

Simulation Output:

6.Sequential networks

Binary Synchronous up counter

library IEEE;




entity sync_counter is

port( clk: in STD_LOGIC;

RESET: in STD_LOGIC;

COUNT: buffer STD_LOGIC_VECTOR( 3 DOWNTO 0):0000);

end sync_counter;

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architecture up_count of sync_counter is

signal clk_int:STD_LOGIC_VECTOR( 25 DOWNTO 0);

signal z:std_logic;

begin

process (CLK)

begin

if rising_edge (CLK) then

clk_int<=clk_int+1;

end if;

z<=clk_int(20);

end process;

begin

process(z,RESET)

begin

if rising_edge (z) then

if(reset=’1’)then

count<=”0000”;

else

count<=count+’1’;

end if;

end if;

end process;

end up_count;

Binary synchronous Down Cuunter

library IEEE;





port( CLK: in STD_LOGIC;



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end sync_counter;

architecture down_count of sync_counter is


signal z:std_logic;

begin

process (CLK)

begin


clk_int<=clk_int+’1’;

end if;

z<=clk_int(20);

end process;

begin

process(z,RESET)

begin



count<=”0000”;

else

count<=count-’1’;

end if;

end if;

end process;

end down_count;

BCD synchronous up counter

library IEEE;








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end sync_counter;



signal z:std_logic;

begin

process (CLK)

begin


clk_int<=clk_int+1;

end if;

z<=clk_int(20);

end process;

begin

process(z,RESET)

begin



count<=”0000”;

else


elsif(count=”1010”)then

count<=”0000”

end if;

end if;

end process;

end up_count;

BCD synchronous down counter

library IEEE;





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end sync_counter;



signal z:std_logic;

begin

process (CLK)

begin


clk_int<=clk_int+1;

end if;

z<=clk_int(20);

end process;

begin

process(z,RESET)

begin



count<=”0000”;

else



count<=”1001”

end if;

end if;

end process;

end up_count;

Asynchronous reset binary up counter

library IEEE;


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entity async_counter is




end sync_counter;

architecture up_count of async_counter is


signal z:std_logic;

begin

process (CLK)

begin


clk_int<=clk_int+1;

end if;

z<=clk_int(20);

end process;

begin

process(z,RESET)

begin



count<=”0000”;

else


end if;

end if;

end process;

end up_count;

Asynchronous reset binary down counter

library IEEE;


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end sync_counter;

architecture down_count of sync_counter is


signal z:std_logic;

begin

process (CLK)

begin


clk_int<=clk_int+’1’;

end if;

z<=clk_int(20);

end process;

begin

process(z,RESET)

begin



count<=”0000”;

else


end if;

end if;

end process;

end down_count;

Asynchronous reset bcd up counter

library IEEE;


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entity async_counter is




end sync_counter;



signal z:std_logic;

begin

process (CLK)

begin


clk_int<=clk_int+1;

end if;

z<=clk_int(20);

end process;

begin

process(z,RESET)

begin



count<=”0000”;

else



count<=”0000”

end if;

end if;

end process;

end up_count;

Asynchronous reset binary down counter

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library IEEE;








end sync_counter;



signal z:std_logic;

begin

process (CLK)

begin


clk_int<=clk_int+1;

end if;

z<=clk_int(20);

end process;

begin

process(z,RESET)

begin



count<=”0000”;

else



count<=”1001”

end if;

end if;

end process;

end down_count;

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UCF file(User constraint file)

NET "clk" LOC = "p52" ;

NET "count[0]" LOC = "p87" ;




NET "reset" LOC = "p74" ;

Logic Symbol:

Simulation Output:

Synchronous any sequence counter

library IEEE;







Q,qb: buffer STD_LOGIC_VECTOR( 2 DOWNTO 0));

end sync_counter;



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signal z:std_logic;

begin

process (CLK)

begin


clk_int<=clk_int+1;

end if;

z<=clk_int(20);

end process;

begin

process(z,RESET)

begin



if(q=”000”)then

q<=”010”;

elsif(q=”010”)then

q<=”100”;


q<=”110”;


q<=”000”;

else

q<=”000”;

else

q<=”000”;

end if;

end if;

qb<=not q;

end process;

end any_count;

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INTERFACING PROGRAMS1. Write VHDL code to generate different waveforms (sawtooth, sine wave, square, triangle, ramp etc) using DAC change the frequency and amplitude.

SAWTOOTH


entity sawtooth is Port ( clk,rst : in std_logic; dac : out std_logic_vector(0 to 7));end sawtooth;

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architecture Behavioral of sawtooth is signal temp:std_logic_vector(3 downto 0); signal cnt:std_logic_vector( 0 to 7);

begin process(clk)beginif rising_edge(clk) thentemp<= temp+'1';end if; end process; process (temp(3),cnt) begin if rst='1' then cnt<="00000000"; elsif rising_edge(temp(3)) then cnt<= cnt+1; end if; end process; dac<=cnt;

end Behavioral;

SQUARElibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity squarewg is Port ( clk,rst : in std_logic; dac : out std_logic_vector(0 to 7));end squarewg;

architecture Behavioral of squarewg issignal temp:std_logic_vector(3 downto 0);signal cnt:std_logic_vector(0 to 7);signal en: std_logic;

beginprocess(clk)begin

if rising_edge(clk) then temp<= temp+'1';end if;

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end process;

process(temp(3)) begin if rst='1' then cnt<="00000000"; elsif rising_edge (temp(3)) then if cnt< 255 and en='0' then cnt<=cnt+1; en<='0'; dac<="00000000"; elsif cnt=0 then en<='0';

else en<='1';cnt<=cnt-1;dac<="11111111";end if;end if;end process;end Behavioral;

TRIANGLE


entity triangwg is Port ( clk,rst : in std_logic; dac : out std_logic_vector(0 to 7));end triangwg;

architecture Behavioral of triangwg issignal temp: std_logic_vector( 3 downto 0);signal cnt: std_logic_vector(0 to 8);signal en:std_logic;beginprocess(clk)beginif rising_edge(clk) then temp<= temp+1;end if; end process; process( temp(3)) begin if rst='1' then cnt<="000000000";

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elsif rising_edge(temp(3)) then cnt<=cnt+1; if cnt(0)='1' then dac<=cnt(1 to 8); else dac<= not(cnt( 1 to 8)); end if; end if; end process; end Behavioral;

RAMP


entity rampwg is Port ( clk,rst : in std_logic; dac : out std_logic_vector(0 to 7));end rampwg;

architecture Behavioral of rampwg is signal temp:std_logic_vector(3 downto 0); signal cnt:std_logic_vector( 0 to 7);

beginprocess(clk)beginif rising_edge(clk) thentemp<= temp+'1';end if; end process; process (temp(3),cnt) begin if rst='1' then cnt<="00000000"; elsif rising_edge(temp(3)) then

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cnt<= cnt+15; end if; end process; dac<=cnt; end Behavioral;

SINE WAVE


entity sinewave is Port ( clk,rst : in std_logic; dac_out : out std_logic_vector(0 to 7));end sinewave;

architecture Behavioral of sinewave is signal temp: std_logic_vector(3 downto 0); signal counter: std_logic_vector(0 to 7); signal en: std_logic;begin

process(clk) is begin if rising_edge (clk) then

temp<= temp+'1';end if;end process;

process(temp(3)) isbegin

if rst='1' then counter<="00000000";elsif rising_edge(temp(3)) then if counter<255 and en='0' then counter<= counter+31; en<='0'; elsif counter=0 then en<='0'; else en<='1'; counter<= counter-31; end if; end if; end process; dac_out<= counter;

4.DAC

NET "CLK" LOC="p18";

NET "dac_out<0>" LOC="p27";






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end Behavioral;

Procedure: 1) Make connection between FRC 5 and FPGA and DAC connector of VTU card 2.2) Make the connection between FRC 1 of FPGA board to the DIP switch connector of VTU card 2.3) Then open xilinx impact s/w, select slave serial mode and select the respective bit file and click program.4) Make the reset switch on.

Result: The waveform obtained Ramp, Saw tooth, Triangular, Sine and Square waves are as per the graph.

2. Write a VHDL code for hex keypad:

Library IEEE;use IEEE.std_logic_1164.all;use IEEE.STD_LOGIC_UNSIGNED.all;USE WORK.LCD_GRAP.ALL;

entity HEXKEY_lcd is port ( CLK: in STD_LOGIC; -- 16 MHz clock RESET: in STD_LOGIC; -- master reset pin lcd_rw : out std_logic;

lcd_select : out std_logic; lcd_enable : out std_logic;

ROW: in STD_LOGIC_VECTOR(0 to 3); -- this are the row lines lcd_data: out STD_LOGIC_VECTOR (7 downto 0); -- gives registered data output

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COL: inout STD_LOGIC_VECTOR(0 to 3) );end HEXKEY_lcd;

architecture HEXKEY_BEH of HEXKEY_lcd is

type KEYPAD_STATE_TYPE is (WAIT_R_0, C3, C2, C1, C0, FOUND, SAMPLE, WAIT_R_1); -- state namesTYPE STATE_TYPE IS (initial,display,clear,location,putchar);

SIGNAL state,next_state: STATE_TYPE;

-- Clear screen.constant CLR: std_logic_vector(7 downto 0) := "00000001";-- Display ON, without cursor.constant DON: std_logic_vector(7 downto 0) := "00001100";-- Function set for 8-bit data transfer and 2-line displayconstant SET: std_logic_vector(7 downto 0) := "00111000";

--frequency divider

--signal c: std_logic_vector(7 downto 0);

constant big_delay: integer :=16;constant small_delay: integer :=2;constant reg_setup: integer :=1;

signal CS, NS: KEYPAD_STATE_TYPE; -- signals for current and next states

signal DIV_REG: STD_LOGIC_VECTOR (16 downto 0); -- clock divide registersignal DCLK,DDCLK: STD_LOGIC; -- this has the divided clock.signal COL_REG_VALUE: STD_LOGIC_VECTOR (0 to 3);signal R1: STD_LOGIC; -- row detection signalsignal KEY_VALUE: STD_LOGIC_VECTOR (7 downto 0);signal DATA: STD_LOGIC_VECTOR (7 downto 0);

begin

--CLK_OUT <= DCLK;R1 <= ROW(3) or ROW(2) or ROW(1) or ROW(0);

------------------------------------------------------------------------------------------------------------------------------- BEGINING OF FSM1 (KEYPAD SCANNER) ------------------------------------

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--------------------------------------------------------------------------------------------------- SYNC_PROC: process (DCLK, RESET, KEY_VALUE) -- This is the synchronous part begin if (RESET = '0') then -- you must have a reset for fsm to synthesize properly CS <= WAIT_R_0; elsif (DCLK'event and DCLK = '1') then

CS <= NS; end if;

end process; COMB_PROC: process (CS, R1, COL_REG_VALUE) -- This is the combinational part begin case CS is--------------------------------------------------------------------------------------------------- when WAIT_R_0 => -- waits till a button is pressed COL <= "1111"; -- keep all columns activated if R1 = '1' then -- a button was pressed. but which one? NS <= C3; -- let's find out else NS <= WAIT_R_0; end if;--------------------------------------------------------------------------------------------------- when C3 => -- COL <= "0001"; -- activate column 3 if R1 = '0' then -- this means button was not in column 3 NS <= C2; -- so check if it was in column 2 else NS <= FOUND; -- button was in column 3 end if;--------------------------------------------------------------------------------------------------- when C2 => -- COL <= "0010"; -- activate column 2 if R1 = '0' then -- this means button was not in column 2 NS <= C1; -- so check if it was in column 1 else NS <= FOUND; -- button was in column 2 end if;--------------------------------------------------------------------------------------------------- when C1 => -- COL <= "0100"; -- activate column 1 if R1 = '0' then -- this means button was not in column 1 NS <= C0; -- so check if it was in column 0 else

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NS <= FOUND; -- button was in column 1 end if;--------------------------------------------------------------------------------------------------- when C0 => -- COL <= "1000"; -- activate column 0 if R1 = '0' then -- this means button was not in column 0 ?? NS <= WAIT_R_0; -- so the button must have been depressed fast else NS <= FOUND; -- button was in column 3 end if;--------------------------------------------------------------------------------------------------- when FOUND => -- COL <= COL_REG_VALUE; if R1 = '0' then -- this means button is depressed NS <= WAIT_R_0; -- so go back to initial state else NS <= SAMPLE; -- otherwise write the key value to DATA register end if;--------------------------------------------------------------------------------------------------- when SAMPLE => -- this state will generate a signal with one clock period for sampling COL <= COL_REG_VALUE; NS <= WAIT_R_1; -- otherwise wait till button is pressed--------------------------------------------------------------------------------------------------- when WAIT_R_1 => -- COL <= COL_REG_VALUE; if R1 = '0' then -- this means button was depressed NS <= WAIT_R_0; -- so go back to initial state else NS <= WAIT_R_1; -- otherwise wait till button is pressed end if;--------------------------------------------------------------------------------------------------- end case; end process;------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

WRITE_DATA: process (DCLK, CS, KEY_VALUE) -- write valid data to register begin if DCLK'event and DCLK = '0' then -- on the falling edge if CS = FOUND then DATA <= KEY_VALUE; end if; end if; end process; -- WRITE_DATA---------------------------------------------------------------------------------------------------

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---------------------------------------------------------------------------------------------------

COL_REG: process (DCLK, CS, COL) -- this is the column value register begin if (DCLK'event and DCLK = '0') then -- register the COL value on the falling edge if (CS = C3 or CS = C2 or CS = C1 or CS = C0) then -- provided we're in states C3 thru C0 only COL_REG_VALUE <= COL; -- otherwise the column value is not valid end if; end if; end process; -- COL_REG------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

DECODER: process(ROW, COL_REG_VALUE) -- decodes binary value of pressed key from row and column variable CODE: STD_LOGIC_VECTOR (0 to 7); begin CODE := (ROW & COL_REG_VALUE); case CODE is-- COL-- ROW 0 0123 when "00010001" => KEY_VALUE <= ZERO;--key 0 when "00010010" => KEY_VALUE <= ONE;--key 1 when "00010100" => KEY_VALUE <= TWO;--key 2 when "00011000" => KEY_VALUE <= THREE;--key 3-- ROW 1 when "00100001" => KEY_VALUE <= FOUR;--key 4 when "00100010" => KEY_VALUE <= FIVE;--key 5 when "00100100" => KEY_VALUE <= SIX;--key 6 when "00101000" => KEY_VALUE <= SEVEN;--key 7-- ROW 2 when "01000001" => KEY_VALUE <= EIGHT;--key 8 when "01000010" => KEY_VALUE <= NINE;--key 9 when "01000100" => KEY_VALUE <= A;--key A when "01001000" => KEY_VALUE <= B;--key B-- ROW 3 when "10000001" => KEY_VALUE <= C;--key C when "10000010" => KEY_VALUE <= D;--key D when "10000100" => KEY_VALUE <= E;--key E when "10001000" => KEY_VALUE <= F;--key F when others => KEY_VALUE <= SPACE; -- just in case end case; end process; -- DECODER

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------------------------------------------------------------------------------------------------------------------------------- END OF FSM1 (KEYPAD SCANNER) --------------------------------------------------------------------------------------------------------------------------------------------

-- select the appropriate lines for setting frequencyCLK_DIV: process (CLK, DIV_REG) -- clock divider

begin if (CLK'event and CLK='1') then DIV_REG <= DIV_REG + 1; end if;

end process; DCLK <= div_reg(8);DDCLK<=DIV_REG(10);------------------------------------------------------------------------------------------------------------------------------- END OF CLOCK DIVIDER ----------------------------------------------------------------------------------------------------------------------------------------------------

lcd_rw<='0';

process (DDclk,rEsEt)variable count: integer range 0 to big_delay;

variable c1 : std_logic_vector(7 downto 0); begin

IF rEsEt = '0' THEN

state<=initial;count:=0;lcd_enable<='0';lcd_select<='0';c1 := "01111111";

elsIF DDclk'EVENT AND DDclk = '1' THEN

case state isWHEN initial => -- to set the function

if count=reg_setup thenlcd_enable<='1';

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elselcd_enable<='0';

end if;lcd_data<=SET;lcd_select<='0';if count=small_delay then

state<=display;count:=0;

elsecount:=count+1;

end if;

WHEN display => -- to set display onif count=reg_setup then

lcd_enable<='1';else

lcd_enable<='0';end if;lcd_data<=DON;lcd_select<='0';if count=small_delay then

state<=clear;count:=0;

elsecount:=count+1;

end if;

WHEN clear => -- clear the screenif count=reg_setup then


lcd_enable<='0';end if;lcd_data<=CLR;lcd_select<='0';if count=big_delay then

state<=location;count:=0;

elsecount:=count+1;

end if;

WHEN location => -- clear the screenif count=reg_setup then

lcd_enable<='1';

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elselcd_enable<='0';

end if;

IF COUNT=0 THENif c1="10001111" then

c1:="11000000";elsif c1="11001111" then

c1:="10000000";else

c1:=c1+'1';end if;

END IF;

lcd_data <= c1 ;lcd_select<='0';

if count=big_delay thenstate<=putchar;count:=0;

elsecount:=count+1;

end if;

when putchar=> -- display the character on the LCDif count=reg_setup then


lcd_enable<='0';end if;

case c1 iswhen "10000000" => lcd_data<= H ;--SIGLE LINEwhen "10000001" => lcd_data<= E ;--SIGLE LINEwhen "10000010" => lcd_data<= X ;--SIGLE LINEwhen "10000011" => lcd_data<= SPACE ;--SIGLE

LINEwhen "10000100" => lcd_data<= SPACE ;--SIGLE

LINEwhen "10000101" => lcd_data<= K ;--SIGLE LINEwhen "10000110" => lcd_data<= E ;--SIGLE LINEwhen "10000111" => lcd_data<= Y ;--SIGLE LINEwhen "10001000" => lcd_data<= B ;when "10001001" => lcd_data<= O ;when "10001010" => lcd_data<= A ;

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when "10001011" => lcd_data<= R ;when "10001100" => lcd_data<= D ;when "10001101" => lcd_data<= SPACE ;when "10001110" => lcd_data<= SPACE ;when "10001111" => lcd_data<= SPACE;

when "11000000" => lcd_data<= K ;--SIGLE LINEwhen "11000001" => lcd_data<= E ;--SIGLE LINEwhen "11000010" => lcd_data<= Y ;--SIGLE LINEwhen "11000011" => lcd_data<= P ;--SIGLE LINEwhen "11000100" => lcd_data<= R ;--SIGLE LINEwhen "11000101" => lcd_data<= E ;--SIGLE LINEwhen "11000110" => lcd_data<= S ;--SIGLE LINEwhen "11000111" => lcd_data<= S ;--SIGLE LINEwhen "11001000" => lcd_data<= E ;when "11001001" => lcd_data<= D ;when "11001010" => lcd_data<= SPACE ;

-- when "11001011" => lcd_data<= RIGHT_ARROW ;when "11001100" => lcd_data<= SPACE ;when "11001101" => lcd_data<= DATA ;when "11001110" => lcd_data<= SPACE ;when "11001111" => lcd_data<= SPACE;WHEN OTHERS => NULL;

end case ;

lcd_select<='1';

if count=small_delay thenstate<=location;count:=0;

elsecount:=count+1;

end if;

end case;end if;

end process;end HEXKEY_BEH;

Procedure: 1.Scan columns and read from the rows

2. If a key is pressed from that column decode and display the key3. Scan next columns until a key pressed is detected4. Display the key until it is released

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Result: The values from 0 to F were displayed on all 4 LCD’s with the respective Hex Key being pressed.

3. Write a VHDL code to display messages on the given seven segment displaylibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity sevkeybrd is Port ( read : in std_logic_vector(3 downto 0); clk : in std_logic; scan : inout std_logic_vector(3 downto 0); disp_cnt : out std_logic_vector(3 downto 0); disp1 : out std_logic_vector(6 downto 0));end sevkeybrd;

architecture Behavioral of sevkeybrd is

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signal cnt_2bit:std_logic_vector(1 downto 0);begin

process(clk)begin

if clk='1' and clk'event thencnt_2bit<= cnt_2bit+1;end if;end process;

process(cnt_2bit)begincase cnt_2bit is when "00" => scan<= "0001";

when "01"=> scan<="0010";when "10"=>scan<="0100";when "11"=>scan<="1000";when others=> null;

end case;end process;

disp_cnt<="1110";process(scan,read)begincase scan iswhen "0001"=>case read is

when "0001"=>disp1<="1111110";when "0010"=>disp1<="0110011";when "0100"=>disp1<="1111111";when "1000"=>disp1<="1001110";when others =>disp1<="0000000";

end case;

when "0010"=> case read iswhen "0001"=>disp1<="0110000";when "0010"=>disp1<="1011011";when "0100"=>disp1<="1111011";when "1000"=>disp1<="0111101"; when others=>disp1<="0000000";

end case;

when "0100"=> case read iswhen "0001"=>disp1<="1101101";when "0010"=>disp1<="1011111";when "0100"=>disp1<="1110111";

5. KEY BOARD TO 7 SEGMENT DISPLAY

NET "CLK" LOC="p18";

NET "disp_cnt<0>" LOC="p30";




NET "disp<0>" LOC="p26";







NET "read_l_in<0>" LOC="122";

NET "read_l_in<1>" LOC="124";

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when "1000"=>disp1<="1001111";when others=>disp1<="0000000";

end case;

when "1000"=> case read iswhen "0001"=>disp1<="1111001";when "0010"=>disp1<="1110000";when "0100"=>disp1<="0011111";when "1000"=>disp1<="1000111";when others=>disp1<="0000000";

end case;when others=> null;end case;end process; end Behavioral;

Procedure: 1) Make connection between FRC 5 and FPGA board to the seven segment connector of

VTU card 1.2) Make the connection between FRC 4 to FPGA board to K/B connector of VTU card1.3) Then open xilinx impact s/w, select slave serial mode and select the respective bit file

and click program.4) Make the reset switch on.5) Change the pressing of Hex Keys to watch the display on LCD’s ranging from 0000 to

FFFF.

Result: The values from 0 to F were displayed on all 4 LCD’s with the respective Hex Key being pressed.

4.Write a HDL code to control Speed, direction of DC Motor

DC MOTORlibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity dcmotr is Port ( dir,clk,rst : in std_logic; pwm : out std_logic_vector(1 downto 0); rly : out std_logic; row : in std_logic_vector(0 to 3));end dcmotr;

architecture Behavioral of dcmotr is signal countr: std_logic_vector(7 downto 0);

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signal div_reg: std_logic_vector(16 downto 0); signal ddclk,tick: std_logic; signal duty_cycle:integer range 0 to 255;

beginprocess(clk,div_reg)beginif(clk'event and clk='1') then div_reg<=div_reg+'1';end if;end process;ddclk<=div_reg(12);tick<= row(0) and row(1) and row(2) and row(3);process(tick) begin if falling_edge(tick) then case row is

when"1110"=> duty_cycle<=255; when"1101"=> duty_cycle<=200; when"1011"=> duty_cycle<=150; when"0111"=> duty_cycle<=100; when others => duty_cycle<=100; end case; end if; end process;

process(ddclk, rst) begin if rst='0'then countr<=(others=>'0'); pwm<="01"; elsif(ddclk'event and ddclk='1') then countr<= countr+1; if countr>=duty_cycle then pwm(1)<='0'; else pwm(1)<='1'; end if; end if; end process; rly<='1' when dir='1' else '0';

end Behavioral;

UCF File: DC MOTOR

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NET "CLK" LOC="p18"; NET "RESET" LOC="p74"; NET "dir" LOC="p75"; NET "pwm<0>" LOC="p5"; NET "pwm<1>" LOC="p141"; NET "rly" LOC="p3"; NET "ROW<0>" LOC="p64"; NET "ROW<1>" LOC="p63"; NET "ROW<2>" LOC="p60"; NET "ROW<3>" LOC="p58";

Procedure : 1) Make connection between FRC 9 and FPGA board to the dc motor connector of VTU card 22) Make the connection between FRC 7 of FPGA board to the K/B connector of VTU card 23) Make the connection between FRC 1 of FPGA board to the DIP switch connector of VTV card 2.4) Connect the down loading cable and power supply to FPGA board.5) Then open xilinx impact s/w, select slave serial mode and select the respective bit file and click program.6) Make the reset switch on.7) Press the Hex keys and analyze speed changes for dc motor.

RESULT : The DC motor runs when reset switch is on and with pressing of different keys variation of DC motor speed was noticed.

5. Write a HDL code to control Speed, direction of Stepper Motorlibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity steppermt is Port ( clk,dir,rst : in std_logic; dout : out std_logic_vector(3 downto 0));end steppermt;architecture Behavioral of steppermt is signal clk_div:std_logic_vector(15 downto 0); -- speed is maximum at 15 signal shift_reg:std_logic_vector(3 downto 0);begin process(clk)

beginif rising_edge (clk) then

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clk_div <= clk_div+'1';end if;end process;process(rst,clk_div(15)) -- speed is maximum at 15beginif rst='0' then shift_reg<="0001";elsif rising_edge (clk_div(15)) then if dir='1' then shift_reg <= shift_reg(0) & shift_reg(3 downto 1); else shift_reg<= shift_reg ( 2 downto 0) & shift_reg(3); end if; end if; end process; dout<= shift_reg;end Behavioral;

UCF File:NET "clk" LOC = "p18"; NET "dir" LOC = "p85";NET "rst" LOC = "p84"; NET "dout<0>" LOC = "p7"; NET "dout<1>" LOC = "p5";NET "dout<2>" LOC = "p3"; NET "dout<3>" LOC = "p141";

Procedure: 1) Make connection between FRC 9 and FPGA board to the stepper motor connector of

VTU card 12) Make the connection between FRC 1 of FPGA board to the DIP switch connector of

VTU card 1.3) Then open xilinx impact s/w, select slave serial mode and select the respective bit file

and click program.4) Make the reset switch on.5) Visualize the speed variation of stepper motor by changing counter value in the

program.

Result: The stepper motor runs with varying speed by changing the counter value

I/O Pin Assignments

Xilinx FPGAFOR DC & Stepper MOTOR

FRC FRC1 FRC2 FRC3 FRC4 FRC6 FRC7 Xilinx FPGA1 74 84 112 122 40 58 FRC FRC92 75 85 114 124 41 60 1 7

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3 76 86 113 129 42 63 2 54 78 87 115 126 48 64 3 35 77 93 117 132 50 65 4 1416 80 94 118 136 51 66 9 5V7 79 95 121 134 56 67 10 GND8 83 100 123 139 57 28 9 VCC VCC VCC VCC VCC VCC 10 GND GND GND GND GND GND FOR LCD & DAC FOR ADCFRC FRC5 FRC8 FRC101 4 96 622 20 99 593 19 101 494 21 102 475 23 103 466 22 116 47 26 120 438 27 131 139 30 133 1210 29 137 1111 31 138 1012 38 140 613 5V 5V 5V14 -5v -5v -5v 15 3.3 3.3 3.316 GND GND GND

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