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verilog program

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Encoder Using Case statement module encoder_using_case( binary_out , // 4 bit binary Output encoder_in , // 16-bit Input enable // Enable for the encoder ); output [3:0] binary_out ; input enable ; input [15:0] encoder_in ; reg [3:0] binary_out ; always @ (enable or encoder_in) begin binary_out = 0; if (enable) begin case (encoder_in) 16'h0002 : binary_out = 1; 16'h0004 : binary_out = 2; 16'h0008 : binary_out = 3; 16'h0010 : binary_out = 4; 16'h0020 : binary_out = 5; 16'h0040 : binary_out = 6; 16'h0080 : binary_out = 7; 16'h0100 : binary_out = 8; 16'h0200 : binary_out = 9; 16'h0400 : binary_out = 10; 16'h0800 : binary_out = 11; 16'h1000 : binary_out = 12; 16'h2000 : binary_out = 13; 16'h4000 : binary_out = 14; 16'h8000 : binary_out = 15; endcase end end endmodule

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DESCRIPTION

VERILOG

TRANSCRIPT

Encoder Using Case statement

module encoder_using_case(

binary_out , // 4 bit binary Output

encoder_in , // 16-bit Input

enable // Enable for the encoder);

output [3:0] binary_out ;

input enable ;

input [15:0] encoder_in ;

reg [3:0] binary_out ;

always @ (enable or encoder_in)

begin

binary_out = 0;

if (enable) begin

case (encoder_in)

16'h0002 : binary_out = 1;

16'h0004 : binary_out = 2;

16'h0008 : binary_out = 3;

16'h0010 : binary_out = 4;

16'h0020 : binary_out = 5;

16'h0040 : binary_out = 6;

16'h0080 : binary_out = 7;

16'h0100 : binary_out = 8;

16'h0200 : binary_out = 9;

16'h0400 : binary_out = 10;

16'h0800 : binary_out = 11;

16'h1000 : binary_out = 12;

16'h2000 : binary_out = 13;

16'h4000 : binary_out = 14;

16'h8000 : binary_out = 15;

endcase

end

endendmoduleDecoder Using Case statement

module decoder_using_case (

binary_in , // 4 bit binary input

decoder_out , // 16-bit out

enable // Enable for the decoder

);

input [3:0] binary_in ;

input enable ;

output [15:0] decoder_out ;

reg [15:0] decoder_out ;

always @ (enable or binary_in)

begin

decoder_out = 0;

if (enable) begin

case (binary_in)

4'h0 : decoder_out = 16'h0001;

4'h1 : decoder_out = 16'h0002;

4'h2 : decoder_out = 16'h0004;

4'h3 : decoder_out = 16'h0008;

4'h4 : decoder_out = 16'h0010;

4'h5 : decoder_out = 16'h0020;

4'h6 : decoder_out = 16'h0040;

4'h7 : decoder_out = 16'h0080;

4'h8 : decoder_out = 16'h0100;

4'h9 : decoder_out = 16'h0200;

4'hA : decoder_out = 16'h0400;

4'hB : decoder_out = 16'h0800;

4'hC : decoder_out = 16'h1000;

4'hD : decoder_out = 16'h2000;

4'hE : decoder_out = 16'h4000;

4'hF : decoder_out = 16'h8000;

endcase

end

end

endmodule

Multiplexer Using Assignmodule mux_using_assign(

din_0 , // Mux first input

din_1 , // Mux Second input

sel , // Select input

mux_out // Mux output

);

//-----------Input Ports---------------

input din_0, din_1, sel ;

//-----------Output Ports---------------

output mux_out;

//------------Internal Variables--------

wire mux_out;

//-------------Code Start-----------------

assign mux_out = (sel) ? din_1 : din_0;

endmodule

Multiplexer Using Ifmodule mux_using_if(

din_0 , // Mux first input

din_1 , // Mux Second input

sel , // Select input

mux_out // Mux output

);

//-----------Input Ports---------------

input din_0, din_1, sel ;

//-----------Output Ports---------------

output mux_out;

//------------Internal Variables--------

reg mux_out;

//-------------Code Starts Here---------

always @ (sel or din_0 or din_1)

begin

if (sel == 1'b0)

mux_out = din_0;

else

mux_out = din_1 ;

end

endmodule

Multiplexer Using Casemodule mux_using_case(

din_0 , // Mux first input

din_1 , // Mux Second input

sel , // Select input

mux_out // Mux output

);

//-----------Input Ports---------------

input din_0, din_1, sel ;

//-----------Output Ports---------------

output mux_out;

//------------Internal Variables--------

reg mux_out;

//-------------Code Starts Here---------

always @ (sel or din_0 or din_1)

begin

case(sel )

1'b0 : mux_out = din_0;

1'b1 : mux_out = din_1;

endcase

end

endmodule

D Flip Flopmodule dff_async_reset (

data , // Data Input

clk , // Clock Input

reset , // Reset input

q // Q output

);

//-----------Input Ports---------------

input data, clk, reset ;

//-----------Output Ports---------------

output q;

//------------Internal Variables--------

reg q;

//-------------Code Starts Here---------

always @ ( posedge clk or negedge reset)

if (~reset) q


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