VLSIDesignMethodologyFinalProjectReport

Programmable

ConvolutionalEncoder

VadimSmolyakov

SafeenHuda

Copyright2009UniversityofToronto

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Introduction

In this document, a design overview of a programmable convolutional encoder is presented.Convolutional encoding is a widely used coding technique that facilitates error correction at thereceiverendofacommunication link.Programmableconvolutionalencodersareespecially suited forFPGAapplications. Commercial FPGAvendorsoffer softIP in the formofRTL code to consumers toalloweffortless implementationofhighperformanceerrorcorrectioncodes. Inthiswork,weproposethedesignofaprogrammableconvolutionalencoderahardwareblock thatcanbeprogrammed toimplementawidevarietyofconvolutionalencodingschemes.Thishardwareblockcouldpotentiallybeimplemented as part of a larger reconfigurable transmitter/transceiver system or as a newprogrammablecustommlayoutIPimplementedinaheterogeneousFPGAarchitecture.

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Input Data Stream

INPUT DATA REGISTER

SWITCH MATRIX (STEERING LOGIC)

MOD-2 ADDER ARRAY

INTERLEAVER BLOCK (PARALLEL TO SERIAL CONVERTER)

CO

NFI

GU

RA

TIO

N M

EMO

RY

Output Data

Stream

ChipOverview

SystemLevelOverviewAtoplevelsystemoverviewisshowninthefollowingdiagram:

Figure1:SystemLevelDiagram

Theproposedsystemusesashiftregisterwhicheffectivelystorespastsamplesoftheinputdatastream.Thesepast samplesofdataare thenadded together ina configurableorder (through theuseof theswitchmatrixandmod2adderarray);indeed,thereexistsavarietyofconvolutionalencodingschemesandeachoffersatradeoffbetweenthetransmissionrateandtheamountoferrorcorrectionthatcanberealized.Finally,aninterleaverblockpresentsaserialoutputofthedata.

Thenovelty intheproposedsystem is inthewaypastsamplesaregroupedthroughaconfigurableasopposedtoafixedarchitecture.Theswitchmatrix (whichactsassteering logic)andthemod2adderarraycanbeprogrammed(bytheconfigurationmemory,implementedasashiftregister)suchthatthesystemasawholecan implementawidevarietyofdifferentencoding schemes; theenduserof thissystemhastheflexibilitytotradeoffdatarateanderrorcorrectingcapability.Specifically,thedesignedprogrammableconvolutionalencoderallows forthe implementationofasubsetofthemaximum freedistancecodesasoutlinedintheIEEE802.16mstandard(thissubsetisprovidedintheAppendix).

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BlockOverview

InputDataRegister

The inputdata registerconsistsofa simple8bit shift register, theoutputsof individual flipflopsareusedbythedownstreamlogic(theswitchmatrixandthemod2adderarray),formingaconvolutionofthe input bitstream with a configurable impulse response of the encoder. The schematics and thelayoutforthisblockarepresentedintheappendix.

SwitchMatrix

ThedesignoftheswitchmatrixwasinspiredbyprogrammableroutingsuchasthatfoundinFPGAs.TheswitchmatrixmakesuseofNMOSpasstransistorstoconnectinputsoftheadderarraytooutputsoftheinput data register. The number of transistors in the switch matrix and the pattern of connectivitybetween theoutputsof thedata registerand the inputsof theadderarraywerebothdecidedonbyoptimizingforminimumnumberoftransistors,whilesupportingthetargetedencodingconfigurations.Alternatively,theswitchmatrixcanbeusedtosetan inputoftheadderarrayto0(this iscrucialas ithelps facilitate themanydifferentmodesof themod2 adder array). Schematics and layout for thisblockareprovidedintheappendix.

Mod2AdderArray

TheMod2adderarray isa tree like structureof two inputadderarrays, inaddition tomultiplexingcircuitry,whichallowsfor ittobeconfiguredasasetofadderswithawidevarietyofaddersizes.Thearray is comprisedof four configurable adderblocks.A symbolicdiagram for the configurable adderblockisshownbelow:

5

4 to 1M

UX

4 to

1M

UX

INPUTS

OUTPUTS

Figure2:Reconfigurableaddercelldiagram

Notethatthemod2addersareimplementedusing2inputXORsandcanbeconfiguredtoimplementavarietyofdifferentaddersbysettingsubsetsofthe inputsignalstozeroandbyconfiguringtheselectsignalsof the two4inputmuxesaccordingly. In fact, the reconfigurableadderblockcan support thefollowingaddersizes:

AdderSize MaximumNumberofAddersImplementableperBlock

2 23 24 25 26 2(withsharedinputs)7 2(withsharedinputs)8 2(withsharedinputs)

Figure3:ReconfigurableAdderCellpossibleconfigurations

ItshouldalsobenotedthattheconfigurableadderblockcontainsasetofPMOSsleeptransistorsusedto shut of parts of the adder block that are not being used; this allows for savings in static powerdissipationforconvolutionalencodingschemeswhichdonotusealloftheresourcesmadeavailablebytheconfigurableadderblock(pleaserefertotheschematicsforthelocationofsleeptransistors).

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Thecompleteadderarray (comprisedof4reconfigurableadderblocks)alongwith theprogrammableswitch matrix gives the required flexibility to implement the set of targeted convolution encodingschemes.

ConfigurationMemory

The configurationmemory is implemented as a simple shift registerwith a singlebitwide input. Aparticular encoding scheme is achieved by shifting a sequence of configuration bits seriallywith anenablesignalusedtocontroltheshiftduration.

Interleaver/ParalleltoSerialConverter

Theinterleaver/paralleltoserialconverterusesan8inputmuxanda3bitcounter.Theeightinputstothemultiplexerareformedbythe4configurableadderblockswith2outputseach. Theoutputofthecounterisusedtocontroltheselectsignalsofthemultiplexer.Everyclockcycle,thecountereffectivelyselectsadifferent inputof themux tobeoutputby theblock.Thus,eachof the8 inputsof themux(whichcorrespondtothe8outputsoftheadderarray)arecycledthroughcontinuously,creatingaserialdata stream from aparallel input. Theoutputof the interleaver is theoutputdata sequenceof theprogrammableconvolutionencoder.

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TopLevel

Thefollowingtableshowsapintableforourchip:

PinName Input/Output Functiondin Input InputDataclk Input EncoderClockrstn Input ActiveLowReseten Input Confshiftregisterenablecntl1 Input ConfigurationData1cntl2 Input ConfigurationData2cntl3 Input ConfigurationData3cntl4 Input ConfigurationData4cntl5 Input Configurationpin(AdderArray)out Output EncoderOutputvdd! Inout Supplygnd! Inout Ground

Figure4:PinTable

Whileschematicsandlayoutsforindividualblocksareprovidedintheappendix,shownbelowareschematicsandlayoutforthetoplevelcoreaswellasthetoplevelcorewithpadframe.

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Figure5:TopLevelSchematic

PADSDataRegister

SwitchMatrix

AdderArray +Interleaver

ConfigurationMemoryforAdderArray

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Figure6:TopLevelLayoutwithPadframe

CORE

Cntl1 Cntl2 Cntl3 Cntl4

Cntl5

vdd!

gnd!

out

gnd!gnd! vdd!vdd!

din

clk

rstn

en

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Figure7:TopLevelCorelayout

AdderArray Interleaver

ConfigurationMemory

DataRegister

ConfigurationMemory

SwitchMatrix

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TeamMemberContribution

Cell Schematic Layout

FlipFlopsandRegisters VadimSmolyakov VadimSmolyakov

Interleaver VadimSmolyakov/SafeenHuda VadimSmolyakov/SafeenHuda

Switchmatrix VadimSmolyakov/SafeenHuda VadimSmolyakov

AdderArray SafeenHuda SafeenHuda

TopLevel VadimSmolyakov/SafeenHuda VadimSmolyakov/SafeenHuda

PadFrame VadimSmolyakov VadimSmolyakov

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AppendixDataRegisterSchematic

DataRegisterLayout

FlipFlop

FlipFlop

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SwitchMatrixSchematic

SwitchMatrixLayout

ConfigurationMemory

SwitchMatrix(withnmospasstransistors)

ConfigurationMemory

SwitchMatrix(withnmospasstransistors)

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4 to 1M

UX

4 to

1M

UX

SLEEP_2

ConfigurableAdderBlockSchematic

ConfigurableAdderBlockLayout

SleepTransistors

XOR

SleepTransistors

XOR

MUX

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AdderArraywithInterleaverSchematic

AdderArraywithInterleaverLayout

ConfigurableAdderBlock

Interleaver

Interleaver

ConfigurableAdderBlock

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LVSREPORT@(#)$CDS: LVS.exe_64 version 5.1.0-64b 04/27/2009 03:12 (cicamd10) $ Command line: /autofs/CMC_2001/CMC/tools/cadence.2000a/IC.5141.ISR200905011535/tools.lnx86/dfII/bin/64bit/LVS.exe -dir /autofs/gulak/b/b2/svadim/CMOSP35/LVS -l -s -t /autofs/gulak/b/b2/svadim/CMOSP35/LVS/layout /autofs/gulak/b/b2/svadim/CMOSP35/LVS/schematic Like matching is enabled. Net swapping is enabled. Using terminal names as correspondence points. Net-list summary for /autofs/gulak/b/b2/svadim/CMOSP35/LVS/layout/netlist count 958 nets 12 terminals 1041 nfet 20 diode 1026 pfet Net-list summary for /autofs/gulak/b/b2/svadim/CMOSP35/LVS/schematic/netlist count 958 nets 12 terminals 1041 nfet 20 diode 1014 pfet Terminal correspondence points N816 N44 clkp N1092 N20 cntl1p N84 N31 cntl2p N258 N86 cntl3p N651 N114 cntl4p N1127 N80 cntl5p N374 N67 dinp N779 N98 enp N423 N1 gnd! N441 N51 outp N996 N101 rstnp N571 N0 vdd! Devices in the netlist but not in the rules: diode Devices in the rules but not in the netlist: capacitor resistor The net-lists match.

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layout schematic instances un-matched 0 0 rewired 0 0 size errors 0 0 pruned 0 0 active 2087 2075 total 2087 2075 nets un-matched 0 0 merged 0 0 pruned 0 0 active 958 958 total 958 958 terminals un-matched 0 0 matched but different type 0 0 total 12 12 Probe files from /autofs/gulak/b/b2/svadim/CMOSP35/LVS/schematic devbad.out: netbad.out: mergenet.out: termbad.out: prunenet.out: prunedev.out: audit.out: Probe files from /autofs/gulak/b/b2/svadim/CMOSP35/LVS/layout devbad.out: netbad.out: mergenet.out: termbad.out: prunenet.out: prunedev.out: audit.out:

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DRCReport\o DRC started at Thu Dec 24 15:28:43 2009 \o \o Validating hierarchy instantiation for: \o library: DiodeLib_dec23 \o cell: top_with_pads_v2 \o view: layout \o Rules come from library cmosp35. \o Rules path is divaDRC.rul. \o Inclusion limit is set to 1000. \o Running layout DRC analysis \o Flat mode \o Full checking. \o executing: nwell = geomAndNot("nwell" "drcex") \o executing: nwellres = geomAndNot(geomAnd("nwellres" "nwell") "drcex") \o executing: saveDerived(badNet "via12 net not covered by drawing") \o executing: via23Net = geomGetPurpose("via23" "net") \o executing: temp = geomAndNot(via23 geomAnd(metal2 metal3)) \o executing: saveDerivedtemp("floating via23") \o executing: drc(metal3 (width < rule) rule_text) ... \o executing: temp = geomEnclose(via34 metal3) \o executing: saveDerivedtemp(rule_text) \o executing: temp = geomAndNot(via34 geomAnd(metal3 metal4)) \o executing: saveDerivedtemp("floating via34") \o executing: saveDerivedtemp(rule_text) \o executing: temp = geomSize(geomSize(geomAndNot(metal4 pad) -5.0) 5.0) \o executing: drctemp((sep < 0.08) "sep of wide metal4 < .08") \o executing: drc(pad (sep < 60) "Warning: If you bond through CMC, keep pad pitch to 150 microns") \o DRC started.......Thu Dec 24 15:28:43 2009 \o completed ....Thu Dec 24 15:29:09 2009 \o CPU TIME = 00:00:06 TOTAL TIME = 00:00:26 \o ********* Summary of rule violations for cell "top_with_pads_v2 layout" ********* \o # errors Violated Rules \o 12 Warning: If you bond through CMC, keep pad pitch to 150 microns \o 164 Warning: substrate/well soft connected \o 176 Total errors found

NOTE1:164substrate/wellsoftconnectionsareexpectedandareintroducedbythesleeptransistorsthatconnectvddislandsofadderarrayandswitchmatrixsubcells.WhenthesleeptransistorsareremovedandreplacedwithadirectconnectiontoVDD,thewarningsdisappear.

NOTE2:Apitchoflessthan150umwaschosenforthepadframeforcompactness.