uso de lonworks

Design and Development of two devices based on LonWorks Technologies over

Power Line media

Jorge Juan Bueno ManglanoISDE Ing S.L. & Mälardalen University

César Martínez & Lars Asplund2007-03-26

Design of two Devices of 74

Jorge Juan Bueno Manglano


Abstract

In the one hand Power line communications technology can nowadays use the electrical power wiring of a home as a transmission medium. This is a technique that can be used in domotics for remote control of lighting and appliances without installation of additional control wiring.

On the other hand domotics have become extended since last ten years until being a common technology that any user can apply to his home without so much effort, such as the unique action the user have to do is to plug a device.

The aim of this thesis project is to invest and develop a LonWorks platform of self-installed interoperable devices that communicate one each other over Power Line Communications. The better way of do that is to get something that could be touched and observed, because of that the title of the project is “Design and Development of two devices based on LonWorks technologies over Power Line media”.

The thesis project describes the design and develop of hardware (by different functional blocks) and software (by implementing a protocol and showing the firmware) of each device. Concluding with future works.



Acknowledgements

Sometimes it is difficult for me to say thanks to people really help me to be a better person. I used to think that is better to demonstrate my gratitude by facts not by words. But sometimes is necessary to say thanks to people that is closer to you.

Thanks to my “Saint Uncle” for being so patient with such a absent-minded boy. Thanks to my family for being closer to me. Thanks to my “little Princess” for feeling you with me even when we were so far away. Thanks to my friends for being there.

And concluding, thanks to the Erasmus life.



Table of Contents

Table of Contents

Figure List........................................................................................................................................... 6 Introduction........................................................................................................................................ 8

Thesis targets.................................................................................................................................... 8Description of the method solution..................................................................................................8

Theoretical background.....................................................................................................................9

Power Line Signaling.....................................................................................................................10LONWORKS Networks................................................................................................................ 12The LonWorks Platform................................................................................................................ 12The Interoperable Self-Installed (ISI) Protocol............................................................................. 13

How it works.............................................................................................................................13ISI Addressing...........................................................................................................................14Subnet and Node ID.................................................................................................................. 14Groups.......................................................................................................................................15Network Variable Selectors...................................................................................................... 15Network Variable Tables.......................................................................................................... 15ISI Connection Model............................................................................................................... 16

Hardware...........................................................................................................................................18Functional blocks of the device..................................................................................................... 19Coupling functional block............................................................................................................. 20Control functional block................................................................................................................ 23Core PL3120 functional block.......................................................................................................25

Neuron Processor Architecture................................................................................................. 25Memory.....................................................................................................................................27Input/Output.............................................................................................................................. 28

Power Supply functional block......................................................................................................37Two inputs functional block.......................................................................................................... 42Two outputs functional block........................................................................................................ 44

Software.............................................................................................................................................45Sensor.............................................................................................................................................47

Actuator.............................................................................................................................. ............49

Summary and Conclusions.............................................................................................................. 51

Future works.....................................................................................................................................53

References......................................................................................................................................... 54



Illustration Index

figure 1: Power Line bands available.........................................................................................10

figure 2: C and A Power Line bands..........................................................................................10

figure 3: Compound Assembly.............................................................................................................16

figure 4: Hardware functional blocks diagram.........................................................................19

figure 5: Coupling functional block schematics.........................................................................20

figure 6: DC Bias current VS Inductance variant.....................................................................21

figure 7: AC Sweep analysis of L1, L2 y C1..............................................................................22

figure 8: Resonant frequency zoom.............................................................................................23

figure 9: Control functional block schematics............................................................................23

figure 10: True table of PT65103.................................................................................................25

figure 11: Neuron Chip PL3120...................................................................................................26

figure 12: Three Processors description......................................................................................27

figure 13: PL3120 Core Interface.................................................................................................28

figure 14: PL3120 Memory Map..................................................................................................29

figure 15: PL3120 IO Interface.....................................................................................................29

figure 16: Pin OOGAS Configuration..........................................................................................30

figure 17: Configureción pin OOGAS..........................................................................................30

figure 18: Clock X10.......................................................................................................................31

figure 19: RXIN Adaptation phase schematics............................................................................31

figure 20: AC Sweep analysis of VL2 and VL3............................................................................32

figure 21: AC Sweep Analysis of VL2, VL3 y VC5......................................................................32

figure 22: AC Sweep analysis of transmission line RXIN............................................................33

figure 23: Amplification phase schematics....................................................................................35



figure 24: Adaptation phase of RXIN............................................................................................35

figure 25: AC Sweep analysis of adaptation phase.......................................................................36

figure 26: AC Sweep analysis of reception line.............................................................................36

figure 27: AC Sweep analysis zoom over reception line...............................................................37

figure 28: Power supply schematics................................................................................................38

figure 29: Simulation of load and download current of C24........................................................39

figure 30: Download of C24 in the worst conditions (250mA).....................................................39

figure 31: Download of C24 in typical conditions (120mA)..........................................................40

figure 32: Packet sending each 250ms............................................................................................41

figure 33: Two Inputs functional block schematics.......................................................................42

figure 34: Time Analysis of TLP126...............................................................................................43

figure 35: Two outputs functional block schematics.....................................................................44

figure 36: Sensor flux diagram........................................................................................................48

figure 37: Actuator flux diagram....................................................................................................50



Introduction

Thesis targets:

Design and Develop two devices based on LonWorks technology with PL3120 Neuron chip, one with two inputs and another one with two outputs, both must be self-installed devices and interact one each other by power line media.

Functional description of devices

– Two inputs device: Self installed device with two high voltage inputs (L-N), in order to be used with on/off switches, push switches and so on. It is used as a sensor that interacts with an actuator (two outputs device) by Power Line media under an Echelon Net. The device is supplied directly by electrical net (230 V - 50Hz).

– Two outputs device: Self installed device with two 5 Amp solid state outputs, in order to be used with motors (blinds), lights, presence sensors, and so on. It is used as an actuator that interacts with a sensor (two inputs device) by Power Line media under Echelon Net. The device is supplied directly by electrical net (230 V - 50Hz).

Description of the method solution:

The whole thesis project is shared in the following different phases:

1. Documentation phase: Determine the main scopes and possibilities of the design through pdfs Databooks, datasheets and additional related books. Instead of studying ISI protocol.

2. Hardware design phase: Develop diagrams, schematics, firmware and layouts of each device.

3. Software design phase: Research and implementation of the ISI protocol and in and out functionality of each device. Also it is included the study of the ISI libraries.

First numbered phase is also the first phase in being developed, unlike the next two phases that are developed at the same time.

Design tools used through thesis work are showed and described in Annexe I.



Theoretical background



Power Line Signaling

The underlying signaling technology used in the PL 3120 and PL 3150 Power Line Smart Transceivers was developed and optimized through more than ten years offield-testing. Millions of Echelon’s narrow band transceivers have been deployed in a wide range of consumer, utility, building, industrial, and transportation applications worldwide. Features such as narrow-band BPSK signaling, dual carrier frequency operation, adaptive carrier and data correlation, impulse noise cancellation, tone rejection and low-overhead error correction provide superior reliability in the face of interfering noise sources.

Dual Carrier Frequency Operation

The PL 3120 and PL 3150 Smart Transceivers utilize a dual-carrier frequency signaling technology to provide superior communication reliability in the face of interfering noise sources. In the case of acknowledged messaging, packets are initially transmitted on the primary frequency and if an acknowledgement is not received the packet is retransmitted on the secondary frequency. In the case of unacknowledged repeat messaging, packets are alternately transmitted on the primary and secondary frequencies. In utility applications the primary and secondary communication frequencies lie within the A-Band shown in Figure 1.1. In non-utility applications, the primary communication frequency lies in the C-Band shown in Figure 1.1 while the secondary frequency actually lies in what is called the B-band in CENELEC nomenclature. Figure 1.2 illustrates how the primary and secondary communications fit into the various frequency bands.

Forward Error Correction


Figure 1: Power Line bands available

Figure 2: C and A Power Line bands


Many noise sources interfere with power line signaling by corrupting data packets. The PL 3120 and PL 3150 Smart Transceivers use a highly efficient, low-overhead forward error correction (FEC) algorithm in addition to a cyclical redundancy check (CRC) to overcome packet errors.

Powerful Output Amplifier

The external, high performance amplifier design developed for use with the PL Smart Transceivers provides a 1 Ohm output impedance and 1Ap-p current capability to drive high output levels into low impedance circuits, while maintaining the extremely low signal distortion levels necessary to meet stringent international EMC regulations.

Wide Dynamic Range

Dynamic range relates to the sensitivity of the receiver. The PL 3120 and PL 3150 Smart Transceivers have a dynamic range of > 80dB. On a quiet line the Power Line Smart Transceivers can receive signals that have been attenuated by a factor of 10,000.

Low Current Consumption

The PL 3120 Power line Smart Transceivers and his associated power amplifier circuitry are powered by user-supplied +8.5 to +18VDC (VA) and +5VDC (VDD5) power supplies. Built-in power management features, combined with a wide supply range, are key benefits when designing inexpensive power supplies. Power management is especially useful for high volume, low cost consumer products such as electrical switches, outlets, and incandescent light dimmers. Very low receive mode current consumption of just 350μA typical from the VA supply and 9mA typical from the VDD5 supply reduces power supply size and cost. The PL 3120 and PL 3150 Smart Transceivers communicate at a raw bit rate of 5.4kbps (C-Band) or 3.6kbps (A-Band), corresponding to maximum packet rates of 20 and 13 packets per second, respectively. This high throughput makes the transceivers well suited for residential, commercial, and industrial automation applications.



LONWORKS Networks

In almost every industry today, there is a trend away from proprietary control schemes and centralized systems. The migration towards open, distributed, peer-topeer LONWORKS networks is being driven by the interoperability, robust technology, faster development time, and scale economies afforded by LONWORKS based solutions. All of the everyday devices in a LONWORKS network communicate using the ANSI/EIA 709.1 protocol standard. This seven-layer OSI protocol provides a set of services that allow the application program in a device to send and receive messages from other devices in the network without needing to know the topology of the network or the functions of the other devices.

LONWORKS networks provide a complete suite of messaging services, including end-toend acknowledgement, authentication, and priority message delivery. Network management services allow network tools to interact with devices over the network, including local or remote reconfiguretion of network addresses and parameters, downloading of application programs, reporting of network problems, and start/stop/ reset of device application programs. Neuron Chips, a family of microprocessors originally designed by Echelon and licensed to third party semiconductor manufacturers, combine an ANSI/EIA 709.1 compliant processor core for running applications and managing the network communications, with a media-independent communication port, memory, I/O, and a 48-bit identification number (Neuron ID) that is unique to every device. The communication port permits short distance Neuron Chip-to-Neuron Chip communications, and may also be used with external line drivers and transceivers of almost any type. The Neuron 3120 Chip family includes self-contained application program memory (no external memory bus) and the real-time operating system (RTOS) and application libraries pre-programmed in ROM. Echelon’s PL Smart Transceivers integrate a Neuron processor core with an ANSI/ EIA 709.2 compliant power line transceiver within a single IC, eliminating the need for an external transceiver. Two variants of PL Smart Transceivers are available: the PL 3120 chip includes self-contained application program memory, RTOS, and application library pre-programmed in ROM.

The LonWorks Platform

LonWorks is a networking platform specifically created to address the unique performance, reliability, installation, and maintenance needs of control applications. The platform is built on a low bandwidth protocol created by Echelon Corporation for networking devices over media such as twisted pairs, powerlines, fiber optics, and RF.

Devices in a LonWorks network communicate through the LonWorks protocol. This provides a set of services that lets a device's application program send and receive messages to and from other network devices without needing to know the network topology or the other devices' names, addresses, or functions. It can optionally provide end-to-end acknowledgement of messages, authentication of messages, and priority delivery to provide bounded transaction times.



The Interoperable Self-Installed (ISI) Protocol

The ISI protocol is an application-layer protocol, under LonWorks platform, that allows installation of devices and connection management without the use of a separate network management tool. The ISI protocol can be used with small networks with up to 200 devices. The ISI protocol supports transitioning an ISI installed network to a managed network where a network management tool assumes responsibility for network configuration of all devices in the network. A network management tool provides additional flexibility, enables more complex connections and configuretion, and supports larger networks. The ISI protocol simplifies installation by eliminating the need for a separate tool for simple networks. LonWorks devices can self-install automatically or at the push of a button.

The ISI protocol performs three key functions: domain acquisition, network address assignment, and connection management. Domain acquisition ensures that devices in a network can interoperable with each other, but will not interfere with devices in a neighboring network. Network address assignment ensures that every device in a network has a unique logical address, which is important to support transitioning to a managed network. Connection management allows devices in a network to exchange data.

How it works

Network address assignment and connection management both require allocation of network resources. In the case of network address assignment, the network resources that must be allocated are subnet and node IDs. In the case of connection management, the network resources that must be allocated are network variable selectors. In a managed network, a network management server allocates network resources and ensures there are no conflicts. In an ISI network, there is no central network management server, so each device must allocate its own network resources and automatically resolve any conflicts that may occur due to duplicate resource assignment.

The ISI protocol uses the fire-and-forget algorithm for the allocation and maintenance of unique network addresses. The fire-and-forget algorithm eliminates delays when configuring the network, eliminates the need for a centralized server, and ensures correct ISI operation even at times of partial network outage or unavailability of many installed devices. When an ISI device needs a new network address such as a device or connection address, the ISI code in the device randomly selects an address and periodically broadcasts its selection to all the other devices in the network. This is the “fire” part of fire-and-forget. When a device does this, it does not wait for a response. It assumes that its chosen address is unique and continues to use it. This is the “forget” part of fire-and-forget. All ISI devices monitor these periodic broadcasts. If a device receives a message that indicates there is an address conflict, the receiving device takes defensive action and changes its own configuration to eliminate the conflict. This eliminates the need for the sending device to wait for a response. ISI devices maintain an estimate of the network size that is used to throttle these periodic broadcasts, such that the broadcasts do not produce more network traffic than is shown below.



Networks are assumed to be in a constant state of flux. Devices may be added and removed from the network, units may be powered on and off, or partial transient network outages may occur at any time. Thanks to the periodic notifications, the fire-and-forget algorithm ensures that each device handles a new situation as it becomes aware of relevant changes.

Devices in an ISI network must join two domains, a primary and a secondary. The primary domain is the application domain, and is used for all application communication and for ISI connection-related messages. The initial primary domain is fixed for all ISI devices. The initial domain must be a 3- byte domain ID with a value of 0x49, 0x53, 0x49 (the ASCII codes for “ISI”).

The secondary domain is the ISI administrative domain. The secondary domain is fixed for all ISI devices. The standard fixed value is the zero-length domain with the clone domain attribute set. The clone domain attribute allows devices to receive messages that originate from a device with the same subnet/node ID as the receiver. Devices without the clone domain attribute automatically reject packets originating from their own address, this is typically desirable except when it is necessary to find duplicate addresses. The clone domain attribute on the secondary domain allows ISI devices to detect and repair duplicate addresses.

Use of a common secondary domain allows multiple ISI networks to coexist on the same, shared, media. All ISI networks on the same shared media scale correctly as a function of the total number of ISI devices using that media, independent from the primary domain ID in use.

ISI Addressing

In a LonWorks network devices communicate using network variables. A network variable update is sent on the network in a packet that contains a network variable value and addressing information that is used to identify the device or devices to send the update to, and to identify the network variables on those devices to receive the update. The addressing information is contained in two components: layer-3 address that identifies the device or devices to receive the update, and a layer-6 address called the network variable selector that identifies the network variables on the receiving devices to receive the update. The layer-3 address may identify a single device, a group of devices, or all devices in the network.

Subnet and Node ID

A subnet and node ID is a pair of layer-3 identifiers that provide a unique address for each device in a network. For ISI networks, the subnet ID is a value between between 128 and 191 for PL-20 devices. Multiple devices can share the same subnet. The node ID is a value between 2 and 125. The combination of the subnet ID and node ID for a device must be unique for every



device in a network. Subnet and node IDs are assigned using the fire-and-forget protocol and the protocol maintains the uniqueness of the subnet/node ID value pairs.

Groups

A group is a logical collection of devices within a domain. Each group is identified by a layer-3 address called a group ID. The group ID is an identifier with a value between 0 and 255, which are split between 128 standard IDs (0 – 127) and 128 manufacturer-defined IDs (128 – 255). Each ISI standard group ID describes a device usage category. Devices are designed to recognize a certain set of group IDs, and might join up to 15 different groups at any time.

In an ISI network, network variables are typically sent using group addressing. Since network variables are typically sent using group addressing, devices that belong to the same group, but do not belong to the same connection, might receive the network variable update message. This is typically benign, since the network variable selector will have a unique value, and network variable updates that relate to a selector value unknown to the receiving device are dropped. If a device is a member of multiple groups, one of the groups must be identified as the primary group. A device may belong to up to 15 groups. The maximum number of concurrent groups is defined by the address table size, which is determined by the device application.

Network Variable Selectors

A network variable selector is the layer-6 address for a network variable. The network variable selector is an identifier that is included with every network variable update that is used to associate the network variable with a network variable within the receiving application. The network variable selector is a 14 bit identifier with a value between 0 and 3FFF hex, for a maximum of 16384 selector values. Selector values 0 to 2FFF hex are available for bound network variables. This provides a total of 12288 network variable selectors for bound network variables. Selector values 3000 to 3FFF hex are reserved for unbound network variables, with the selector value equal to 3FFF hex minus the network variable index. Selectors are assigned using the fire-and-forget protocol. The protocol maintains the uniqueness of the selectors.

Network Variable Tables

Every device on net maintains two tables that are used to associate a network variable selector contained in a network variable update message with a network variable on the device. These tables are also used to determine which selector or selectors to use when the application sends a network variable update. The first table is called the network variable configuration table. This table contains a single network variable selector per network variable on the device. The selector contained in this table is called the primary network variable selector. The second table is called the alias table. This table contains a variable number of selectors for each network variable on the device. The alias table is used as a pool of selectors, where any number of selectors may be assigned to each of the network variables on the device, up to the number of entries available in the alias table. Each entry in the alias table is called an alias.



ISI Connection Model

Connections are created during an open enrollment period that is initiated by a user, a connection controller, or a device application. Once initiated, a device is selected to open enrollment, this device is called the connection host. Any device in a connection may be the connection host, the connection host is responsible for defining the open enrollment period and for selecting the connection address to be used by all network variables within the connection. Connection address assignment and maintenance is handled by the ISI engine, and is transparent to the application.

A connection host opens enrollment by sending a connection invitation. Once a connection host opens enrollment then any number of devices may join the connection. Connections are created among connection assemblies. A connection assembly is a block of functionality, much like a functional block. A simple assembly refers to a single network variable, and a connection assembly consisting of more than one network variable is called a compound assembly.

To communicate and identify an assembly, the device application assigns a unique number to each assembly. This assembly number must be in the 0–254 range, sequentially assigned, starting at 0. Required assemblies for standard profiles must be first, assigned in the order the profiles are declared in the application. Standard ISI profiles that define multiple assemblies must specify the order the assemblies are to be assigned.

An assembly has a width, which equals the number of network variable selectors required for the connection of the assembly. Typically, the width equals the number of network variables in the assembly. All assemblies must have a width of at least 1. Simple assemblies have a width of 1; compound assemblies have a width of greater than 1.

One of the network variables in a compound assembly is designated as the primary network variable. If the primary network variable is part of a functional block, that functional block is designated as the primary functional block. Information about the primary network variable may be included in the connection invitation. To open enrollment, the connection host broadcasts a connection invitation that may include the following information about the assembly on offer: the network variable type of the primary network variable in the assembly, the functional profile number of the primary functional profile in the assembly, and the connection width. The connection invitation is sent using an ISI message called the open enrollment message (CSMO). Other devices on the network receive the invitation and interpret the offered assembly to decide whether they could join the new connection.


Figure 3: Compound Assembly


Devices that receive this CSMO message decide whether or not to join this connection based on the CSMO data, and knowledge of the local application. Any device that understands the data that is being offered may join this connection.

Since the invitation includes no more than one functional profile number, a compound assembly is typically limited to a single functional block on each device. To include multiple functional blocks in an assembly, a variant may be specified. A variant is an identifier that customizes the information specified in the connection invitation. Variants may be defined for any device category and/or any functional profile/member number pair.

Variant values 1 – 127 are standard variant values specified by this specification and by ISI profiles published by LONMARK International. Variant values 128 – 254 are available for use by manufacturer-specific connections. The open enrollment message (CSMO [1]) includes fields for the manufacturer ID, scope at which the types are defined, and a variant field. For standard connections, the manufacturer ID and scope are both set to zero. The variant field, too, is typically set to zero.

With manufacturer-specific compound connections, the variety of connection models supported with the CSMO message is virtually unlimited. The ISI protocol is limited to connections with a width of no more than 63.

Each assembly on a device has a unique number that is assigned by the application. Each network variable on a device may be assigned to an assembly.



Hardware



Hardware

The following points are a detailed description of the hardware parts of the design. Unlike in and out hardware reference the entire other points are common to the two devices (two inputs and two outputs).

Functional blocks of the device

The figure 1 shows the functional blocks contained on a device.

Device power supply and data both are obtained from the power mains (230V – 50Hz). The Power Supply functional block brings Vdd5 (5V) and Va (15V) by an energy storage power supply. The coupling functional block filters power mains voltage (230V – 50Hz) in order to carry the data signal to the PL3120 functional block. Through Core PL3120 functional block the data signal is adapted and processed, also the outputs (or inputs) are switched (or read) by this functional block. The control block brings to the Core PL3120 information about what address must the device have once inside the net.


Figure 4: Hardware functional blocks diagram


Coupling functional block

This functional block implements the interface between Power mains (230V - 50Hz) and Core PL3120 functional block.

Device communications are semi-duplex type, data transmission and reception are done through the same physical line. This functional block share modulated signal from electrical net (230V – 50Hz) and divides transmission and reception line in order to being subsequently adapted by Core PL3120 functional block.

Injecting a communication signal into a power mains circuit is accomplished by capacitively coupling a transceiver’s output to the power mains. In addition to the coupling capacitor, an inductor is present. The coupling capacitor and the inductor or transformer together act as a high-pass filter when receiving the communications signal. The high-pass filter attenuates the large AC mains signal (at either 50Hz or 60Hz), while passing the transceiver’s communication signal. The value of the capacitor is chosen to be large enough so that its impedance at the communication frequencies is low, yet small enough that its impedance at the mains power frequency (50Hz or 60Hz) is high. The impedance of the capacitor can be considered as part of the transmitter’s output impedance (Zo Transmitter). Keeping the impedance of the coupling capacitor low minimizes the signal injection loss caused by the voltage divider formed between the output impedance of the amplifier and the mains loading (ZLoad).

Figure shows the electrical schematics of the coupling functional block.

Capacitor C1 and inductor L1 shape a high pass passive filter that attenuates frequencies less than 10KHz, which filters electrical net signal (230V – 50Hz) and let the data signal to flux to the circuit. Value of the capacitor C1, unlike inductor L1, presents low impedance at high


Figure 5: Coupling functional block schematics


frequencies (120Khz – 160KHz) and high impedance at low frequencies (50Hz – 60Hz).

Inductor L1 has a value of 1mH, and tolerance of 10%, must support a DC current over 30mA without having an inductance value change. According to this conditions a LAL04TB100K model is selected, have a look to figure 3.

Inductor L2 with a value of 15uH form along with capacitors C1 and C2 a resonant type circuit. While the values of C1 and C2 could be set high enough to meet this goal, doing so would significantly increase the cost of the high-voltage capacitor C1. Since C2 is connected only to low voltage, and thus is lower cost for a given value, its value can be set higher relative to the value of the high-voltage capacitor C1.

Figure below shows the AC sweep analysis of RXINC line, circuit implemented by inductor L1, L2 and capacitor C1.

In this simulation is shown how frequencies less than 10KHz are efficiently attenuated,


Figure 7: AC Sweep analysis of L1, L2 y C1

Figure 6: DC Bias current VS Inductance variant


resonant circuit frequency is fixed to a value of 12.8KHz. RXIN line is subsequently connected to another adaptation phase detailed in Core PL3120 functional block.

Capacitor C2 avoid the DC current from amplification phase (transistor Q5 and Q7 polarization current) to flow towards coupling circuit in order not to have a shut-circuit through inductor L1, directly connected to ground.

Diodes D1 and D2 work as a protection element, in order to limit the range from 0V to 15V.

Capacitor C3, as well as stabilizing voltage Va, performs as bypass element in the case D1 drives high current that could damage Va voltage supply components.


Figure 8: Resonant frequency zoom


Control functional block:

Control functional block is the interface for the assignment of group and element to the device, they are important parameters in order to give a net address to the device, they are assigned by the user through two rotaries, one for the group and another one for the element.

Rotaries RO1 and RO2 are PT65103 model, each of them has 16 positions and offers the binary code of the position of the selector, the output states are shown in the figure.


figure 9: Control functional block schematics

Figure 10: True table of PT65103


Each rotary has in each of his pins a pull up resistor, in order to offer a defined state (0V – 5V) in the entrance of the shift register U5.

Shift register U5 is the 74HC165 model, it is a parallel load and serial output register, it is also directly controlled by Core PL3120 functional block, the control signals are clock signal, data load and clock enable.



Core PL3120 functional block

This functional block contains the main nucleus of the system, concretely the PL3120 chip, it is the manager of communications and control of the other functional blocks.

Neuron Processor Architecture

The Neuron core is composed of three processors. These processors are assigned to the following functions by the Neuron firmware. Processor 1 is the MAC layer processor that handles layers 1 and 2 of the 7-layer LonTalk® protocol stack. This includes driving the communications subsystem hardware and executing the media access control algorithm. Processor 1 communicates with Processor 2 using network buffers located in shared RAM memory.

Processor 2 is the network processor that implements layers 3 through 6 of the LonTalk protocol stack. It handles network variable processing, addressing, transaction processing, authentication, background diagnostics, software timers, network management, and routing functions. Processor 2 uses network buffers in shared memory to communicate with Processor 1, and application buffers to communicate with Processor 3. These buffers are also located in shared RAM memory. Access to them is mediated with hardware semaphores to resolve contention when updating shared data.

Processor 3 is the application processor. It executes the code written by the user, together with the operating system services called by user code. The primary programming language used by applications is Neuron C, a derivative of the ANSI C language optimized and enhanced for LONWORKS distributed control applications. The major enhancements are the following:


Figure 11: Neuron Chip PL3120


• A network communication model, based on functional blocks and network variables, that simplifies and promotes data sharing between like and disparate devices.• A network configuration model, based on functional blocks and configuration properties, that facilitates interoperable network configuration tools.• A type model based on standard and user resource files that expands the market for interoperable devices by simplifying the integration of devices from multiple manufacturers.• An extensive set of I/O drivers that support the I/O capabilities of the Neuron core.• Powerful event driven programming extensions that provide easy handling of network, I/O, and timer events.

The support for all these capabilities is part of the Neuron firmware, and does not need to be written by the programmer.

Each of the three identical processors has its own register set, but all three processors share data, ALUs (arithmetic logic units) and memory access circuitry. On the PL 3150 Smart Transceiver, the internal address, data, and R/W signals are reflected on the corresponding external lines when utilized by any of the internal processors. Each CPU minor cycle consists of three system clock cycles, or phases; each system clock cycle is two input clock cycles. The minor cycles of the three processors are offset from one another by one system clock cycle, so that each processor can access memory and ALUs once during each instruction cycle. Figure 2.3 shows the active elements for each processor during one of the three phases of a minor cycle. Therefore, the system pipelines the three processors, reducing hardware requirements without affecting performance. This allows the execution of three processes in parallel without time-consuming interrupts and context switching.


Figure 12: Three Processors description


Memory

Memory Allocation Overview

• 4,096 bytes of in-circuit programmable EEPROM that store:— Network configuration and addressing information.— Unique 48-bit Neuron ID — written at the factory.— User-written application code and read-mostly data.• 2,048 bytes of static RAM that store the following:— Stack segment, application, and system data.— Network buffers and application buffers.• 24,576 bytes of ROM that store the following:— The Neuron firmware, including the system firmware executed by the MAC and networkprocessors, the executive supporting the application program, and application libraries.


Figure 13: PL3120 Core Interface


Input/Output

- Twelve Bidirectional I/O Pins: These pins are usable in several different configuretions to provide flexible interfacing to external hardware and access to the internal timer/counters. The logic level of the output pins may be read back by the application processor. Pins IO4 – IO7 and IO11 have programmable pull-up current sources. They are enabled or disabled with a compiler directive. Pins IO0 – IO3 have high current sink capability (20 mA @ 0.8 V). The others have sink capability of 1.4 mA @ 0.5 V. All pins (IO0 – IO11) have TTL level inputs with hysteresis. Pins IO0 – IO7 also have low level detect latches.

- Two 16-Bit Timer/Counters: The timer/counters are implemented as a load register writable by the processor, a 16- bit counter, and a latch readable by the processor. The 16-bit registers are accessed 1 byte at a time. Both the PL 3150 and PL 3120 Smart Transceivers have one timer/ counter whose input is selectable among pins IO4 – IO7, and whose output is pin IO0, and a second timer/counter with input from pin IO4 and output to pin IO1. No I/O pins are dedicated to timer/counter functions. If, for example, Timer/Counter 1 is used for input signals only, then IO0 is available for other input or output functions. Timer/counter clock and enable inputs may be from external pins, or from scaled clocks derived from the system clock; the clock rates of the two timer/counters are independent of each other. External clock actions occur optionally on the rising edge, the falling edge, or both rising and falling edges of the input.


Figure 14: PL3120 Memory Map


Pin OOGAS [2] is configured through resistors R29, R30 and capacitor C17. Connecting this components the OOGAS [2] function is activated. During transmission mode if voltage Va is under 7.9V, value determined by R29 and R30, transmission is stopped and recovered when voltage Va be over 13V.

Chip U1 PL3120 oscillates with a frequency fixed by clock component X1, this frequency is 10Mhz.


Figure 16 : Pin OOGAS Configuration

Figure 15: PL3120 IO Interface


Capacitors C8 and C9 filter harmonics produced by component X1 and make this component to oscillate at 10Mhz as fundamental frequency.

Component D8 is the service led diode, it is driven making a shut-circuit between two pins of JP1.

Next figure shows the data reception signal RXIN adaptation circuit, this signal come


Figure 17: Clock X10

Figure 18: Service Led


from coupling functional block.

The circuit filters and adapts input signal RXINC in order to be connected to RXIN pin of Neuron Chip PL3120 U1. Capacitor C7 and inductor L3 conforms a low pass filter in order to filer in a more effective way the signal that comes from coupling functional block.

figure above shows the AC sweep of the coupling functional block (VL2) and the same sweep with the low pass filter (VL3) formed by C7 and L3.

Resistor R8 and capacitor C5 make a low pass filter that attenuates frequencies over 190KHz. Next figure shows AC sweep for adaptation circuit adding this two components


Figure 20: AC Sweep analysis of VL2 and VL3

Figure 19: RXIN Adaptation phase schematics


As a result with the circuit formed by resistors R6, R7 and R10 and diodes DP2 current limits are applied in order not to damage the Neuron Chip U1 inputs. Decoupling capacitor C6 permits to connect reception line RXINC to the RXIN pin of U1.

Figure shows above describe AC sweep of the whole reception line, since coupling functional block to adaptation circuit.

Figure shows amplification phase of Core PL3120 functional block, through structure formed by current mirror and thermal coupling power transistors a current up to 1A is given in transmission mode.


figure 21: AC Sweep Analysis of VL2, VL3 y VC5

figure 22: AC Sweep analysis of transmission line RXIN


Power transistors Q5 and Q7 amplifies data from Neuron Chip U1, they are sent to the transmission line TXOUT. Output voltage amplitude is 7Vp-p.

Transistors Q8 and Q3 along with Q5 and Q7 form a thermal coupling structure, in order to help to Q5 and Q7 output transistors [9] to compensate their power dissipation parameter. Maximum duty cycle is fixed to 54% for Q5 and Q7.

A “current mirror” [9] is implemented by transistors Q10, Q9 and Q6 along with resistors R28 and R27 and capacitor C20. Transistors Q5 and Q7 are always in a polarized state due to the performance of the “current mirror”, because of that the phase distortion effect is avoided and signal is far of suffering any alteration produced by this phase.

Through TXBIAS line, connected to the emitter of transistor Q4, is configured the transmission current that is needed in order to make a properly transmission of data. Maximum limit current of this phase is 1Ap-p.


figure 23: Amplification phase schematics


The sense line TXSENSE permits to feedback the circuit in order to keep a constant current value meanwhile data transmission is active.

Through Vcore line, connected to the base of transistor Q4, transmission is interrupted if it is needed (have a look to OOGAS [2] configuration property, power supply functional block). When data transmission must be interrupted Vcore is power down and transistor Q4 putted in shut state until power supply is recovered.

Decoupling capacitor C23 only permits the AC current to flow to amplification phase.

Diodes DP3 are TXOUT line transmission protection elements.

The following is showing a detailed description of signals relatives to transmission and reception mode:

Transmission

TXON: High level active signal that indicates that a packet is being sent.VCORE: Transmission interrupt signal, have a look to the OOGAS [2] function.TXDAC: Digital to Analog transmission signal.TXBIAS: Configuration transmission current pin.TXSENSE: Feedback circuit signal.

Reception

RXIN: Data input signal.RXC: Adapted data input signal.INTOUT: Adaptation phase output signal.INTIN: Adaptation phase input signal.

Next figure shows adaptation phase of reception signal, helped by internal circuits of Neuron Chip U1 signal is treated in order to obtain data in a properly way along with relative circuit in coupling functional block.



A low pass filter is conformed through resistors and capacitors R11, R12, R14, C12 and C13, adding internal circuits of Neuron Chip U1. As a result, frequencies over 170KHz are attenuated.

Adding the described circuit to the low pass filter formed with resistors R15 and R13 and capacitors C11 and C14 the effect of the first is maximize due to the frequency response of this structure. The figure that follows shows the AC sweep of the entire adaptation circuit.


figure 24: Adaptation phase of RXIN

Figure 26

figure 25: AC Sweep analysis of adaptation phase


Next figure shows the AC sweep analysis of the entire reception line RXIN, which includes coupling phase, adaptation phase and internal Neuron Chip PL3120 circuit.

It can be observed how reception signal is adapted from electrical net (230V – 50Hz) to pin RXIN of Neuron Chip PL3120 U1. The figure showed below is a zoom of the AC sweep analysis showed above, maximum value of ganancia is between 110KHz and 170KHz, where are situated primary (130KHz) and secondary (115KHz).


figure 26: AC Sweep analysis of reception line

Figure 27: AC Sweep analysis zoom over reception line


Power Supply functional block:

This functional block manages the supply of the device, as well as generates the voltage Va and the voltage Vdd.

Voltage Va is a non-isolated voltage, it is obtained from the electrical net (230V – 50Hz), it is rectified through bridge diode BR1 and fixed to a value of 15V with diode D7, with a Vzener of 13V, and diodes D5 and D6 with negative temperature coefficient. This structure compensate the positive temperature coefficient of D7. As a result Va = Vd7 + Vd5 + Vd6 = 15V.

When the PL Smart Transceiver is in receive mode the allowed Va supply range is 8.5V to 18V. When the PL Smart Transceiver is transmitting a message the Va supply should be between 10.8V and 12.6V. Under certain conditions the Va supply range during transmission may be extended from a minimum of 8.5V to a maximum of 18V. These conditions are described in the next paragraphs.

The minimum Va supply voltage while transmitting may be relaxed from 10.8V down to 8.5V when worst case line voltage, temperature, component tolerance and transmit power supply loading are present (including a maximum Va transmit current of 250mA). This condition provides adequate headroom when the transmit amplifier is driving a low impedance line and its output voltage is somewhat less than 7Vpp. Power supply design must maintain Va ≥10.8V under typical line voltage, current drain (including typical transmit current of 120mA from the Va supply) and room temperature conditions.

This condition ensures adequate transmit amplifier headroom to drive the full 7Vpp signal onto the line under lighter load conditions. Extending the maximum VA range above 12.6V up to a maximum of 18V is allowed providing the thermal requirements of the transmit amplifier are met. The temperature of the amplifier depends on the on how frequently the device will be required to transmit, the ambient temperature and the power supply voltage. The key power supply parameter with regard to amplifier heating is the average Va supply voltage during transmission. If we express how frequently the device is required to transmit in terms of maximum transmit duty cycle then the thermal requirements of the amplifier are met by satisfying the following formula:


Figure 28: Power supply schematics


VATXAVE < (150-TAMAX)/(8*DMAX);Where:VATXAVE = Average Va supply voltage while transmittingTAMAX = Maximum ambient temperature inside the product enclosure (degrees C)DMAX = Maximum transmit duty cycle of the device (expressed as a decimal number)

The maximum transmit duty cycle generally does not exceed 64% since this is the largest value possible for a device that uses LONMARK interoperable transceiver parameters and transmits messages of ≤ 34 Bytes (A transmission with a period of 92.2ms). Note that many products transmit infrequently and thus have much lower transmit duty cycle requirements than 64%.

Capacitor C24 is a critical component due to his functionality. This component, as well as stabilizing the voltage Va, must storage enough energy in order to supply the requirements of transmission mode. The load process of the capacitor is performed while device is not in transmission mode. The figure 9 shows the simulation of the current load and download of the capacitor C24. The load period from 0V to 15V is around 1.35s.

In sencond 3s a data packet is sent simulating the worst conditions the device must support (250mA).


Figure 29: Simulation of load and download current of C24


Figure above shows the download of C24 due to a packet transmission, when transmission is finished(3.922s) the voltage Va has a value of 10.3V. By this way it is confirmed that the value of C24 is large enough in order to fulfill the specifications in the worst case conditions.

The next figure shows the simulation of a data transmission inside typical conditions of performance, with a current of 120mA.

As it is showed when the transmission is finished (3.922s) the value of voltage Va is 12.87V (over the limit of 10.8V).

In the figure below is showed the simulation relative to the sending of several administrative messages (32 bytes each 250ms), in order to determine the limits of the power supply resources in transmission mode.


figure 30: Download of C24 in the worst conditions (250mA)

figure 31: Download of C24 in typical conditions (120mA)


It can be observed that power supply resources are enough in order to supply the periodical packet sending (administrative messages) each 250ms (fixed by ISI [1] protocol) as maximum.

Inductors L4 and L5 have a high value impedance in high frequencies (120KHz – 160KHz), inside this frequencies communications frequencies are found, the inductor target is to make the current easy to flow towards coupling functional block and data signals don´t be attenuated by power supply functional block.

Decoupling capacitor C23 permits only the AC current flows towards power supply circuit (connected to bridge diode BR1).

– PL3120 Power managed system (OOGAS)

In cost or size-sensitive devices, it may be desirable to use an energy storage power supply. These supplies take advantage of the wide supply voltage range and the large difference between the transmit and receive current requirements of the transceiver, storing energy while the device is in receive mode and expending it during signal transmission. By using an energy storage system, the device can use a smaller, less expensive, power supply than a device with an equivalent “full power” supply. In this way, a low-current supply may be used which only has to supply the required receive mode current, plus an incremental current to recharge a capacitor between transmissions. An energy storage power supply is generally designed so that its VA supply voltage, while in receive mode, is above the 12V nominal specification (e.g 15V). During packet transmission the voltage on the VA supply is then allowed to drop, as energy from the capacitor is used for transmission. The value of the energy storage capacitor must be large enough so that the VA supply voltage is still sufficient for proper operation by the end of a single maximum-length packet transmission. Proper device opera-tion is then maintained when the energy storage capacitor is selected such that the VA power supply meets both of the following conditions:

• VA ≥10.8V after the typical IA transmit load of 120mA has been active for 140.7ms (see note) for an A-band device (92.2ms for a C-band device). This condition only needs to be met at room


Figure 32: Packet sending each 250ms


temperature with nominal AC line voltage.

• VA ≥8.5V after the worst case IA transmit load of 250mA has been active for 140.7ms (see note) for an A-band device (92.2ms for a C-band device). For proper node operation this condition must be met over the full range of worst-case component tolerances (including IDD5 drain), AC line voltage, and temperature.

Having chosen a storage capacitor to provide adequate voltage after transmission of a single packet, the power management feature of the PL Smart Transceiver must also be enabled to ensure adequate supply voltage over the span of multiple packet transmissions. The power management feature prevents excessive power supply droop from transmission of multiple back-to-back packets under worst case conditions by monitoring the voltage on the energy storage capacitor and then, if required, regulating the time between transmissions so that the capacitor has time to recharge. The power management feature is enabled by first connecting an appropriate resistor voltage divider between the VA supply and the OOGAS pin of PL 3120/PL 3150 IC, as shown in reference schematic diagrams described in Appendix A. In addition, use of a standard transceiver type with a “-LOW” suffix is required to enable the power management feature, as described in Chapter 8.

Once enabled, the power management system detects any instance where the VA supply drops below the lower power management threshold (nominally 7.9V). The PL Smart Transceiver then delays transmission until the energy storage capacitor has been recharged to allow transmission of a complete packet. The Smart Transceiver then transmits any waiting packets once the capacitor has fully charged.


Figure 33: OOGAS Description


Two inputs functional block

This functional block offers two non-isolated high voltage capable (230V – 50Hz) inputs. A push switch must be connected to pins 1-2 (or 3-4) of connector J3 in order to cut the line offered by the device. Neutral line is not necessary in this connector because is connected internally in the device.

Component U6 is an opto-coupler that contains a led diode and a phototransistor. When connector J3 pins 1-2 are shut-circuited by an external component (i.e a push switch) the led diode of the opto-coupler U6 emits light, which is received by the phototransistor positioning it into conduction state. When this phototransistor is in conduction state voltage at pin IO2 is 0V. At the contrary in the shut state (with no light being emitted by led diode) voltage at pin IO2 is 5V.

Performance is the same for the opto-coupler U7 when pins 3-4 are shut-circuited. Voltage is switched (0V-5V) in pin IO3.

Due to work with AC voltage (230V - 50Hz) in order to excite the photo transistor of each optocoupler a two diodes structure is required. Each diode works in one of the semi-cycle of AC voltage. Because of that a TLP26 model is selected for U6 and U7.

Even with a two diodes structure in several periods of time inside each cycle (50Hz) it would be difficult to excite the photo-transistor. Vf in each led diode has a value of 1.15V, so each


Figure 33: Two Inputs functional block schematics


photo transistor will not be polarized in each “pass through zero” of main powers signal (230 V – 50Hz).

In order to calculate the period of time when photo-transistor is not polarized in the case the “press switch” is pressed (pins 1-2 or 3-4 of J3 are shut-circuited) it has to have taken into account the next statements:

- The period of time that a signal(230V – 50Hz) spend in changing from +1.15V to -1.15V is 37us.- The period of time between led diode emits light and photo-transistor drives current is ton=10us.- The period of time between led diode stops emitting light and photo-transistor stops driving current is toff=8us.

The time the photo-transistor is off will be:

t transistor−off =t1.5V a−1.5V−toff ton=37 s−8 s10 s=39 s

Once the period of time is known and in order to have an optimal design with as components as possible, this kind of error is solved by software.


Figure 34: Time Analysis of TLP126


Two outputs functional block

This functional block offers two solid state outputs (5A).

Trough pins IO2 and IO3 transistors Q11 and Q12 are driven, when this fact is performed the inductor of rele U3:A and U4:A is energized then the contacts U3:B and U4:B change their position to shut.

Line is connected to one of the contacts U3:B and U4:B, and shut-circuited with the other when current flow through each inductor.


Figure 35: Two outputs functional block schematics


Software



In order to communicate the two devices a communication protocol must be implemented in both of them, the targets of the project indicate that one of the device must be enrolled as a two inputs device (sensor) and another as a two outputs device (actuator), by these means since the two devices are reseted and plugged each other into the Power Mains a connection net must be created for sharing data between both of them. To solve and implement this kind of network, a firmware based on LonWorks and ISI Protocol has been developed (have a look to the theoretical background).

The following is a description and flux diagram of the firmwares load in each device.



– Sensor:

Once the group and the element is read the application waits for an event (ISIWarm [4]) that indicates that the device is ready to make a connection invitation, when this event happens all LEDs 0 – 7 of the evaluation board (see annexe I) are turned on. The device broadcasts the connection invitation, which includes group and element fixed by the user. If the device does not receive any confirmation of connection accepted broadcast the invitation periodically. At the contrary, if the connection is accepted properly the application starts polling the push switches PW1 – PW6, if the state of any of them changes an update is made over the associated network variable.

The next figure shows the flux diagram of the sensor firmware.




Figure 36: Sensor flux diagram


– Actuator:

Once the group and element is read the device waits for any connection invitation in order to accept what fits in with it. If the connection invitation is received and properly processed LED7 of the evaluation board (see annexe I) is turned on. From this moment each network variable update will produce the LED0 – LED7 of EVAL Board to change his state.

The next figure shows the flux diagram of the actuator firmware.




Figure 37: Actuator flux diagram


Summary and Conclusions

Once the targets of the thesis have been achieved the following is a conclusion in order to resume the main aspects the design.

The main aim of this thesis project was to design and develop two self-installed and interoperable devices. This target has been solved by implementing the ISI protocol over each device, the ISI protocol is an application layer protocol based on the LonWorks platform (have a look to the theoretical background). Through the study of libraries and the development of the firmware (annexe II) the two devices can communicate one each other only with the action of select a group and a element and plug them. Automatically a net is implemented by all devices and connections are created in a short period of time.

Hardware resources of each devices has been taking into account in order to do an optimal (size and cost) design. Each device has been shared into several hardware functional blocks, the following is a description of

● Coupling functional block: This functional block implements the interface between Power mains (230V - 50Hz) and Core PL3120 functional block. Device communications are semi-duplex type, data transmission and reception are done through the same physical line. This functional block share the modulated signal from electrical net (230V – 50Hz) and divides it into transmission and reception line in order to being subsequently adapted by Core PL3120 functional block. The relevant structure is formed by capacitor C1 and inductor L1, they conform a high pass filter for frequencies over 12Khz, with this filter the data signal can be shared from electrical net (230V – 50Hz). Decoupling capacitor C2 is added in order to not permit the DC current (transistors polarization of Core PL3120 amplification phase) flows towards coupling functional block as well as avoiding any shut-circuit that can be produced through inductor L1 (directly connected to ground). A L2 inductor is also added in order to create a resonant circuit along with C1 and C2. Adding inductor L2 a less capacitor C1 (directly connected to 220V – 50Hz signal) value can be selected reducing in a significantly way the size of the design (have a look to Coupling functional block – Hardware).

● Control functional block: This is the interface for the assignment of group and element to the device, all devices in a self-installed net must have a group and element id (even if it is the same for several of them). The selection has to be done by the user and they are selected through two rotaries, one will be assign the group and other one will select the element.

● Core PL3120 functional block: This functional block contains the PL3120 Neuron Chip, it is a dedicated chip with three processors and a power line transceiver embedded in the same core. Though it the data signals are processed and sent, IO functions managed and device controlled. This functional block is also shared in several phases. Reception Line adaptation phase: Through this circuit the signal, firstly received by the coupling functional block, is adapted in order to obtain a clear data signal on the entrance of RXIN pin of Core PL3120. It is made with several high and low pass filters and current limits circuit. Amplification phase: This circuit implements an amplifier to be applied over the transmitted signal, though the combination of a “current mirror” and a thermal coupling transistors structure a current until 1Ap-p can be applied to the transmitted signal.

● Power Supply functional block: This functional block managed the supply of the device, as well as generates the voltage Va and the voltage Vdd. The voltage Va is a non-isolated voltage obtained from the electrical net (230V – 50Hz), which is rectified through a bridge



diode and fixed to a value of 15V by a regulator component. The most current demand is made when device is in transmission mode, because of that Capacitor C24 is a critical component due to it must storage enough energy in order to supply the requirements of this mode (In the worst case must supply 250mA during 92.2ms). The value of the energy storage capacitor C24 must be large enough so that the Va supply voltage is still sufficient for proper operation by the end of a single maximum-length packet transmission along with power manage system (OOGAS, have a look to Power Supply functional block). In order not to attenuate the data signal two inductors must be added at the beginning of this functional block.

● Two inputs functional block: This functional block offers two non-isolated high voltage capable (230V – 50Hz) inputs. Electrical net (230V – 50Hz) directly drives a opto-coupler component that permits the device to detect any variation of the state of the input.

● Two outputs functional block: This functional block offers two solid state outputs (5A), which are driven by Core PL3120 IOs pins.

As a result it can be concluded that the combination of hardware and software parts compound a interoperable self-installed device which uses power line media in order to communicate and keep into the net.



Future works

The following is described several future works related to this thesis project.

– “Develop two devices based on Managed LonWorks Netwoks over Power Line Media”. It would be interesting to study the difference between the two technologies, self-installed networks (One of the subject of this thesis) and managed networks.

– “Improvements about Power Line Communications Media”: Power Line resoeurces has been one of the limits during the develop of this thesis. It would be interesting to study this relative new technology.

– “Design two devices based on LonWorks technology and supporting self-installed and managed networks”. It would be interesting to develop a devices which supports the two types of nets, due to make it powerful towards the final user.

It would like interesting too to expand this thesis project in order to work with other power mains configurations, for instance 230V – 60Hz.



References

[1] Echelon Corporation, “ISI Programmer's Guide ” (2007)

[2] Echelon Corporation, “PL31203150 Datasheet” (2007)

[3] Echelon Corporation, “Neuron C Programmer's Guide” (2007)

[4] Echelon Corporation, “ISI Protocol Specification” (2007)

[5] Echelon Corporation, “Neuron C Reference Guide” (2007)

[6] Echelon Corporation, “NodeBuilder Error's Guide” (2007)

[7] Echelon Corporation, “ISI Protocol Specification” (2007)

[8] Echelon Corporation, “Mini EVK QuickStarter Guide” (2007)

[9] Echelon Corporation, “PL3120 and PL3150 Databook” (2007)

[10] Echelon Corporation, “MiniEVK Hardware Guide” (2007)

[11] Douglas Self, Ediciones CEAC, “Amplificadores de Potencia Manual de Diseño”

[12] NILSSON, JAMES W. y RIEDEL, SUSAN A. ELECTRIC CIRCUITS AN PSPICE MANUAL USING ORCAD PACKAGE (7TH ED.)

[13] “TEORIA DE PSPICE”, LOPEZ VALDIVIA, ANDRES y OGAYAR FERNANDEZ, BLAS,

[14] “POWER ELECTRONICS: CONVERTERS, APPLICATIONS AND DESIGN, MEDIA ENH ANCED ” MOHAN, NED 3rd Edion.

[15] HOROWITZ, PAUL y HILL, WINFIELD THE ART OF ELECTRONICS (2ND ED)

[16] CENELEC EN 50065-1:2001 “Signaling on low-voltage electrical installations in the frequency range 3kHz to 148.5kHz” Part 1 “General requirements, frequency bands and electromagnetic disturbances,”.

[17] “SPICE : A Guide to Circuit Simulation and Analysis Using PSPICE”, Tuinenga, Paul W 2nd ed., Englewood Cliffs, N.J. : Prentice Hall, c 1992.

[18] “SPICE : A Guide to Circuit Simulation and Analysis Using PSPICE”, Tuinenga, Paul W 3rd ed., Englewood Cliffs, N.J. : Prentice Hall, c 1995

[19] “Power Electronics: Principles and Applications”, Vithayathil, Joseph New York : McGraw-Hill, c 1995

[20] “Electronic Principles”, Albert P. Malvino


http://www.casadellibro.com/fichas/fichaautores/0,1463,RIEDEL32SUSAN2A1,00.html?autor=RIEDEL%2C+SUSAN+A.

http://www.casadellibro.com/fichas/fichabiblio/0,1094,2900001030139,00.html?codigo=2900001030139&titulo=ELECTRIC+CIRCUITS+AN+PSPICE+MANUAL+USING+ORCAD+PACKAGE+(7TH+ED.)


http://www.echelon.com/support/documentation/manuals/devtools/078-0299-01E.pdf


http://www.casadellibro.com/fichas/fichabiblio/0,1094,2900000491202,00.html?codigo=2900000491202&titulo=THE+ART+OF+ELECTRONICS+(2ND+ED)



http://www.casadellibro.com/fichas/fichabiblio/0,1094,2900001118831,00.html?codigo=2900001118831&titulo=POWER+ELECTRONICS%3A+CONVERTERS%2C+APPLICATIONS+AND+DESIGN%2C+MEDIA+ENH+ANCED+(3RD+ED.)












http://www.casadellibro.com/fichas/fichaautores/0,1463,NILSSON32JAMES2W1,00.html?autor=NILSSON%2C+JAMES+W.



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[21] “Technician's Guide to Electronic Communications”, Milton Gussow

[22] “Power electronic systems: theory and design”, Upper Saddle River, N.J.: Prentice Hall

[23] “Power electronic circuits”, Hoboken, NJ: John Wiley, c 2004

[24] “Battery management systems: design by modeling”, Dordrecht; Boston: Kluwer Academic, 2002

[25] “Power Electronics and Variable Frequency Drives: Technology and Applications”, Wiley, 2001

[26] “Power Electronics and Controls”, Reston, Reston Pub. Co., c 1985

[27] “Filters and Power Conditioning, Gainesville”, Eckert, Jeffery K. (editor) : Interference Control Technologies, c 1988

[28] “Principles of Electric Machines with Power Electronic Applications, 2nd Ed., Wiley-IEEE Press, 2002. El-Hawary, Mohamed E

[29] “Introduction to power electronics”, Fewson, Denis London: Arnold; New York: Oxford University Press, 1998

[30] “Design and Build Electronic Power Supplies”, Gottlieb, Irving M. 1st ed., Blue Ridge Summit, PA : Tab Books, c 1991

[31] “Introduction to Power Electronics”, Hart, Daniel W Upper Saddle River, N.J. : Prentice Hall, c 1997

[32] “Principles of Power Electronics”, Kassakian, John G., Martin F. Schlecht, and George C. Verghese Reading, Mass. : Addison-Wesley, c 1991

[33] “Simplified Design of Linear Power Supplies”, Lenk, John D. Boston : Butterworth-Heinemann, c 1995

[34] “Controlling Radiated Emissions by Design”, Mardiguian, Michel 2nd ed., Boston, MA : Kluwer Academic Publishers, 2001

[35] “Power electronics : converters, applications, and design”, Mohan, Ned, Tore M. Undeland, William P. Robbins ,Hoboken, NJ: John Wiley & Sons, c 2003

[36] “Power Supplies for Electronic Equipment”, Nowicki, Jerzy Ryszard ,Vols. I and 2, CRC Press, Cleveland, Ohio, 1971

[37] “Noise Reduction Techniques in Electronic Systems”, Ott, H. W. Wiley, 1988

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[39] “Power electronics”, New York: J. Wiley, 1997

[40] “Power Electronics Technology and Applications”, Thollot, Pierre A., (editor) New York City, N.Y. : Institute of Electrical and Electronics Engineers, c 1992

Annexe IDesign tools


http://www.smpstech.com/books/bookt.htm#THOLLO01


The following is description of the design tools used in thesis development:

– PL3120 and PL3150 Evaluation Boards

– Pspice Schematics tool



– P-CAD 2002

– Nodebuilder 3.1



– LonMaker Managed Network tool


Annexe IIFirmware Source Code

Annexe II

//// Actuador

#include <isi.h>#include <mem.h>#include <stdlib.h>#include <control.h>#include <snvt_cfg.h>

#pragma num_alias_table_entries 4

#pragma num_addr_table_entries 5

#pragma enable_io_pullups#pragma codegen optimization_on#pragma codegen cp_family_space_optimization#pragma set_node_sd_string "MGLight"

// Para LonMakernetwork input SCPTnwrkCnfg cp cp_info(reset_required) nciNetConfig = CFG_EXTERNAL;

network input SNVT_switch nviLight;

static IsiCsmoData AcceptMgSwitch = { // group direction width profile nvtype variant ISI_DEFAULT_GROUP, 0, 1, 3, 95u, 0, { 0, 0, isiScopeStandard, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 7} };

device_properties { nciNetConfig};

//// Entradas y Salidas para LEDs y Botones

IO_4 input bitshift numbits(8) clockedge(-) ioButtons;IO_6 output bit ioButtonLd = 1;#define MG_BUTTONS_DEBOUNCE 3

unsigned GetButtons(void) { unsigned Buttons, Index; Buttons = 0xFFu; for(Index = 0; Index < MG_BUTTONS_DEBOUNCE; ++Index) {

Annexe II

// capture parallel lines: io_out(ioButtonLd, 0); // deactivate capture. The 74HC165 requires no more than 100ns for // capture; we cannot beat this even with a 40MHz Smart Transceiver // or Neuron Chip. No need to consider load pulse timing, therefore: io_out(ioButtonLd, 1); // take a sample and debounce: Buttons &= (unsigned)io_in(ioButtons); }

return ~Buttons;}

IO_2 output bitshift numbits(8) ioLEDs;IO_1 output bit ioLEDLd = 1;

unsigned PreviousLEDs = 0;

void SetLEDs(unsigned LEDs, unsigned Mask) { LEDs |= PreviousLEDs & ~Mask; PreviousLEDs = LEDs;

io_out(ioLEDs, ~LEDs); // strobe: io_out(ioLEDLd, 0); io_out(ioLEDLd, 1);}

IsiCsmoData *pData;

eeprom SCPTnwrkCnfg OldNwrkCnfg = CFG_NUL;

//// Reset Processing

when(reset) { unsigned grupo, elemento; SCPTnwrkCnfg cpNwrkConfig; grupo=70; //Lectura de los registros

elemento=7;

pData=&AcceptMgSwitch;

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pData->Group=grupo;pData->Extended.Member=elemento;

SetLEDs(0xFF, 0xFFu); // LEDs into defined state cpNwrkConfig = OldNwrkCnfg; if(cpNwrkConfig == CFG_NUL) { nciNetConfig = CFG_LOCAL; } OldNwrkCnfg = nciNetConfig;

if(nciNetConfig == CFG_LOCAL) { if(cpNwrkConfig == CFG_EXTERNAL) { IsiReturnToFactoryDefaults(); // Call NEVER returns! (resets the device) } scaled_delay(31745UL); // 800ms IsiStartS(isiFlagExtended); //Cambio }

SetLEDs(0x00, 0xFFu);}

mtimer repeating kbTick = 50ul;

#define ISI_BUTTON 0x80u#define ISI_RETURN 0x40u

when(timer_expires(kbTick)) { unsigned Buttons;

Buttons = GetButtons();

if(Buttons & ISI_BUTTON)IsiStartS(isiFlagExtended);

if(Buttons & ISI_RETURN)IsiReturnToFactoryDefaults();

}

when(nv_update_occurs(nviLight)) {

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unsigned LEDs;

LEDs = 0;

if(nviLight.state) LEDs=0xFF; else

LEDs=0x00; SetLEDs(LEDs, 0xFFu);

}

when(wink) { unsigned Index, StoredPreviousLeds; StoredPreviousLeds = PreviousLEDs;

for(Index = 0; Index != 255u; ++Index) { SetLEDs(Index, 0xFFu); delay(100); } SetLEDs(StoredPreviousLeds, 0xFF);}

//// ISI//

mtimer repeating isiTick = 1000ul / ISI_TICKS_PER_SECOND; // 10 times faster than ISI

when(timer_expires(isiTick)) { // Envios periodicos del estado de ISI IsiTickS();

}

when(msg_arrives) { if(IsiApproveMsg()) { if(IsiProcessMsgS()) { // TODO: process unprocessed ISI messages here (if any) ; } } else { // TODO: process other application messages here (if any)

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; }}

void IsiUpdateUserInterface(IsiEvent Event, unsigned Parameter) {

if(Event == isiRun) SetLEDs(0x01, 0xFF); #pragma ignore_notused Parameter}

//// Definicion de la tabla de conexiones de ISI

eeprom IsiConnection MyConnectionTable;

unsigned IsiGetConnectionTableSize(void) { return(unsigned)(sizeof(MyConnectionTable)/sizeof(IsiConnection));}

const IsiConnection* IsiGetConnection(unsigned Index){ return &MyConnectionTable;

#pragma ignore_notused Index}

void IsiSetConnection(IsiConnection* pConnection, unsigned Index) { MyConnectionTable = *pConnection;


//// Override IsiGetNvIndex / IsiGetNextNvIndex with application-specific implementations://unsigned IsiGetNvIndex(unsigned Assembly, unsigned Offset){ return nviLight::global_index; #pragma ignore_notused Offset

#pragma ignore_notused Assembly}

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// Override IsiGetAssembly / IsiGetNextAssembly with application-specific implementations:unsigned IsiGetAssembly(const IsiCsmoData* pCsmoData, boolean Auto) { SetLEDs(0x80, 0xFFu); return memcmp(pCsmoData, &AcceptMgSwitch, sizeof(IsiCsmoData)) ? ISI_NO_ASSEMBLY : 0; #pragma ignore_notused Auto}

unsigned IsiGetNextAssembly(const IsiCsmoData* pCsmoData, boolean Auto, unsigned Assembly) { return ISI_NO_ASSEMBLY;

#pragma ignore_notused pCsmoData#pragma ignore_notused Auto#pragma ignore_notused Assembly

}

// The following override allows developing and debugging of this application in a managed NodeBuilder// development environment. See documentation for further, important, considerations related to debugging// ISI-enabled devices in a managed environment, and regarding the IsiSetDomain override in particular.#ifdef _DEBUG#ifndef _MINIKITvoid IsiSetDomain(domain_struct* pDomain, unsigned Index) { ;#pragma ignore_notused pDomain#pragma ignore_notused Index}#pragma ignore_notused IsiSetDomain#endif#endif

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//// Sensor

//#pragma num_alias_table_entries 10

#include <isi.h>#include <mem.h>#include <stdlib.h>#include <control.h>#include <snvt_cfg.h>

// Definicion de Alia#pragma num_alias_table_entries 10// Definicion de la tabla de direcciones#pragma num_addr_table_entries 4// Directivas#pragma enable_io_pullups#pragma codegen optimization_on#pragma set_node_sd_string "MGSwitch"

// Para LonMakernetwork input SCPTnwrkCnfg cp cp_info(reset_required) nciNetConfig = CFG_EXTERNAL;

network output bind_info(unackd_rpt) SNVT_switch nvoSwitch;

static IsiCsmoData MyCsmo = { // group direction width profile nvtype variant ISI_DEFAULT_GROUP, 0, 1, 3, 95u, 0, { 0, 0, isiScopeStandard, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, 1} };

device_properties { nciNetConfig};

//// Entradas y Salidas para LEDs y Botones//IO_4 input bitshift numbits(8) clockedge(-) ioButtons;IO_6 output bit ioButtonLd = 1;#define MG_BUTTONS_DEBOUNCE 3

unsigned GetButtons(void) { unsigned Buttons, Index; Buttons = 0xFFu;

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for(Index = 0; Index < MG_BUTTONS_DEBOUNCE; ++Index) { // capture parallel lines: io_out(ioButtonLd, 0); // deactivate capture. The 74HC165 requires no more than 100ns for // capture; we cannot beat this even with a 40MHz Smart Transceiver // or Neuron Chip. No need to consider load pulse timing, therefore: io_out(ioButtonLd, 1); // take a sample and debounce: Buttons &= (unsigned)io_in(ioButtons); }

return ~Buttons;}

IO_2 output bitshift numbits(8) ioLEDs;IO_1 output bit ioLEDLd = 1;

unsigned PreviousLEDs = 0;

void SetLEDs(unsigned LEDs, unsigned Mask) { PreviousLEDs = LEDs | (PreviousLEDs & ~Mask);

io_out(ioLEDs, ~PreviousLEDs); // strobe: io_out(ioLEDLd, 0); io_out(ioLEDLd, 1);}

IsiCsmoData *pData;

eeprom SCPTnwrkCnfg OldNwrkCnfg = CFG_NUL; // Almacenamos estado de red

//// Reset Processing

when(reset) { unsigned grupo, elemento;

SCPTnwrkCnfg cpNwrkConfig;

cpNwrkConfig = OldNwrkCnfg;

grupo=70; //Lectura de los registroselemento=7;

pData=&MyCsmo;

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pData->Group=grupo;pData->Extended.Member=elemento;

SetLEDs(0xFF, 0xFFu); // LEDs into defined state

if(cpNwrkConfig == CFG_NUL) { nciNetConfig = CFG_LOCAL; } OldNwrkCnfg = nciNetConfig;

if(nciNetConfig == CFG_LOCAL) { if(cpNwrkConfig == CFG_EXTERNAL) { IsiReturnToFactoryDefaults(); // Call NEVER returns! (resets the device) } scaled_delay(31745UL); // 800ms IsiStartS(isiFlagExtended); //Cambio } SetLEDs(0x00, 0xFFu);}

#define APP_MS_TICK 50#define APP_TICKS_PER_SEC (unsigned)(1000ul/APP_MS_TICK)mtimer repeating kbTick = APP_MS_TICK;

#define ISI_BUTTON 0x80u#define ISI_RETURN 0x40u

unsigned previo=1, unsegund=0;

when(timer_expires(kbTick)) { unsigned Buttons;

Buttons = GetButtons();

if(Buttons & ISI_BUTTON)IsiStartS(isiFlagExtended);

if(Buttons & ISI_RETURN) IsiReturnToFactoryDefaults(); if(Buttons && !unsegund)

{

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if(previo){

previo=0;nvoSwitch.state=TRUE;nvoSwitch.value=1;

}else{

previo=1;nvoSwitch.state=FALSE;nvoSwitch.value=0;

}

}

unsegund++;if(unsegund == 10){

unsegund = 0;}

}

when(wink) { unsigned StoredPreviousLeds; StoredPreviousLeds = PreviousLEDs;

SetLEDs(0x55, 0xFFu); delay(20000ul);

SetLEDs(StoredPreviousLeds, 0xFF);}

//// ISI//

mtimer repeating isiTick = 1000ul / ISI_TICKS_PER_SECOND; // 10 times faster than ISI

when(timer_expires(isiTick)) { // call into the ISI engine IsiTickS(); }

when(msg_arrives) { if(IsiApproveMsg()) { if(IsiProcessMsgS()) {

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// TODO: process unprocessed ISI messages here (if any) ; } } else { // TODO: process other application messages here (if any) ; }}

void IsiUpdateUserInterface(IsiEvent Event, unsigned Parameter) { if(Event == isiWarm && !IsiIsConnected(0)) { IsiInitiateAutoEnrollment(&MyCsmo, 0); SetLEDs(0xFF, 0xFFu); } if(Event == isiRun) { SetLEDs(0x01, 0xFF); }

#pragma ignore_notused Parameter}

void IsiCreateCsmo(unsigned Assembly, IsiCsmoData* pCsmoData){ memcpy(pCsmoData, &MyCsmo, sizeof(IsiCsmoData));

#pragma ignore_notused Assembly}

//// Definicion de la tabla de conexiones para ISI

eeprom IsiConnection MyConnectionTable;

unsigned IsiGetConnectionTableSize(void) { return 1u;}

const IsiConnection* IsiGetConnection(unsigned Index) { return &MyConnectionTable;


void IsiSetConnection(IsiConnection* pConnection, unsigned Index)

Annexe II

{ MyConnectionTable = *pConnection;


//// Override IsiGetNvIndex / IsiGetNextNvIndex with application-specific implementations://unsigned IsiGetNvIndex(unsigned Assembly, unsigned Offset) { return nvoSwitch::global_index;

#pragma ignore_notused Assembly#pragma ignore_notused Offset

}

unsigned IsiGetAssembly(const IsiCsmoData* pCsmoData, boolean Auto) { return ISI_NO_ASSEMBLY; #pragma ignore_notused pCsmoData #pragma ignore_notused Auto}

unsigned IsiGetNextAssembly(const IsiCsmoData* pCsmoData, boolean Auto, unsigned Assembly) { return ISI_NO_ASSEMBLY;

#pragma ignore_notused pCsmoData#pragma ignore_notused Auto#pragma ignore_notused Assembly

}

// The following override allows developing and debugging of this application in a managed NodeBuilder// development environment. See documentation for further, important, considerations related to debugging// ISI-enabled devices in a managed environment, and regarding the IsiSetDomain override in particular.#ifdef _DEBUG#ifndef _MINIKITvoid IsiSetDomain(domain_struct* pDomain, unsigned Index) { ;#pragma ignore_notused pDomain#pragma ignore_notused Index}

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#pragma ignore_notused IsiSetDomain#endif#endif

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