Unleashing NXP’s Cortex-M3 based LPC1700 seriesPresenters- Amit Bhojraj, Amish Desai

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Contents

Introduction

Memory support

Key system blocks

Peripheral support

Tools

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IntroductionKey Family Features

Series Overview

Bridging ARM7 and Cortex-M3

Block Diagram

Cortex-M3 Overview

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LPC17xx Series

Smooth migration from ARM7

Unique Implementations:– MPU– NVIC– WIC– Flash Accelerator– DMA

Tailored for communication with 15 serial interfaces

Low power operation

Industry’s first Cortex-M3 implementation running at 100MHz

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Series Overview

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Bridging Two GREAT Families- ARM7 & Cortex-M3

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LPC2300 Block Diagram

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LPC1700 Block Diagram (Part 1)

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Multilayer AHB Bus Matrix

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Block Diagram (Part 2)

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Cortex-M3 Operating Modes

User

System

FIQ

IRQ

Supervisor

Abort

Undefined

ThreadHandler

Main Stack

Process stack

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Thumb-2 Instruction Set

ARM9 & ARM7– 32-bit ARM Instruction set (code performance)– 16-bit Thumb instruction set (code compression)

Thumb-2 Instruction set– Blend of both instruction set– Around 25% code density over ARM and 25% code performance

over Thumb

Enhanced Instructions– Single cycle multiply & 2-7 cycle hardware divide– If then construct targeted for C compiler

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Bit-Band Regions

*Images From the Cortex-M3 TRM

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LPC1700 Bit Band Regions

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Memory SupportInternal Memories

Flash Accelerator

Booting

Memory Protection Unit (MPU)

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Memory Support

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Memory Support ExplainedOn-chip Flash

– Maximum 512 KB– Zero wait-state performance with Flash Accelerator

On-Chip SRAM– Total 64 KB

• 32 KB SRAM – accessible by the CPU and DMA controller on a higher speed bus

• Two additional 16 KB SRAM – separate slave port on the AHB multilayer matrix.

• Allows CPU and DMA accesses to be spread over 3 separate RAMsthat can be accessed simultaneously.

On-Chip ROM– 8 KB ROM– Flash program/erase APIs

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Flash Accelerator

Just one register configuration- “FLASHCFG”

Configuring Flash Timing– 100MHz, 80MHz, 60MHz, 40MHz and 20 MHz

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Booting

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Memory Protection Unit (MPU)Support for 8 regions and each region can be broken up into 8 sub-regions

MPU provides full support for:– Region protection– Overlapping protection regions– Access permissions– Exporting memory attributes to the system

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MPU- Region Access

http://infocenter.arm.com/help/topic/com.arm.doc.ddi0337e/DDI0337E_cortex_m3_r1p1_trm.pdf

*Image From the Cortex-M3 TRM

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Key System BlocksClocking

Nested VIC

Wakeup Interrupt Controller (WIC)

DMA Support

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Clock Structure (Inputs)Internal RC oscillator

– Clock source for the WDT, and/or as the clock that drives the PLL and subsequently the CPU

– The nominal IRC frequency is 4 MHz ± 1% accuracy over the entire temp and voltage range

Main oscillator– Clock source for the CPU, with or without using the PLL.– The main oscillator also provides the clock source for the dedicated USB

PLL– Operates at frequencies of 1 MHz to 25 MHz

RTC oscillator– Clock source for the RTC block, the main PLL, and subsequently the CPU.– 1 Hz clock to RTC

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Clock Structure (PLLs)

Main PLL (PLL0)– Input clock frequency in the range of 32 kHz to 50 MHz. – May run from the main oscillator, the internal RC oscillator, or the

RTC oscillator– Output frequency to the max. CPU rate

USB PLL (PLL1)– Input clock frequency from the main oscillator only (10-25MHz)– Output frequency of 48MHz used only by the USB subsystem– Dedicated to provide clocking for the USB interface to allow added

flexibility for the main PLL settings

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Clocking Explained

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Clock OUT

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NVIC Interrupt LatencyDeterministic interrupt latency

Cortex-M3 has an interrupt latency of 12 cycles and 12 cycles to returnfrom servicing

ARM7 has an interrupt latency of 24 - 42 cycles and 16 cycles to return from servicing

PUSH PUSHISRCortex-M3

IRQ

12 12

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NVIC Interrupt Tail ChainingIn the case of back-to-back interrupts, traditional systems would repeat the complete state save and restore cycle twice, resulting in higher latency

Tail-chaining achieves much lower latency by replacing serial stack pop and push actions that normally take over 30 clock cycles with a simple 6 cycle instruction fetch.

*Image From ARM Website

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NVIC Key Features

Priority– A programmable priority level of 0-31 for each interrupt. A higher

level corresponds to a lower priority, so level 0 is the highestinterrupt priority

– Grouping of priority values into group priority and sub-priority fields

Stack Operations– The processor automatically stacks its state on exception entry and

unstacks this state on exception exit, with no instruction overhead

An external Non-maskable interrupt (NMI)

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DMA Support

AHB Bus master

Eight DMA channels with a four-word FIFO per channel

SSP, I2S, UART, ADC & DAC. DMA can also be triggered by a timer match condition

Single and burst requests supported

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Peripheral Support15 Serial Interfaces

Timers

Motor Control

Analog Blocks

General Purpose IO

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10110101

10100101101101100111100000100000

10100101101101100

15 Serial Interfaces

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SPI0/ SSP(0 &1)SPI controller (Serial Peripheral Interface)

– Synchronous, Serial, Full Duplex Communication.– SPI master or slave.– 8 to 16 bits per transfer– Programmable clock polarity and phase for data transmit/receive

operations– Maximum possible speed of the SPI (master/slave) 12.5 Mbits/sec

SSP controller (Synchronous Serial Communication)– 8 Frame FIFO’s for both Transmit and Receive and multi-protocol

capabilities. – 4 to 16 bits frame sizes– DMA support– Maximum possible speed of the SSP 50 Mbits/s (Master Mode), 8 Mbits/s

(Slave Mode)

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I2C (0,1 & 2)I2C compliant bus interface, and can be configured as Master, Slave, or Master/Slave.

Bi-directional data transfer between masters and slaves

Supports Fast Mode Plus (I2C0 only)

SDA

SCL

I2CInterface

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I2SSupports 3-wire data transmit and receive OR

4-wire combined transmit and receive connections

Audio Master Clock input/output (used on many I2S codecs)

The I2S input and output can each operate independently in both master and slave mode.

CKLPC1700

NXPSD

WS

MCLK

CK Audio Codec

SD

WS

MCLK

Dig

ital I

nter

face

Ana

log

Inte

rface

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UARTs (0, 1, 2 & 3)

16 byte Receive and Transmit FIFOs with DMA support

Fractional divider for baud rate control, auto-baud capabilities, and implementation of software or hardware flow control

EIA-485/RS-485 and 9-bit mode supportModem control support

IrDA support for infrared communication

UART1 is identical to UART0/2/3, with the addition of a modem interface and RS-485/EIA-485 modes, no IrDA support

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CAN (1 & 2) & EthernetCAN2.0B controllers (Controller Area Network)

– Full implementation of the CAN-Protocol according to the CAN Specification Version 2.0B

– Data rates to 1 Mbit/s on each bus– Built-in Hardware Acceptance Filter recognizes 11- and 29-bit Rx

Identifiers

Ethernet Interface– Contains a Ethernet MAC (Media Access Controller) with RMII

interface (reduced Media Independent Interface)– Supports 10 or 100 Mbps PHY devices – Dedicated DMA controller– Fully compliant with 802.3x Full Duplex Flow Control and Half

Duplex back pressure

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USBUSB 2.0 Full Speed (12 Mbps) Device and On-The-Go/Open Host Control Interface.

Built-in on-chip PHY for Device/Host functions

Dedicated DMA controller

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Timers

Four General Purpose timers

Watchdog timer

Repetitive interrupt timer

PWM (Timer operation)

Systick timer

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Timers (1)General Purpose Timers

– Total 8 capture inputs, and 4 external match outputs – Timer as counter or timer mode. – Selected timer events can selectively generate DMA requests. This allows

for timed memory-to-memory transfers.– Match output can toggle, go high, go low or do nothing

Watchdog Timer– Enabled by software but requires a hardware reset or a Watchdog

reset/interrupt to be disabled– Can be used in Deep Sleep mode– Debug mode (interrupt)

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Timers (2)

Repetitive Interrupt Timer (RIT)– An interrupt is generated when the counter value equals the

compare value, after masking

PWM timer– Seven match registers allow up to 6 single edge controlled or 3

double edge controlled PWM outputs, or a mix of both types. The match registers also several operations at match

– May be used as a standard timer if the PWM mode is not enabled– Two 32 bit capture channels take a snapshot of the timer value

when an input signal transitions. A capture event may also optionally generate an interrupt

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Timers (3)Systick Timer

– 24-bit timer that counts down to zero and provides 10 millisecond time interval between interrupts

– Can be clocked internally by the CPU clock or by a clock input from a pin (STCLK)

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Motor Control PWM (MCPWM)Optimized for three-phase AC and DC motor control

The MCPWM contains three independent channels, each including:– a 32-bit Timer/Counter (TC), a 32-bit Limit register (LIM), a 32-bit Match

register (MAT), a 10-bit dead-time register (DT) and an associated 10-bit dead-time counter, a 32-bit capture register (CAP)

– two modulated outputs (MCOA and MCOB) with opposite polarities– a period interrupt, a pulse-width interrupt, and a capture interrupt

Three PWM (match) outputs each with opposite polarities, edge or center aligned, and programmable dead-band insertion

Feedback inputs are provided to automatically sense rotor position and use that information to ramp speed up or down

An abort input is also provided that causes the PWM to immediately release all motor drive outputs

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Motor Control PWM

TC

LIM

MAT

DT

CAP

MCOA0 MCOB0 MCOA1 MCOB1 MCOA2 MCOB2

Channel 1 Channel 2

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Motor Control- An Overview

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Quadrature Encoder Interface (QEI)The digital pulses from an external quadrature encoder wheel can be decoded to integrate position over time and determine direction of rotation

– By monitoring both the number of pulses and the relative phase of the two signals, position, direction of rotation, and velocity can be tracked

– The Index signal (3rd signal) can be used to reset the position counter – In addition, it can capture the velocity of the encoder wheel

Position Monitoring– Tracks encoder position and increments/ decrements depending on

direction– Three position compare registers with interrupts– Programmable for 2X or 4X position counting.

Velocity Monitoring– Velocity capture using built-in timer with a compare function with interrupt– Uses 32-bit registers for position and velocity.

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QEI Explained

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QEI Block Diagram

Digital Filter

Quad Encoder

Velocity Timer

Velocity Counter

Velocity Compare

Velocity Reload

Velocity Capture

Ph APh B

IndexPC

LK

CLK

Velocity InterruptRST

Low Velocity Interrupt

Position Counter

Position Compare 0

Position Compare 1

Index Counter

Index Compare

Direction Interrupt Position

Interrupt 0

Position Interrupt 1

Revolution Interrupt

Phase ErrorInterrupt

CLK

CLK

Encoder ClockInterrupt

INX

Index Interrupt

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Analog Blocks- 12-bit ADC Measurement range 0 V to VREFP (typically 3 V; not to exceed VDDA voltage level)

12 bit conversion rate of 1 MHz

Burst conversion mode for single or multiple inputs

Optional conversion on transition on input pin or Timer Match signal.

Select ChannelADCR (7:0)

3 0127 56 4

12-bit ADC

ADC Inputs

VREFN

ADDR0

ADDR7

VREFPV3A VSSA

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Analog Blocks (contd.)

10 Bit DAC (Digital to Analog Converter)– 10 bit digital to analog converter– Resistor string architecture– Buffered output– Power-down mode– Selectable speed vs. power

Power-on-Reset (POR)

BOD– Two thresholds- 2.65V & 2.95V

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RTC Domain

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RTC FeaturesMeasures the passage of time to maintain a calendar and clock

– Provides seconds, minutes, hours, day of month, month, year, day of week, and day of year

Ultra-low power design to support battery powered systems. Less than 1 uA required for battery operation

– Uses power from the CPU power supply when it is present

20 bytes of Battery-backed storage and RTC operation when power is removed from the CPU

Dedicated 32 kHz ultra low power oscillator with dedicated battery power supply pin

RTC power supply is isolated from the rest of the chip

RTC will work down as low as 2.1 V

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General Purpose I/O (GPIO)

70 High Speed GPIOs (LQFP100) and 52 High Speed GPIOs (LQFP80)

All pins have configurable pull-ups/pull-downs

New configuration - open-drain mode (applies to all GPIO pins)

GPIO registers are located on a peripheral AHB bus for fast I/O timing

GPIO registers are accessible by the GP DMA

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GPIO & External InterruptsExternal interrupt inputs

– Up to 46 edge sensitive interrupt inputs (42 GPIO + 4 EINT) combined with up to four level sensitive external interrupt inputs (EINT pins) as selectable pin functions

– The external interrupt inputs can optionally be used to wake up the processor from Power-down mode

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Power ManagementPower Domains

Power down modes

Wakeup Interrupt Controller (WIC)

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Power domainsSingle 3.3 V power supply (2.4 V to 3.6 V)

– VDD(reg)(3V3) – on-chip voltage regulator– VDD(3V3) – I/O pads

VBAT pin (2.1 V to 3.6 V) – Power only to the RTC– No Battery RAM– Backup Registers

12 Bit ADC (2.7 V to 3.6 V) – VDDA – VREFP

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Power Modes (1)Active Power options

– Wide rage of clock sources to static clocking– Ability to divide down or shut off clocks to individual on-chip peripherals

Power reduced modes– Sleep

• CPU execution is suspended

• Peripherals continue running

• (Similar to Idle Mode on ARM7)

– Deep-Sleep• Main oscillator and all internal clocks except the IRC are stopped

• Flash memory is in standby, ready for immediate use

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Power Modes (2)Power reduced modes

– Power-down• Same as Deep-Sleep mode except Flash and IRC are shut down

• State is preserved

– Deep power-down• All clocks including IRC are stopped. Internal voltage is turned off

• Complete system state is lost, only special registers in the RTC domain are preserved

• Exit >>> reset, external pin, or RTC Alarm

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Wakeup Interrupt Controller (WIC)

Enables the chip to wake up from Deep Sleep and Power down mode (without the use of NVIC)

Completely controlled in hardware (no programming required)

Interrupts used:– NMI, External Interrupts EINT0 through EINT3, GPIO interrupts,

Ethernet Wake-on-LAN interrupt, Brownout Detect, RTC Alarm, CAN activity interrupt and USB activity interrupt

– In addition, the watchdog timer can wake up the part from Deep Sleep mode if it is clocked by the IRC oscillator

Only available in Release 2 of Cortex-M3

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Tools

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Emulation and debuggingDebug and trace functions are integrated into the ARMCortex-M3.

Standard JTAG debug (5 pin)

Serial wire debug (SWD) (two pin)

Embedded Trace Macrocell (ETM) interface for real-time trace

Support up to eight breakpoints and four watchpoints.

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Overview of SW and Trace Pins

6363

LPC1700 Tools HighlightsEvaluation boards

– Embedded Artists– Hitex LPC17xx-Stick– IAR KSDK-LPC17xx– Keil MCB17xx

IDEs– ARM/Keil µVision3– CodeRed RedSuite– Hitex HiTOP– IAR Embedded Workbench for ARM

JTAG debuggers– All debuggers supporting Cortex-M3

Plus many more tools available!

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