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Modeling and Simulation

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Decoupling of IonDiffusivity andElectromobility in PorousDielectrics

Editor of portion(s)Ye Fan, Rizwan Ali, SeanW. King, Jeff Bielefeld andMarius K Orlowski

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Decoupling of IonDiffusivity andElectromobility in PorousDielectrics

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Modeling and Simulationof Cu Diffusion in PorousLow-k Dielectrics ECSTrans. 2017 volume 77,issue 5, 121-132


Modeling and Simulationof Cu Diffusion in PorousLow-k Dielectrics

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Modeling and Simulationof Cu Drift in Porous Low-kDielectrics.


Modeling and Simulationof Cu Drift in Porous Low-kDielectrics

Editor of portion(s) Rizwan Ali, Sean W. Kingand Marius K Orlowski

Author of portion(s) Rizwan Ali, Sean W. Kingand Marius K Orlowski

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Name: Rizwan Ali

Description of item under review for fair use: Fig. 1.1 Technology scaling according to Moore's Law [100]. Source: ITRSRoadmap (2009).

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Draft 09/01/2009





Name: Rizwan Ali

Description of item under review for fair use: Fig. 1.2 90 nm interconnect technology on 300 nm wafer with six levels of metal(Photo courtesy, Intel Corp.).



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Name: Rizwan Ali

Description of item under review for fair use: Fig. 1.3 Schematic of an abstract circuit representing the interconnect structure .Source: M. He and T. Lu, Metal Dielectric Interfaces in Giga-scale Electronics, Springer Series.



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Name: Rizwan Ali

Description of item under review for fair use: Fig. 1.4 Trend of interconnect and gate delay as technology scales. Source ITRSRoadmap 1999.



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Name: Rizwan Ali

Description of item under review for fair use: Fig. 1.5 schematic of the Cu interconnect structure. The metal barrier anddielectric capping layer are to block Cu penetration into ILD. Source: M. He and T. Lu, Metal Dielectric Interfaces in Giga-scale Electronics, Springer Series in Materials Science (2012).



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Name: Rizwan Ali

Description of item under review for fair use: Fig. 1.6 Roadmap of dielectric constant given by ITRS. Source: ITRS Roadmap2009.



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Name: Rizwan Ali

Description of item under review for fair use: Fig. 1.7 Embedding RS devices in CMOS back-end would reduce logic-memorylatency. Source: N. Xu, EE 290D, Fall 2013, University of California, Berkeley.



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Name: Rizwan Ali

Description of item under review for fair use: Fig. 1.9 (Left) Crossbar architecture to implement RS in a dense packing. Source:J.J. Yang, D.B. Strukov & D. R. Stewart, Nature Nanotechnology 8, 13-24 (2013). (Right) Cu/TaOX/Pt RS devicesimplemented in crossbar achitecture by G. Ghosh. Source: G. Ghosh, MS Thesis, Virginia Tech (2015).



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Name: Rizwan Ali

Description of item under review for fair use: Fig. 1.10 Owing to non-requirement of a Si substrate and a simple structure,possibility to embed RS devices in CMOS back-end has been proposed in many literatures. Source: J.J. Yang, D.B. Strukov &D. R. Stewart, Nature Nanotechnology 8, 13-24 (2013).



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Name: Rizwan Ali

Description of item under review for fair use: Fig. 1.13 Switching process in CBRAM due to [O] vacancy filament. Source: T.Liu, PhD. Dissertation, Virginia Tech (2013).



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Name: Rizwan Ali

Description of item under review for fair use: Fig. 1.15 Hybrid nanofilament model, four CFs are shown: a monolithic Vo CF, amonolithic Cu CF, a hybrid Vo/Cu CF and a Cu/Vo CF. Source: Y. Kang, Ph.D. dissertation, Virginia Tech (2015).



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Name: Rizwan Ali

Description of item under review for fair use: Fig. 1.16 VFORM increases linearly with electrolyte thickness, while VSET hasno relation. Source: C. Schindler, G. Staikov, and R. Waser, Appl. Phys. Lett. 94, 072109 (2009).



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Name: Rizwan Ali

Description of item under review for fair use: Fig. 1.17 Dependence of the ON resistance on the compliance current. Source: Y.Bernard, V. T. Renard, P. Gonon, and V. Jousseaume, Microelectronic Engineering, vol. 88, no. 5, pp. 814–816, (2011).



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Name: Rizwan Ali

Description of item under review for fair use: Fig. 1.18 VSET vs sweep rate v for Cu/SiO2/Ir cells. A logarithmic relation isobserved for v > 10mV/s, but below that, a critical VSET is approached. Source: C. Schindler, G. Staikov, and R. Waser, Appl.Phys. Lett. 94, 072109 (2009).



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Name: Rizwan Ali

Description of item under review for fair use: Fig. 2.6 Schematic diagram of positive and negative lithography. Source:Photolithography, http://www2.ece.gatech.edu/research/labs/vc/theory/photolith.html



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Name: Rizwan Ali

Description of item under review for fair use: Fig. 2.8 Schematic illustration of the electron beam deposition. Source: T. Liu,PhD. Dissertation, Virginia Tech (2013).



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Name: Rizwan Ali

Description of item under review for fair use: Fig. 2.12 TCR of Cu/TaOx/Pt different Icc; (a) TCR of Cu CF for Pt devices (Icc= 10 μA); (b) TCR of Cu CF for Pt devices (Icc = 10 mA). Source: Y. Fan, MS. Thesis, Virginia Tech (2016).



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Name: Rizwan Ali

Description of item under review for fair use: Fig. 2.13 TCR of (a) Cu CF and (b) VO CF. Source: T. Liu, M. Verma, Y. Kangand M. K. Orlowski, “Coexistence of Bipolar and Unipolar Switching of Cu and Oxygen Vacancy Nanofilaments inCu/TaOx/Pt Resistive Devices,” ECS Solid-State Lett. 2012, vol.1, issue 1, pp q11q13



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Name: Rizwan Ali

Description of item under review for fair use: Fig. 2.15 Cross-section of the devices received in the first phase andcharacterized by Ye Fan. Source: Y. Fan, S. King, J. Bielefeld, M. Orlowski, ECS Trans. 72(2), 35-50 (2016).



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Name: Rizwan Ali

Description of item under review for fair use: Fig. 2.18 Plot of the resistance as a function of the inverse value of the area of thetop electrode in 635-Pt. Source: Y. Fan, S. King, J. Bielefeld, M. Orlowski, ECS Trans. 72(2), 35-50 (2016).



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Name: Rizwan Ali

Description of item under review for fair use: Fig. 2.19 Resistance as a function of temperature for a sample that has beenfound highly conductive from the beginning. Source: Y. Fan, S. King, J. Bielefeld, M. Orlowski, ECS Trans. 72(2), 35-50(2016).



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Name: Rizwan Ali

Description of item under review for fair use: Fig. 2.20 Plot of the resistance as a function of the inverse value of the area of thetop electrode in 635-Pt. Source: Y. Fan, S. King, J. Bielefeld, M. Orlowski, ECS Trans. 72(2), 35-50 (2016).



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Name: Rizwan Ali

Description of item under review for fair use: Table 2.3 Forming voltages at positive bias for the four type of devices tested byYe Fan. Source: Y. Fan, MS. Thesis, Virginia Tech (2016).



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Name: Rizwan Ali

Description of item under review for fair use: Fig. 2.21 Resistance as a function of temperature for a filament formed in 391-Wat positive bias (Vform = 0.58 V) and 391-W at negative bias (Vform = -0.73 V), and 388-W (25% porosity) at positive bias(Vform = 2.2 V). Source: Y. Fan, S. King, J. Bielefeld, M. Orlowski, ECS Trans. 72(2), 35-50 (2016)



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Name: Rizwan Ali

Description of item under review for fair use: Fig. 5.2 Binary phase diagrams for Cu-W and Cu-Ir. In both diagrams, almost nosolubility is observed till 1000K. Source: P.R. Subramanian, D. J. Chakrabarti and D.E. Laughlin (eds.), Phase Diagrams ofBinary Copper Alloys, ASM International, Materials Park, OH, 1994.



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Name: Rizwan Ali

Description of item under review for fair use: Fig. 5.6 Schematic depiction of the barrier failure mechanism in Cu/Ru/Si: (a)Before barrier breakdown, (b) initiation of barrier breakdown with the nucleation of Ru2Si3, (c) complete consumption Ru toform Ru2Si3, and (d) diffusion of Cu through the Ru2Si3 to form Cu3Si in the substrate. Source: M. Damayanti, T. Sritharan,S.G. Mhaisalkar, E. Phoon and L. Chan, Journal of Materials Research, Vol 22, Issue 92007, pp. 2505-2511 (2007).



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Name: Rizwan Ali

Description of item under review for fair use: Fig. 5.7 Cross-sectional TEM image of as-deposited Cu/Ru thin film on Si (100)showing Ru thin film’s columnar microstructure, (b) the Cu/Ru/Si sample vacuum annealed at 550°C, showing thin filmdelamination as well as diffusion into the Si substrate. Source: R. Chan, T. N. Arunagiri, Y. Zhang, O. Chyan, R. M. Wallace,M. J. Kim and T. Q. Hurd, Electrochemical and Solid-State Letters, 7 (8) G154-G157 (2004).



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