thinfilm electronics commercializing printed memory and integrated systems
DESCRIPTION
Thinfilm Electronics Commercializing Printed Memory and Integrated SystemsTRANSCRIPT
Technical development in commercializing printed memory and integrated systems Christer Karlsson, Ph. D. CTO Thin Film Electronics ASA
Thinfilm introducBon Mem
ory Standalone
memory for toys and games
Mem
ory + Logic Addressable memory for integraBon
Integrated Systems Sensor tags
Display tags Wireless
• Strong IP posi-on in unique and cri-cal memory technology
• Secured partnerships and other technology components for integrated systems
Thinfilm ferro-‐electric memory
BoHom Electrode (BE) = WL
FE Polymer
Top Electrode (TE) = BL
• Non-‐volaBle • Rewritable • Excellent retenBon
Memory product development
• Mass producBon (R2R
prinBng) at our partner
InkTec (South Korea)
• Process development at
Thinfilm
– Currently S2S; will be R2R.
• Gravure prinBng
• Slot die coaBng
• Screen prinBng
• Test speed: up to 10M memories per month equivalent to 200M cells/month.
• Step-‐and-‐go principle • 6 memories are currently
tested in parallel.
R2R tesBng
5
R2R tester data
0-‐signal: blue dots indicate polarizaBon by ferro-‐electric switching. 1-‐signal: red dots indicate polarizaBon by bulk capacitance.
Data here from > 50000 cells printed roll-‐to-‐roll.
Thinfilm Electronics confidenBal
Q1
Q0
Cell number
Signal charge
Sorted (no defects)
Unsorted
ProtecBon of memories • Hard scratch protecBon: Significant yield drop
• The soluBon is a two-‐step coaBng process:
– A first layer that is a flexible and handle mechanical stress
– A second layer that is hard and scratch resistant
Type Yield loss (%)
Cross-‐linkable PPG 0%
Natural rubber 0%
Polyvinylacetate 0%
Cross-‐linkable PDMS Low
Highly flexible acrylates Moderate
Flexible acrylates High
Epoxides High
Epoxide/acrylate hybride High
AliphaBc isocyanate High
Transistor fabricaBon steps
2. 4.
1. 3. 5.
6.
# Layer Material Initial process Target process
- Substrate PEN foil - -
1 Planarization Polymer Spin coating Slot die/-
2 S/D electrodes Ag Evaporation or Inkjet Gravure
3 S/D treatment SAM Spin coating Printing or Immersion
4 Semiconductor Organic Spin coating or Inkjet Gravure
5 Gate insulator Polymer Spin coating Gravure or Screen
6 Gate electrodes Ag Evaporation or Inkjet Gravure
p-‐channel OTFTs with printed S/D, OSC, GI and G
L = ~30 µm
W = 650 µm
Ci = 4 nF/cm2
µsat = ~0.5 cm2/Vs @ 20 V
ION/IOFF = ~104
Layer Material Deposi-on process Source-‐drain electrodes Ag Gravure Semiconductor Organic Gravure Gate insulator Polymer Screen Gate electrodes Ag Gravure
n-‐channel OTFTs with printed S/D, OSC and G
L = ~35 µm
W = 2000 µm
Ci = 4.5 nF/cm2
µsat = ~0.3 cm2/Vs @ 20 V
ION/IOFF = ~105
Layer Material Deposi-on process Source-‐drain electrodes Ag Gravure Semiconductor Organic Gravure Gate insulator Polymer Spin coaBng Gate electrodes Ag Gravure
Temperature tag proof-‐of-‐concept prototype
2-‐bit memory Thinfilm
TFT circuits PARC
Thermistor bridge PST
Electrochromic display ACREO
Backplane and Integra-on Thinfilm and PARC
4 printed devices/technologies integrated on the same printed plasBc backplane
Trigger circuitry supported by Flextech
Tag block diagram
Temp sensor
Threshold trigger
Amplifier/Buffer
Pulse generator
External electronics Display
Memory
Trigger circuitry supported by Flextech
• Basic funcBonality achived! • CalibraBon needed using current processes
Q&A Further quesBons: [email protected] +46 702 157921