the potential and challenges of concurrent test...the potential and challenges of concurrent test...

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THE POTENTIAL AND CHALLENGES OF CONCURRENT TEST [email protected] “New Challenges In DFT” – Cambridge, April16th 2015 Because Technology Never Stops

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  • THE POTENTIAL AND CHALLENGES OF

    CONCURRENT TEST

    [email protected]

    “New Challenges In DFT” – Cambridge, April16th 2015

    Because Technology Never Stops

  • Test Time Reduction

    WHAT IS CONCURRENT TEST ?

    2

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    SERIALIZED

    FLOW

    Test

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    Tests

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    Tests

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    Device trends: Higher complexity Greater integration IP-based architecture

    Concurrent Test =

    Parallel test of independent device blocks

    2-LEVEL

    CONCURRENCY

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    ck B

    Tests

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    Tests

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    Tests

    SCA

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    Test

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    3-LEVEL

    CONCURRENCY

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    ck B

    Tests

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    Tests

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    ck C

    Tests

    SCA

    N T

    est

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    Block

    A Block

    B

    Block

    C DUT

  • ATE ARCHITECTURES AND CONCURRENT CAPABILITY

    3

    MAGNUM

    Tester per board • Up to 40 boards • 128 IOs + 16 supplies / board • Controller and patgen / board • External RF instrument

    Patgen per board • Up to 16 boards • 128 IOs / board • 2 Patgens per board • Separate analog instruments • Sync. through digital channel

    or pattern microcode

    J750 + RF tester • Upgrade to any J750 • LitePoint instrument is a full

    tester (Src, Cap, processing) • Sync via code or digital

    channels

    Multi-time domain • Complex SOC tester • Large instrumentation offering • Multiple time domains per

    instrument • Multiple flow domains • Protocol-aware engines • Sync-link technology • background DSP • Deferred Limits & Datalog

    Complexity & Capability

  • MOTIVATION FOR CONCURRENT TEST

    Reduce test time Objections to this are rare

    Situations where increasing parallelism is not an option (questionable ROI, high product mix with little high runners, handler limited …)

    Gain is application dependant, typically double digit number

    Preserve or adopt an IP-based test strategy As opposed to system-level optimization (reduced pin-count etc…)

    Particularly beneficial for SIP

    Reduce or optimize investment May appear devious or counter nature

    Concurrent test can allow to reduce test time .. or configuration !

    As long as a test runs concurrently it doesn’t matter how long it takes (share costly resources)

    Improve test Coverage uncommon

  • CONCURRENT TEST IN THE DEVELOPMENT CYCLE

    Capitalize on Cost-of-Test savings asap

    Device design enables Concurrent Test

    Tester configuration addresses Site Count and

    CT flow

    Tester SW enables fast CT implementation and

    debug

    Dev

    ice

    Vo

    lum

    e

    1st Si Samples

    Volume Shipment

    Functional Characterization

    MultiSite/TTR/CT

    Faster Time to Profit

    Market pressure

  • APPRAISING CONCURRENT TEST

    Shortest path to FAILURE

    CT is a Test Program Optimization

    technique

    My device already works concurrently

    It just takes a “concurrent” tester

    It’s trivial

    Safest path to SUCCESS

    CT is part of my DFT strategy

    I need to review the constrains that CT

    sets on the device

    I need a clear understanding of the

    tester architecture and capability

    I need to define my concurrent test

    strategy early on

    Concurrent Implementation

    Concurrent Planning

    Tester Device

  • PLANNING PHASE

    What tests CAN run concurrently?

    • Device conflicts

    • Tester configuration

    What tests SHOULD be run concurrently?

    • Find the optimal concurrent flow

    Evaluating manually gets laborious for complex SOC :

    • 1000s of tests leads to millions+ combinations

    • Satisfying tester rules is getting complex with high levels of concurrency

    Need a tool to:

    • capture rules

    • flag conflicts

    • runs scenarios and provides results

    Concurrent Test

    strategy

    Device Architecture

    Test System Configuration

    & Architecture

    Test Time Estimates

  • CONCURRENT TEST PLANNING PROCESS

    Define test blocks

    Identify device resources used (by-block)

    Identify tester resources required (by-block)

    Find valid concurrent flows

    Choose and execute *best* option

    • Group tests by similar device and tester usage • Typically < ~15-20 blocks

    • DUT pins, internal resources, etc. • Will define what concurrency the device can support

    • Used to find tester channel assignments that satisfy for the tester rules for a given concurrent flow

    • Discard flows with device conflicts • Attempt to find valid concurrent blocks

    • Best Cost-of-Test balance of: o tester configuration o site count o Concurrent flow

    iterate

  • CT DESIGN WITH CTEXPERT

    Tester Configuration & Usage by Block

    Device Requirements & restrictions

    Test time estimate Per Block

    CONFLICTING BLOCKS

    RESULTS FOR ALL SCENARIOS

    Optimal CT Flows

  • DEVICE CONSIDERATIONS

    Understand Device Block Independence

    access to device block are all signals available shared output pins shared test access pins

    access to control registers / data shared interface (JTAG, SPI …) registers separation test mode entry

    shared signals / functions reset power supplies test mode entry clock domains

    Interference crosstalk noise power consumption power dissipation

    scan which in/out pins can cause resource mapping conflict (scan optimization vs

    concurrent requirements)

    10

    Block A Block B

    Block C Block D

    DUT

    Concurrent Test Starts

    at the DESIGN STAGE,

    requires test eng for

    tester capability

    discussion

    Teradyne Confidential

  • IMPLEMENTATION PHASE: CHALLENGES

    Challenges

    Time to Convert

    Program to CT

    Hard to debug

    CT flow complex to

    optimize

    Identifying the

    optimal CT flow

    Teradyne Confidential 11

    Minimize Development Time Optimize Concurrent Test Efficiency

    CTExpert Test Solution Planning

    Multi-sheet Support Collaborative development

    CTExec Serial / Concurrent Execution

    TimeLines

  • CONCURRENT TEST PROOFS

    12 Teradyne Confidential

    Device Sites Concurrency

    Level TT Savings (%) Comment

    Mobile Baseband SiP

    Analog

    Digital

    2 2 41%

    DVD device 1 2 33%

    Mobile Integrated Cellular RF Tx/Rx

    PMIC

    ABB

    DBB, USB

    4 3 25%

    Mobile Baseband SiP

    ABB

    DBB

    4 2 6.9%

    Device limited

    - shared control bus

    - unavoidable device

    resets

    - sensitive tests run serially

  • CONCLUSION

    13

    Concurrent testing can be applied to various extents and

    various degrees of complexity

    Reducing Cost Of Test is the main objective

    ATE platforms support Concurrent test in various ways -

    each have their specific rules and constrains

    Successful implementation of Concurrent Test requires

    careful planning and DFT

  • TO LEARN MORE ABOUT CONCURRENT TEST

    Talk to your local Teradyne Representative

    (number available on demand)

    14