“Impact of Low-Voltage Devices on Test and Inspection”

Teradyne Assembly Test Division Website: www.teradyne.com/cbti

Michael J SmithMichael.J.Smith@Teradyne.com

What’s Driving the Use of Low Voltage Devices?• Cramming more components onto

integrated circuits-“With unit cost falling as the number of

components per circuit rises, by 1975 economics may dictate squeezing as many as 65,000 components on a single silicon chip.”

Gordon E. Moore April 19th 1965

What’s Driving the Use of Low Voltage Devices?• Increasing functionality

– Speed

– Memory

– Colour

– Extended operation

– Small size

• Disk drives

– Larger size

• 42-inch displays

What’s Driving the Use of Low Voltage Devices?• Environmental concerns

– Reduce power consumption

• Pd = F x C x V²

– Restrict heat generation.

• Reduce air-conditioning

• Less temperature differentiation

14

3º

38º

149º C Alternator Surface

Current Air Flow Dynamics

90º to

110º

90º to 110º

Road Surface 66º C

Engine Block 129 °C

Exhaust System >600

°C

Engine Oil 148°CTransmission Oil 148 °C

129º C Ignition Surface

14

3º

38º

149º C Alternator Surface

Current Air Flow Dynamics

90º to

110º

90º to 110º

Road Surface 66º C

Engine Block 129 °C

Exhaust System >600

°C

Engine Oil 148°CTransmission Oil 148 °C

129º C Ignition Surface

What’s Driving the Use of Low Voltage Devices?• New functions

– Wireless communication.

• 3G, WiFi, Bluetooth

– Combining functions

• Cell phone

– PDA,

– Cameras

– GPS

– Video

What’s Driving the Use of Low Voltage Devices?• The future?

– MP3 Jukebox

– Portable Mpeg4 video players

– Nanotechnology

– Remote vehicles

What’s Driving the Use of Low Voltage Devices?• The future?

– Personal server

– Tele-health

– Security

The Next Generation Technology Challenge: Intel’s 2004 Desktop Platform Vision

GMCHGMCH

1 PATA port1 PATA port

Next GenerationNext GenerationInt. Gfx coreInt. Gfx core

PCI Express* x16PCI Express* x16Discrete GraphicsDiscrete Graphics

Azalia Audio Azalia Audio ArchitectureArchitecture

800MHz FSB800MHz FSB

4 Serial ATA ports4 Serial ATA ports

RAID0/1RAID0/1AHCIAHCI11

Hyper-ThreadingHyper-Threading Technology Technology

8 Hi-Speed USB 8 Hi-Speed USB 2.0 Ports2.0 Ports

4 PCI Express* x1 lanes4 PCI Express* x1 lanesPCI PortsPCI Ports

Platform SoftwarePlatform Software

Dual ChannelDual ChannelDDR2-533DDR2-533

MCH

ICH

Higher integration - Smaller gate geometries - Lower voltages

The Next Generation Technology Challenge: Intel’s 2004 Desktop Platform Vision

• DDR SDRAM @ 2.5 V

• Front Side Bus @ 1.2 V

• Rambus 64Bit @ 1.8 V

• HUB Interface @ 1.5 V

• AGP 3.0 @ 1.5 V

Source : Intel Corp.

Process P854 P856 P858 Px60 P1262 P1264 P1266 P12681st Production 1995 1997 1999 2001 2003 2005 2007 2009

Lithography 350nm 250nm 180nm 130nm 90nm 65nm 45nm 32nmGate Length 350nm 200nm 130nm 70nm 50nm 35nm 25nm 17nm

Voltage 2.5V 1.8V 1.5V 1.3V 1.1V 0.85V ? ?Wafer (mm) 200 200 200 200/300 300 300 300 300

Voltage Level Technology Trends

10/1995 2.5V JEDEC 8-5

02/1997 1.8V JEDEC 8-7

10/2000 1.5V JEDEC 8-11

05/2001 1.2V JEDEC 8-12

12/2001 1.0V JEDEC 8-14

Source : Texas Instrument Technology Roadmap

Joint Electron Device Engineering Council

The 1980-90’s Logic Family

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

Out

put

Vol

tage

(V

)

High

Low

5.0V

3.3V

2.4V

0.8V

0 1 Logic Level

2.5 Volt Logic - JEDEC 8-5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

Out

put

Vol

tage

(V

)

High

Low

1.7V

0.7V

0 1 Logic Level

5.0V

3.3V

Joint Electron Device Engineering Council

1.8 Volt Logic - JEDEC 8-7

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

Out

put

Vol

tage

(V

)

0 1 Logic Level

High

Low

0.65V

0.35V

5.0V

3.3V

Joint Electron Device Engineering Council

1.5 Volt Logic - JEDEC 8-11

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

Out

put

Vol

tage

(V

)

0 1 Logic Level

High

Low

0.65V

0.35V

5.0V

3.3V

Joint Electron Device Engineering Council

1.0 Volt Logic - JEDEC 8-14

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

Out

put

Vol

tage

(V

)

High

Low

0.65V

0.35V

0 1 Logic Level

5.0V

3.3V

Joint Electron Device Engineering Council

1.0 Volt Logic - JEDEC 8-14

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

Out

put

Vol

tage

(V

)

Maximum High

Minimum Low

0.65V

0.35V

0 1 Logic Level

Maximum High = 200mV above VDDMaximum Low = -200mV below GND

5.0V

3.3V

Joint Electron Device Engineering Council

What Are the Issues?

• V - Voltage:– 1.0 Volt Logic

• 200mV below GND and 200mV above VDD ---- JEDEC

– 1.5 & 1.8 Volt Logic

• 300mV below GND and 300mV above VDD ---- JEDEC

– Intel AGTL signal

• 350mV for Intel AGTL signal for only 10nS

• 500mV for 15pS

• I - Current:– 90nm technology

• No more than 100mA through each output

Joint Electron Device Engineering Council

Outside the Safe Operating Area?

• Over-Voltage and Over-Current Failure– These failures taken place in milliseconds - once the second breakdown

region has been reached, the transistor will enter a negative resistance state, and there is nothing that will prevent total failure.

ON Semiconductor

Newer Parts Are More Sensitive to Over-Voltage Conditions

• As core and I/O

Voltages decrease, so

must the transistor

gate oxide thickness

• Thinner oxides break

down at lower

voltages

Graph is for a 100ppm failure rate

90nm Generation Gate Oxide

Gate Oxide is less than 5 atomic layers

1.2nm Thick

Leakage through the silicon dioxide layer of a gate increases exponentially as its thickness decreases. Nevertheless, making the dielectric ever thinner is necessary in order to meet increasing performance goals. When the gate dielectric of a transistor thins, its insular quality decreases and current leaks through it. Uncontrolled, this conduction causes the transistor to stray from its purely "on" and "off" state and into an "on" and "leaky off" behavior. The effect is similar to that of a light bulb that lights fully when turned on but only dims when you turn the light switch off.

Newer Parts Are More Sensitive to Over-Voltage Conditions (SOA)

Safety Limits for 1.2V AGTL Logic

1.4

1.45

1.5

1.55

1.6

1.65

1.7

1.75

1.8

0 2 4 6 8 10Overvoltage Time (nsec)

Sig

nal V

olta

ge (V

)

5nsec clock

50nsec clock

• Today’s processors

have strict over-

voltage/time

specification

• AGTL signals

should not exceed

1.8V, always for <

10nsec

Source : Intel Corp. Itanium 2 processor datasheet

Over-Current-Related Failures

• Bondwire fusing or bambooing

• Die metallization failure

(Joule heating)

Over-Voltage-Related Failures

• CMOS latch-up– A self sustaining short from VDD to GND

Over-Voltage-Related Failures

• Gate oxide breakdown, time dependent dielectric breakdown (TDDB)– Time Dependent Breakdown of Ultrathin Gate Oxide

• By Abdullah M. Yassine, Member, IEEE, H. E. Nariman, Member, IEEE, Michael McBride, Mirac Uzer, Member, IEEE,and Kola R. Olasupo, Member, IEEE

Photos Rohm Electronics

Over-Voltage-Related Failures

• Electrostatic Discharge (ESD) damage– Damaged Protection diode

What does this mean for Electrical Test

• In-circuit– Tight control of voltage and current

– Minimize Noise

• Fixture, Feedback etc

• Functional Test– Tight control of voltage and current

– Minimize Noise

• Boundary Scan and BIST– Minimize Noise

• Ground Bounce

The Difficulty of Programming the Correct Voltage Levels

• Maximum Output drive current of 100mA at 0.6 Voltages– R = V/I ~ 6 Ohms

• Older Driver Output Impedance– ~ 5 Ohms

• Connection Resistance– Wire

– Relays

– Contact

– ~ 1 Ohm

5 Ohms Output Impedance +1 Ohm wiring, relay and contact resistance

Equivalent Output Resistance6 Ohms

1.2VDriver

0.6V

0.6V

Simple Voltage Divider

The Difficulty of Programming the Correct Voltage Levels

Actual example of a non custom design driver sensor

1.5V

710mVUnderLoad

DUT

High

80mA

400mV

Vprog = 1.2V

(+/- 100mV)Driver

Backdriven Part

0.62V

Low

5 Ohm

1.2V Logic

The Difficulty of Programming the Correct Voltage Levels

100mV

Vprog = 1.2V

(+/- 100mV)Driver

20mV

80mV

5 Ohm 1 Ohm

1 Ohm

0.98V20mA

1.2V Logic

DUT

High

80mA

400mV

Vprog = 1.7V

(+/- 100mV)Driver

Backdriven Part

5 Ohm

1.2V Logic

The Difficulty of Programming the Correct Voltage Levels

100mV

Vprog = 1.7V

(+/- 100mV)Driver

20mV

80mV

5 Ohm 1 Ohm

1 Ohm

20mA

Low

1.2V Logic

1.12V1.68V

The Difficulty of Programming the Correct Voltage Levels

For 4 logic families you may need 8 sensor levels to measure both inputs and outputs voltages

1.0V

1.2V

1.5V

1.8V

1.8V

1.5V

1.0V

1.2V

1.7V

1.4V

2.2V

1.9V

High impedance in-circuit drivers, require different programmed outputs to match the device output currents.

Backdriven currents could range from 80mA’s to 500mA’s

DUT

High

20mA

100mV

Vprog = 1.2V

(+/- 100mV)Driver

Backdriven Part

5 Ohm

1.2V Logic

The Difficulty of Programming the Correct Voltage Levels

100mV

Vprog = 1.2V

(+/- 100mV)Driver

20mV

20mV

5 Ohm 1 Ohm

1 Ohm

20mA

1.2V LogicDUT

Low

0.98V

DUT

High

80mA

400mV

Vprog = 1.2V

(+/- 100mV)Driver

Backdriven Part

5 Ohm

1.2V Logic

The Difficulty of Programming the Correct Voltage Levels

100mV

Vprog = 1.2V

(+/- 100mV)Driver

20mV

80mV

5 Ohm 1 Ohm

1 Ohm

20mA

DUT

Low

1.2V Logic

0.62V

Spikes Are Caused By Changing States

•Uncontrolled Voltage Spikes result from outputs changing while they are being backdriven

DUT

Isolation,Force a Logic high

Stimulus MeasurementBackdriven Part

•Example:When back driving a low to a high and the back driven output changes, the out signal now re-enforces the back drive level and the current has to go from a positive current to zero.

V = L x I t

Can cause CMOS latch-up failures or TDDB

Example: Greater than 9V Voltage Spike Measured!

Spikes Are Caused By Changing States

Tri-stated or Back-driven?

• With complex devices can we really be sure that our big devices are tri-state?

• Tri-state back-drive <10mA

• Output back-drive >80mA

• Limits of 100mA?

Tri-stated or Back-driven?

• An analysis of a typical in-circuit test program of a PC motherboard found that back-driving occurred during 30% of the digital device tests.

• A total of 156 back-driving events requiring greater than 50mA of back-driving current were recorded.

• Median back-drive current– 176mA.

• Highest back-drive current– 600mA.

• Longest back-drive duration– 2.5mS.

Functional Test

• Functional Test– Tight control of voltage and current

• Low impedance and feedback

– Minimize Noise

• Fixture design

• Boundary Scan and BIST– External circuits will need to match logic families

– Minimize Noise

• Fixture and interface design

• Ground Bounce

Potential Impact

• Damaged or Stressed Components – Catastrophic or latent failures related to

• Gate Oxide Breakdown

• ESD Diode overstress

• CMOS Latch-up

• Reduced Fault Coverage– Unable to test components without violating device specifications

• Increased False Failures– Needless replacement of good devices

– Cost of repair and associated retest

– Possible damage to product during repair

– Longevity of reworked product vs. product that is untouched

What Is Needed to Prevent Damage?

• Driver Voltage and Current Verification– Low impedance, closed loop measurement

• Per Pin Programmable Voltage Levels– >5 logic families per device ( 1.0,1.2,1.5,1.8,2.5 and 3.3)

• Hardware Back-drive Limits for both Current and Time– 100mA’s maximum or ANY limit that is considered safe

• High Speed Digital Controller– Minimize test time

• Multi level Software Isolation– Eliminate noise, clocks and feedback loops.

Technical Papers • Reliability limits for the gate insulator in CMOS technology

– By J. H. Stathis

• CMOS scaling beyond the 100-nm node with silicondioxide-based gate dielectrics

– By E. Y. Wu,E. J. Nowak,A. Vayshenker,W. L. Lai,D. L. Harmon

• Degradation and Breakdown of Thin Silicon Dioxide Films Under Dynamic Electrical Stress

– Montserrat Nafr´ıa, Jordi Su˜n´e, David Y´elamos, and Xavier Aymerich

• Time Dependent Breakdown of Ultrathin Gate Oxide– By Abdullah M. Yassine, Member, IEEE, H. E. Nariman, Member, IEEE, Michael

McBride, Mirac Uzer, Member, IEEE,and Kola R. Olasupo, Member, IEEE

• Issues and Challenges of Testing Modern Low Voltage Technologies with Traditional In-circuit Testers

– Alan Albee, APEX 2004

“Impact of Low-Voltage Devices on Test and Inspection”

Teradyne Assembly Test Division Website: www.teradyne.com/cbti

Michael J SmithMichael.J.Smith@Teradyne.com

http://www.teradyne.com/prods/cbt/webinar_lvd_survey.html