the fe-i4 pixel readout system-on-chip for atlas experiment upgrades
DESCRIPTION
The FE-I4 Pixel Readout System-on-Chip for ATLAS Experiment Upgrades. Tomasz Hemperek on behalf of ATLAS Pixel Collaboration. ATLAS Detector. Pixel Detector: 3 barrels 1 12 stave s 1744 modules 80 million channels. Existing B-layer. IBL. Beam pipe. - PowerPoint PPT PresentationTRANSCRIPT
The FE-I4 Pixel Readout System-on-Chip for ATLAS Experiment Upgrades
Tomasz Hemperek on behalf of ATLAS Pixel Collaboration
Tomasz Hemperek, University of Bonn @ TWEPP 20102
ATLAS Detector
21/09/2010
Pixel Detector: 3 barrels 112 staves 1744 modules 80 million channels
IBL = New Insertable B-Layer at 33 mm
IBL
Beam pipe
Existing B-layer
Tomasz Hemperek, University of Bonn @ TWEPP 20103
Current Pixel Detector Module
21/09/2010
16-front-end chip (FE-I3) module with a module controller chip (MCC)
Planar n-on-n DOFZ silicon sensors, 250 μm thick
Designed for for 1 x 1015 1MeV neq fluence and 50 MRad
Tomasz Hemperek, University of Bonn @ TWEPP 20104
Front End ChipFE-I3 FE-I4
21/09/2010
Pixel Size [μm2] 50×400 50×250 Pixel Array 18×160 80×336 Chip Size [mm2] 7.6×10.8 20.2×19.0 Active Fraction 74 % 89 % Output Data Rate [Mb/s] 40 160 Transistor Count [M] - ~80
2mm
16.8
mm
8mm
2.8m
m
7.6mm
20.2mm
Tomasz Hemperek, University of Bonn @ TWEPP 20105
Double Hit Column Waiting (FE-I3)
21/09/2010
Inefficiencies
ToT
Vth
Lost LE
Time over Threshold ~Q
Vth
LE
1. Record2. Transfer3. Trigger4. Transmit
Tomasz Hemperek, University of Bonn @ TWEPP 20106
Motivation
21/09/2010
0.1 0.2 0.3 0.4 0.5
0.600
0000
0000
0001
0.700
0000
0000
0001 0.8 0.9 1 1.5 2 2.5 3 3.5 4 4.5 5
0%
20%
40%
60%
80%
100%
Inefficiency for FE-I3 at 3.7cm
Total Double HitWrong Bunch Crossing Busy Pixel
Hit probability per Double-Column
LHC
IBL SL
HC
Tomasz Hemperek, University of Bonn @ TWEPP 20107
New FE improvements
21/09/2010
New technology Smaller pixel size Bigger chip size and active area New digital architecture New analog pixel Reduce number of external components New powering schemes Decrease cost (per area) Better radiation hardness
Tomasz Hemperek, University of Bonn @ TWEPP 20108
FE-I4 Functional Overview
21/09/2010
Pads / RX /TX
Double Column
End Of Chip Logic Data Output Block Phase Lock Loop Command Decoder SEU-Hard Memory DACs & Reference Power
4 Pixel Region
Pixel Array
Tomasz Hemperek, University of Bonn @ TWEPP 20109
Analog Pixel
21/09/2010
150 mm
50 mm
Cc
Cf2Cf1
Preamp Amp2
feedbox feedbox
Inj0
Inj1
injectIn
Cinj1
Cinj2
+local
feedback tune
FDAC4 Bit
Vfb
+local
thresholdtune
TDAC5 Bit
Vfb2
+
-
HitOutNotKill
Vth
Two-stage architecture optimized for low power, low noise and fast rise time
Additional gain Cc/Cf2~ 6 More flexibility on choice of Cf1 Charge collection less
dependent on detector capacitor
Decoupled from preamplifier DC potential shift caused by leakage
Local DACs for tuning feedback current and global threshold
Charge injection circuitryPreamp
Am
p2
FDAC
TDAC
discri
Tomasz Hemperek, University of Bonn @ TWEPP 201010
FE-I4-P1 (Prototype)
21/09/2010
61x14 pixel array Silicon proven RadHARD up to 200MRad
(loaded ~400 fF)
<ENC> = ~65 e
Noise Measurements
Noise Measurements (Irradiation)
Tomasz Hemperek, University of Bonn @ TWEPP 201011
4 Pixel Region
21/09/2010
- Analog - Digital
1 2 3 4 5 60
5000
10000
15000
20000
25000
30000central module - direction
Mean: 1.76
Cluster size projection
1 2 3 4 5 60
5000
10000
15000
20000
25000
30000central module - Z direction
Mean: 1.87 4 analog pixels are connected to one digital region
Analog pixels can operate and be tested independently from digital part
Pixel organization
Tomasz Hemperek, University of Bonn @ TWEPP 201012
Digital Region (simplified)
21/09/2010
- Hit Processing- ToT Counter- ToT Memory- Latency Counter- Triggering/Readout
Receiving hit
Start ToT counter Assign first free memory and
latency counter Generate trailing edge Store ToT value Check for trigger when
latency counter finished Indicate ready to read status
(release token)
Release memory after read
Read memory
Generate leading edge
Tomasz Hemperek, University of Bonn @ TWEPP 201013
Regional Buffer Overflow FE-I4 Inefficiency (3.7cm)
21/09/2010
FE-I4 Inefficiency
MemoriesSimulation
IBL 10xLHC
5 0.047% 2.19%
6 0.011% 0.65%
7 <0.01% 0.16%
Series10%
1%
2%
3%
4%
Total Double Hit Buffer Overflow
Hit probability per pixelLH
C IBL
SLHC
Mean ToT = 4
Tomasz Hemperek, University of Bonn @ TWEPP 201014
Column Readout
21/09/2010
TokenBus
End of Chip Logic
Two prioritized token scenario (column and periphery level)
One data bus End of column logic selects
column to read Chip control logic controls
trigger and read Data is always read in the
same order All buses including address
(thermal encoded) protected with hamming encoding
Tomasz Hemperek, University of Bonn @ TWEPP 201015
Pixel Array Layout
21/09/2010
Digital Region
Analog Pixel
50x250mm
16
Framing / Transmission
21/09/2010Tomasz Hemperek, University of Bonn @ TWEPP 2010
Re-
Form
attin
g
Eve
nt B
uild
er
Asy
nchr
onou
s re
dund
ant F
IFO
(8
x32b
it)
8b10
b E
ncod
ing
Fram
ing
Ser
ializ
er
Readout Control
Dat
a S
witc
h
Hamming Encoded Pixel Data
Header
Service
TX
40MHz Clock Domain160MHz Clock Domain
Re-formatting: Data reduction about 25% and 8-bit word format
Ham
min
g D
ecod
er
Tomasz Hemperek, University of Bonn @ TWEPP 201017
DC/DC
Serial Power
21/09/2010
Powering
Shunt LDO
FE-I41.2V1.5V Shunt LDO
Shunt LDO
FE-I41.2V1.5V Shunt LDO
IinIout
2x DC/DC LDO
FE-I4 1.2V1.5V
3.3V
2x DC/DC LDO
FE-I4 1.2V1.5V
Saving cable material budget
Reduction of cable power losses
Tomasz Hemperek, University of Bonn @ TWEPP 201018
New Module Concept
21/09/2010
Sensor technology independent. Decision on sensors after prototyping with FE-
I4 Minimum amount of external components
FE-I4
Sensor
Flex
Tomasz Hemperek, University of Bonn @ TWEPP 201019
Design Flow
21/09/2010
Design in “big A small D” methodology Blocks designed and verified individually Full chip digital and mixed-signal verification Work synchronization with integrated Revision Control System Big chip = many difficulties with software and PDK!
Analog Block Design & Verification
Digital Block Design & Verification
Integration
Full Chip Verification
Tomasz Hemperek, University of Bonn @ TWEPP 201020
Verification
21/09/2010
Full chip verification based on Open Verification Methodology (OVM) with multiple physics based and random test
ANALOGARRAY
(digital part)
DIGITALARRAY
END OF COLUMN
END OF CHIP
COMMAND DECODER
REGISTER MEMORYPLL
PLL
DATA OUTPUT
- verilog model- Implementation (RTL/gate)
FE-I4
DETECTOR(PIX)
OUTPUT(RECEIVE
)
MANUAL
SLOW COMMAND
(CMD)
Modeling Interfaces
Tomasz Hemperek, University of Bonn @ TWEPP 201021
Conclusion
21/09/2010
Project duration: ~3 years Design team: ~21 persons+
FE-I4A last official shipping date: This Thursday (23rd September 2010) Test setup readiness ramping-up, on time for IC back Tests: Wafer, single-chip, bump-bonded (planar, 3D, diamond), irradiation
Design teamBonn: D. Arutinov, M. Barbero, T. Hemperek, A. Kruth,
M. KaragounisCPPM: D. Fougeron, F. Gensolen, M. MenouniGenova: R. Beccherle, G. DarboLBNL: S. Dube, D. Elledge, J. Fleury (LAL),
M. Garcia-Sciveres, D. Gnani, F. Jensen, A. MekkaouiNIKHEF: V. Gromov, R. Kluit, J.D. Schipper, V. Zivkovic
Tomasz Hemperek, University of Bonn @ TWEPP 201022
Extra Slides
21/09/2010
Tomasz Hemperek, University of Bonn @ TWEPP 201023
Test Chips
21/09/2010
FE-I4-P1
LDORegulator
ChargePump
CurrentReference
DACs
Con
trol
Blo
ckC
apac
itanc
eM
easu
rem
ent
FE-I4-P161x14 Array
SEU test IC
4-LVDS Rx/Tx
ShuLDO+trist LVDS/LDO/10b-
DAC
turboPLL: PLL core + PRBS +
8b10b coder + LVDS driv
low power discri.
Tomasz Hemperek, University of Bonn @ TWEPP 201024
Clocking
21/09/2010
Phase Lock Loop (PLL) type 2
Voltage Controlled Oscillator (VCO) at 640 MHz (x16)
Lost of Lock Detection 2 Independent output
multiplexers Silicon Proven
Tomasz Hemperek, University of Bonn @ TWEPP 2010
LVDS TX LVDS RX
21/09/201025
Data Transmission
M3 M4
M5 M6
CMFBCMOSdriver
D
D
D
VofsVcm
Vbp
Vbn
5pF
5pF
100k 100k
TX
TX
M11 M12 M13 M14
M8
M9 M10
M4 M5 M6 M7
M1
M2 M3
RX RX
M14
M15 M16
M18M17
OUT
M20M19
M21 M22
Transition speed up to 330 MHz RadHARD up to 200MRad Silicon Proven
Tomasz Hemperek, University of Bonn @ TWEPP 201026
Shunt-LDO
21/09/2010
+ -
+
-
+
-
Iin
Iout
Vref
Vout
A1
A2
A3
M1M2
M3
M4
M5
R1
R2
Vin
Iload
R3
M6
Ishunt
Combination of LDO and shunt transistor „Shunt-LDO“ regulators having completely different output voltages can
be placed in parallel without any problem regarding mismatch & shunt current distribution
„Shunt-LDO“ can cope with an increased supply current if one FE-I4 does not contribute to shunt current e.g. disconnected wirebond
Can be used as an ordinary LDO when shunt is disabled Silicon Proven
Tomasz Hemperek, University of Bonn @ TWEPP 201027
RadHARD Memory
21/09/2010
Silicon Proven RadHARD and SEU Tolerant