Wire Bonding and Analogue Readout

● Cold bump bonding is not easy● Pixel chip is not reusable

● FE-I3 is not available at the moment● FE-I4 is coming -> 2 readout versions: Old (no spares) Temporary (many changes, limited maintenance)

● Reduced data set (TDAQ = demonstrator / production tool)

Instrument for research is needed

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Signal Routing for the Wire Bonding

column-wise using M2 (original proposal)

signal wires must not extend beyond the guard ring

● 0 < cluster size < 400 um – readout every 8th pixel● Minimum 8 bond pads / span (300 um) -> staggering

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row-wise:

● Better solution for the AC readout● Constant pitch for the bonding pads● M2 / Poly could be used (RD-50)

odd channels are read

out from the left side,

even channels – from

the right side

Signal Routing for the Wire Bonding

● Signal traces are orthogonal to the

bias line to reduce parasitic effects● 50 um pitch between signal traces reduces the inter-channel X-talk

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Analogue ReadoutaLiBaVa (Beetle V1.5)

H1(APC128 PSI 19)

Readout chip is usually designed for the AC coupling of strip sensors

- it usually tolerates high detector capacitance

- should tolerate high leakage current (typical limit ~500nA

-> 5...8 pixels in parallel after 10e+15 N/cm^2)

stand-alone system based on the USB interface

VME-based: uses FADC+RIO2

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Geometry: N rows, M columnsN rows = 128 (ASIC's readout channels)

= 160 (compartible with the FE-I3)

M columns =14 (7 pixels in parallel)

- Max: should not be too high

(limited by leakage current)

- Min: the bias ring should be

outside the FE-I3 dice (7.4 mm)

160 x 14:

128x14 pixels with wire bond pads,

readout by FE-I3 / Beetle

32x14 pixels without wire bond pads,

readout by FE-I3 only

160x4 FE-I3 channels without C-load

good configurationfor the noise studies

Sensor size corresponds to 160x18 pixel matrix (FE-I3),

Wire bond pads are placed instead of 2 outer column pairs.

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Design Variances

AC-coupling:M1 is needed as a field plate & for bump bonding

M1-M2 (0.1 fF/um^2) 24 um x 350 um -> 1 pF

similar to the pixel capacitance of 0.4 pF, but not

a problem: Xc (@10 Mhz) ~ 10 k << Rbias

Punchthrough biasing:

● p-spray only to form a

conductive channel● p-spray + p-stop

(smearing of implants is

critical for proper work)

a.) to be simulated in TCAD b.) “efforts and failures”Page 6

Guard rings: CMS: variable distance, constant width

ATLAS: variable width & distance

Hybridisation

replaceable sensor

● Optimisation of the sensor size (NxM pixels) to finish the PCB design● Design tool: Eagle Light (freeware), PCB ~60 Eur (inc. components)● Need help with manufacturing of pitch adapters (PA)

ASICs are “stationary”

- could be calibrated to a high precision

- same conditions for all measurements

http://ific.uv.es/~rmarco/Schematics/Daughter Board/

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Pitch Adapter

1 chip -> 10 sensors (PA only) -> 190 sensors (PA + patch) -> 3610 (PA + 2 patches)

● Aluminium on glass substrate● saw or laser cut● to be produced by CNM

capacitance ~ 0.3 pF / cm

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Applications

● Charge collection measurementsusing Beta-source:

Beam Test

EUDET package:● Monoenergetic MIPs ● Trigger, Telescope● Magnetic field, Cooling

& lunches ...

● Charge sharing● Geometric efficiency● Spatial resolution

Page 9 let's make friends !

Summary

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Our research requires some standard framework that we offer:

Technology proof: Compare foundries using the “standard” geometry competition = compartmentalisation (risk management)

Planar sensor design: Process engineering / Layout features collaboration = knowledge database, common structures